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1380 lines
37 KiB
1380 lines
37 KiB
/*++
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Copyright (c) 1997 Microsoft Corporation
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Module Name:
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ixcmos.c
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Abstract:
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Implements CMOS op region interface functionality
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Author:
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brian guarraci (t-briang) 07-14-2000
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Environment:
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Kernel mode only.
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Revision History:
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--*/
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#include "halp.h"
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#include "acpitabl.h"
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#include "exboosts.h"
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#include "wchar.h"
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#include "xxacpi.h"
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#ifdef ACPI_CMOS_ACTIVATE
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//
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// prototypes for the 2 HalpGet/Set ixcmos.asm functions
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//
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ULONG
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HalpGetCmosData(
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IN ULONG SourceLocation,
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IN ULONG SourceAddress,
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IN PUCHAR DataBuffer,
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IN ULONG ByteCount
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);
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ULONG
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HalpSetCmosData(
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IN ULONG SourceLocation,
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IN ULONG SourceAddress,
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IN PUCHAR DataBuffer,
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IN ULONG ByteCount
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);
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ULONG
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HalpcGetCmosDataByType(
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IN CMOS_DEVICE_TYPE CmosType,
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IN ULONG SourceAddress,
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IN PUCHAR DataBuffer,
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IN ULONG ByteCount
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);
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ULONG
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HalpcSetCmosDataByType(
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IN CMOS_DEVICE_TYPE CmosType,
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IN ULONG SourceAddress,
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IN PUCHAR DataBuffer,
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IN ULONG ByteCount
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);
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ULONG
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HalpReadCmosDataByPort(
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IN ULONG AddrPort,
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IN ULONG DataPort,
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IN ULONG SourceAddress,
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IN PUCHAR ReturnBuffer,
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IN ULONG ByteCount
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);
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ULONG
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HalpWriteCmosDataByPort(
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IN ULONG AddrPort,
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IN ULONG DataPort,
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IN ULONG SourceAddress,
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IN PUCHAR ReturnBuffer,
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IN ULONG ByteCount
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);
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ULONG
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HalpReadCmosData(
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IN ULONG SourceLocation,
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IN ULONG SourceAddress,
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IN ULONG ReturnBuffer,
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IN PUCHAR ByteCount
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);
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ULONG
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HalpWriteCmosData(
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IN ULONG SourceLocation,
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IN ULONG SourceAddress,
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IN ULONG ReturnBuffer,
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IN PUCHAR ByteCount
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);
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ULONG
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HalpReadStdCmosData(
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IN ULONG SourceAddress,
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IN PUCHAR ReturnBuffer,
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IN ULONG ByteCount
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);
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ULONG
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HalpWriteStdCmosData(
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IN ULONG SourceAddress,
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IN PUCHAR ReturnBuffer,
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IN ULONG ByteCount
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);
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ULONG
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HalpReadRtcStdPCAT(
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IN ULONG SourceAddress,
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IN PUCHAR ReturnBuffer,
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IN ULONG ByteCount
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);
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ULONG
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HalpWriteRtcStdPCAT(
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IN ULONG SourceAddress,
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IN PUCHAR ReturnBuffer,
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IN ULONG ByteCount
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);
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ULONG
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HalpReadRtcIntelPIIX4(
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IN ULONG SourceAddress,
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IN PUCHAR ReturnBuffer,
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IN ULONG ByteCount
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);
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ULONG
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HalpWriteRtcIntelPIIX4(
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IN ULONG SourceAddress,
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IN PUCHAR ReturnBuffer,
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IN ULONG ByteCount
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);
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ULONG
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HalpReadExtCmosIntelPIIX4(
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IN ULONG SourceAddress,
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IN PUCHAR ReturnBuffer,
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IN ULONG ByteCount
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);
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ULONG
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HalpWriteExtCmosIntelPIIX4(
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IN ULONG SourceAddress,
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IN PUCHAR ReturnBuffer,
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IN ULONG ByteCount
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);
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ULONG
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HalpReadRtcDal1501(
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IN ULONG SourceAddress,
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IN PUCHAR ReturnBuffer,
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IN ULONG ByteCount
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);
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ULONG
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HalpWriteRtcDal1501(
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IN ULONG SourceAddress,
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IN PUCHAR ReturnBuffer,
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IN ULONG ByteCount
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);
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ULONG
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HalpReadExtCmosDal1501(
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IN ULONG SourceAddress,
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IN PUCHAR ReturnBuffer,
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IN ULONG ByteCount
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);
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ULONG
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HalpWriteExtCmosDal1501(
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IN ULONG SourceAddress,
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IN PUCHAR ReturnBuffer,
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IN ULONG ByteCount
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);
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//
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// at the time of this writing, the largest known cmos ram address is 0xff
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// that is, for a given cmos ram bank, the largest address is 0xff
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//
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typedef enum {
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LARGEST_KNOWN_CMOS_RAM_ADDRESS = 0xff
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} CMOS_RAM_ADDR_LIMITS;
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//
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// Additional information about Standard CMOS/RTC can be acquired at:
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//
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// "ISA System Architecture" Mindshare, Inc. (ISBN:0-201-40996-8) Chaper 21.
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//
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// To put the registers and the RTC region in context, the following
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// constants describe the layout of the registers (0x00 - 0x0d).
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// Registers A-D are control registers which affect the state of the rtc.
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//
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typedef enum {
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CMOS_RAM_STDPCAT_SECONDS = 0,
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CMOS_RAM_STDPCAT_SECONDS_ALARM,
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CMOS_RAM_STDPCAT_MINUTES,
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CMOS_RAM_STDPCAT_MINUTES_ALARM,
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CMOS_RAM_STDPCAT_HOURS,
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CMOS_RAM_STDPCAT_HOURS_ALARM,
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CMOS_RAM_STDPCAT_DAY_OF_WEEK,
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CMOS_RAM_STDPCAT_DATE_OF_MONTH,
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CMOS_RAM_STDPCAT_MONTH,
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CMOS_RAM_STDPCAT_YEAR,
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CMOS_RAM_STDPCAT_REGISTER_A,
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CMOS_RAM_STDPCAT_REGISTER_B,
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CMOS_RAM_STDPCAT_REGISTER_C,
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CMOS_RAM_STDPCAT_REGISTER_D
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} CMOS_RAM_STDPCAT_REGISTERS;
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//
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// definition of bits with in the control registers
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//
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typedef enum {
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//
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// (Update In Progress)
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// when the rtc is updating the rtc registers, this bit is set
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//
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//
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CMOS_RAM_STDPCAT_REGISTER_A_UIP_BIT = 0x80,
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//
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// this bit must be set when updating the rtc
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//
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CMOS_RAM_STDPCAT_REGISTER_B_SET_BIT = 0x80
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} CMOS_RAM_STDPCAT_REGISTER_BITS;
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//
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// Additional information about the Intel PIIX4 cmos/rtc chip
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// can be acquired at:
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//
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// http://developer.intel.com/design/intarch/DATASHTS/29056201.pdf
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//
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// To put the registers and the RTC region in context, the following
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// constants describe the layout of the
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//
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// Intel PIIX4 CMOS ram
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//
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// for the 0x00 - 0x0d registers. Registers A-D are control registers
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// which affect the state of the rtc.
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//
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//
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//
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typedef enum {
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CMOS_RAM_PIIX4_SECONDS = 0,
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CMOS_RAM_PIIX4_SECONDS_ALARM,
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CMOS_RAM_PIIX4_MINUTES,
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CMOS_RAM_PIIX4_MINUTES_ALARM,
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CMOS_RAM_PIIX4_HOURS,
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CMOS_RAM_PIIX4_HOURS_ALARM,
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CMOS_RAM_PIIX4_DAY_OF_WEEK,
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CMOS_RAM_PIIX4_DATE_OF_MONTH,
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CMOS_RAM_PIIX4_MONTH,
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CMOS_RAM_PIIX4_YEAR,
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CMOS_RAM_PIIX4_REGISTER_A,
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CMOS_RAM_PIIX4_REGISTER_B,
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CMOS_RAM_PIIX4_REGISTER_C,
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CMOS_RAM_PIIX4_REGISTER_D
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} CMOS_RAM_PIIX4_REGISTERS;
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//
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// definition of bits with in the control registers
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//
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typedef enum {
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//
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// (Update In Progress)
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// when the rtc is updating the rtc registers, this bit is set
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//
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//
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CMOS_RAM_PIIX4_REGISTER_A_UIP_BIT = 0x80,
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//
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// this bit must be set when updating the rtc
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//
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CMOS_RAM_PIIX4_REGISTER_B_SET_BIT = 0x80
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} CMOS_RAM_PIIX4_REGISTER_BITS;
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//
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// Additional information about the Dallas 1501 cmos/rtc chip
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// can be acquired at:
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//
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// http://www.dalsemi.com/datasheets/pdfs/1501-11.pdf
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//
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// To put the registers and the RTC region in context, the following
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// constants describe the layout of the
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//
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// Dallas 1501 CMOS ram
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//
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// for the 0x00 - 0x0d registers. Registers A-D are control registers
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// which affect the state of the rtc.
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//
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//
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//
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typedef enum {
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CMOS_RAM_DAL1501_SECONDS = 0,
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CMOS_RAM_DAL1501_MINUTES,
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CMOS_RAM_DAL1501_HOURS,
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CMOS_RAM_DAL1501_DAY,
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CMOS_RAM_DAL1501_DATE,
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CMOS_RAM_DAL1501_MONTH,
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CMOS_RAM_DAL1501_YEAR,
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CMOS_RAM_DAL1501_CENTURY,
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CMOS_RAM_DAL1501_ALARM_SECONDS,
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CMOS_RAM_DAL1501_ALARM_MINUTES,
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CMOS_RAM_DAL1501_ALARM_HOURS,
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CMOS_RAM_DAL1501_ALARM_DAYDATE,
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CMOS_RAM_DAL1501_WATCHDOG0,
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CMOS_RAM_DAL1501_WATCHDOG1,
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CMOS_RAM_DAL1501_REGISTER_A,
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CMOS_RAM_DAL1501_REGISTER_B,
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CMOS_RAM_DAL1501_RAM_ADDR_LSB, // 0x00 - 0xff
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CMOS_RAM_DAL1501_RESERVED0,
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CMOS_RAM_DAL1501_RESERVED1,
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CMOS_RAM_DAL1501_RAM_DATA // 0x00 - 0xff
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} CMOS_RAM_DAL1501_REGISTERS;
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typedef enum {
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//
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// The TE bit controls the update status of the external
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// RTC registers. When it is 0, the registers are frozen
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// with the last RTC values. If you modifiy the registers
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// while TE = 0, then when TE is set, the modifications
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// will transfer to the internal registers, hence modifying
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// the RTC state. In general, when TE is set, the external
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// registers then reflect the current RTC state.
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//
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CMOS_RAM_DAL1501_REGISTER_B_TE_BIT = 0x80
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} CMOS_RAM_DAL1501_REGISTER_BITS;
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#define MAX(a, b) ((a) > (b) ? (a) : (b))
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#define MIN(a, b) ((a) < (b) ? (a) : (b))
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typedef enum {
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CmosStdAddrPort = 0x70,
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CmosStdDataPort = 0x71
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};
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typedef enum {
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CMOS_READ,
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CMOS_WRITE
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} CMOS_ACCESS_TYPE;
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typedef
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ULONG
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(*PCMOS_RANGE_HANDLER) (
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IN ULONG SourceAddress,
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IN PUCHAR ReturnBuffer,
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IN ULONG ByteCount
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);
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typedef struct {
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ULONG start;
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ULONG stop;
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PCMOS_RANGE_HANDLER readHandler;
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PCMOS_RANGE_HANDLER writeHandler;
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} CMOS_ADDR_RANGE_HANDLER, *PCMOS_ADDR_RANGE_HANDLER;
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//
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// define the discrete ranges so that the appropriate
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// handlers can be used for each.
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//
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// Note: address ranges are inclusive
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//
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CMOS_ADDR_RANGE_HANDLER CmosRangeHandlersStdPCAT[] =
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{
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//
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// The RTC region
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//
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{0, 0x9, HalpReadRtcStdPCAT, HalpWriteRtcStdPCAT},
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//
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// The standard CMOS RAM region
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//
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{0x0a, 0x3f, HalpReadStdCmosData, HalpWriteStdCmosData},
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//
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// end of table
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//
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{0, 0, 0}
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};
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CMOS_ADDR_RANGE_HANDLER CmosRangeHandlersIntelPIIX4[] =
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{
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//
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// The RTC region
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//
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{0, 0x9, HalpReadRtcIntelPIIX4, HalpWriteRtcIntelPIIX4},
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//
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// The standard CMOS RAM region
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//
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{0x0a, 0x7f, HalpReadStdCmosData, HalpWriteStdCmosData},
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//
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// The extended CMOS SRAM region
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//
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{0x80, 0xff, HalpReadExtCmosIntelPIIX4, HalpWriteExtCmosIntelPIIX4},
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//
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// end of table
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//
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{0, 0, 0}
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};
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CMOS_ADDR_RANGE_HANDLER CmosRangeHandlersDal1501[] =
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{
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//
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// The RTC region
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//
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{0, 0x0b, HalpReadRtcDal1501, HalpWriteRtcDal1501},
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//
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// The standard CMOS RAM region
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//
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{0x0c, 0x0f, HalpReadStdCmosData, HalpWriteStdCmosData},
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//
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// NOTE: this table skips the standard CMOS range: 0x10 - 0x1f
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// because this area is reserved in the spec, and the is no
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// apparent reason why the op region should access this area.
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// Also, regs 0x10 and 0x13 are used to access the extended
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// ram, hence there is no reason why the op region should access
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// this either. Hence, all op region access beyond 0x0f are
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// interpretted as accesses into the Extended CMOS
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//
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//
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// The extended CMOS SRAM region
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//
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{0x10, 0x10f, HalpReadExtCmosDal1501, HalpWriteExtCmosDal1501},
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//
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// end of table
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//
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{0, 0, 0}
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};
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ULONG
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HalpCmosRangeHandler(
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IN CMOS_ACCESS_TYPE AccessType,
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IN CMOS_DEVICE_TYPE CmosType,
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IN ULONG Address,
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IN PUCHAR DataBuffer,
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IN ULONG ByteCount
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)
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{
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ULONG bytes; // bytes read in last operation
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ULONG offset; // the offset beyond the initial address
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ULONG bufOffset; // the index into the data buffer as we read in data
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ULONG extAddr; // the corrected address for accessing extended SRAM
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ULONG range; // the current address range we are checking for
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ULONG bytesRead; // total bytes successfully read
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ULONG length; // the length of the current operation read
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PCMOS_ADDR_RANGE_HANDLER rangeHandlers; // the table we are using
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//
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// get the appropriate table
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//
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switch (CmosType) {
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case CmosTypeStdPCAT:
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rangeHandlers = CmosRangeHandlersStdPCAT;
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break;
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case CmosTypeIntelPIIX4:
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rangeHandlers = CmosRangeHandlersIntelPIIX4;
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break;
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|
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case CmosTypeDal1501:
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rangeHandlers = CmosRangeHandlersDal1501;
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break;
|
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default:
|
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break;
|
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}
|
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bytesRead = 0;
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bufOffset = 0;
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range = 0;
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offset = Address;
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length = ByteCount;
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while (rangeHandlers[range].stop) {
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|
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if (offset <= rangeHandlers[range].stop) {
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//
|
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// get the # of bytes to read in this region
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//
|
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// length = MIN(remaining # bytes remaining to read, # bytes to read in the current range)
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//
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length = MIN((ByteCount - bytesRead), (rangeHandlers[range].stop - offset + 1));
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|
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//
|
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// Since the handler routines are only called from here, we can consolidate
|
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// the ASSERTIONS. This is also nice, because we know which range in the
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// table we are dealing with, hence we know what the limits should be.
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//
|
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// make sure both the offset into the range,
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// and the operation's length are in bounds
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//
|
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ASSERT(offset <= rangeHandlers[range].stop);
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ASSERT((offset + length) <= (rangeHandlers[range].stop + 1));
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|
|
|
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switch (AccessType) {
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|
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case CMOS_READ:
|
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bytes = (rangeHandlers[range].readHandler)(
|
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offset,
|
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&DataBuffer[bufOffset],
|
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length);
|
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break;
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|
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case CMOS_WRITE:
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bytes = (rangeHandlers[range].writeHandler)(
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offset,
|
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&DataBuffer[bufOffset],
|
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length);
|
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break;
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|
default:
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break;
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}
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|
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ASSERT(bytes == length);
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bytesRead += bytes;
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|
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//
|
|
// adjust offset based on the length of the last operation
|
|
//
|
|
offset += length;
|
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bufOffset += length;
|
|
}
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|
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//
|
|
// if offset is at or beyond specified range, then we are done
|
|
//
|
|
if (offset >= (Address + ByteCount)) {
|
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break;
|
|
}
|
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|
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//
|
|
// move to the next range
|
|
//
|
|
range++;
|
|
}
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|
|
ASSERT(bytesRead == ByteCount);
|
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|
|
return bytesRead;
|
|
}
|
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|
|
ULONG
|
|
HalpcGetCmosDataByType(
|
|
IN CMOS_DEVICE_TYPE CmosType,
|
|
IN ULONG Address,
|
|
IN PUCHAR DataBuffer,
|
|
IN ULONG ByteCount
|
|
)
|
|
{
|
|
return HalpCmosRangeHandler(
|
|
CMOS_READ,
|
|
CmosType,
|
|
Address,
|
|
DataBuffer,
|
|
ByteCount
|
|
);
|
|
}
|
|
|
|
ULONG
|
|
HalpcSetCmosDataByType(
|
|
IN CMOS_DEVICE_TYPE CmosType,
|
|
IN ULONG Address,
|
|
IN PUCHAR DataBuffer,
|
|
IN ULONG ByteCount
|
|
)
|
|
{
|
|
return HalpCmosRangeHandler(
|
|
CMOS_WRITE,
|
|
CmosType,
|
|
Address,
|
|
DataBuffer,
|
|
ByteCount
|
|
);
|
|
}
|
|
|
|
|
|
ULONG
|
|
HalpReadCmosDataByPort(
|
|
IN ULONG AddrPort,
|
|
IN ULONG DataPort,
|
|
IN ULONG SourceAddress,
|
|
IN PUCHAR ReturnBuffer,
|
|
IN ULONG ByteCount
|
|
)
|
|
/*++
|
|
This routine reads the requested number of bytes from CMOS using the
|
|
specified ports and stores the data read into the supplied buffer in
|
|
system memory. If the requested data amount exceeds the allowable
|
|
extent of the source location, the return data is truncated.
|
|
|
|
Arguments:
|
|
|
|
AddrPort : address in the ISA I/O space to put the address
|
|
|
|
DataPort : address in the ISA I/O space to put the data
|
|
|
|
SourceAddress : address in CMOS where data is to be read from
|
|
|
|
ReturnBuffer : address in system memory for return data
|
|
|
|
ByteCount : number of bytes to be read
|
|
|
|
Returns:
|
|
|
|
Number of bytes actually read.
|
|
|
|
Note:
|
|
|
|
This routine doesn't perform safety precautions when operating
|
|
in the RTC region of the CMOS. Use the appropriate RTC routine
|
|
instead.
|
|
|
|
--*/
|
|
{
|
|
ULONG offset;
|
|
ULONG bufOffset;
|
|
ULONG upperAddrBound;
|
|
|
|
upperAddrBound = SourceAddress + ByteCount;
|
|
|
|
ASSERT(SourceAddress <= LARGEST_KNOWN_CMOS_RAM_ADDRESS);
|
|
ASSERT(upperAddrBound <= (LARGEST_KNOWN_CMOS_RAM_ADDRESS + 1));
|
|
|
|
//
|
|
// NOTE: The spinlock is needed even in the UP case, because
|
|
// the resource is also used in an interrupt handler (profiler).
|
|
// If we own the spinlock in this routine, and we service
|
|
// the profiler interrupt (which will wait for the spinlock forever),
|
|
// then we have a hosed system.
|
|
//
|
|
HalpAcquireCmosSpinLock();
|
|
|
|
for (offset = SourceAddress, bufOffset = 0; offset < upperAddrBound; offset++, bufOffset++) {
|
|
|
|
WRITE_PORT_UCHAR((PUCHAR)AddrPort, (UCHAR)offset);
|
|
|
|
ReturnBuffer[bufOffset] = READ_PORT_UCHAR((PUCHAR)DataPort);
|
|
|
|
}
|
|
|
|
HalpReleaseCmosSpinLock();
|
|
|
|
return bufOffset;
|
|
}
|
|
|
|
ULONG
|
|
HalpWriteCmosDataByPort(
|
|
IN ULONG AddrPort,
|
|
IN ULONG DataPort,
|
|
IN ULONG SourceAddress,
|
|
IN PUCHAR ReturnBuffer,
|
|
IN ULONG ByteCount
|
|
)
|
|
/*++
|
|
This routine reads the requested number of bytes from CMOS using the
|
|
specified ports and stores the data read into the supplied buffer in
|
|
system memory. If the requested data amount exceeds the allowable
|
|
extent of the source location, the return data is truncated.
|
|
|
|
Arguments:
|
|
|
|
AddrPort : address in the ISA I/O space to put the address
|
|
|
|
DataPort : address in the ISA I/O space to put the data
|
|
|
|
SourceAddress : address in CMOS where data is to be read from
|
|
|
|
ReturnBuffer : address in system memory for return data
|
|
|
|
ByteCount : number of bytes to be read
|
|
|
|
Returns:
|
|
|
|
Number of bytes actually read.
|
|
|
|
Note:
|
|
|
|
This routine doesn't perform safety precautions when operating
|
|
in the RTC region of the CMOS. Use the appropriate RTC routine
|
|
instead.
|
|
|
|
--*/
|
|
{
|
|
ULONG offset;
|
|
ULONG bufOffset;
|
|
ULONG upperAddrBound;
|
|
|
|
upperAddrBound = SourceAddress + ByteCount;
|
|
|
|
ASSERT(SourceAddress <= LARGEST_KNOWN_CMOS_RAM_ADDRESS);
|
|
ASSERT(upperAddrBound <= (LARGEST_KNOWN_CMOS_RAM_ADDRESS + 1));
|
|
|
|
//
|
|
// NOTE: The spinlock is needed even in the UP case, because
|
|
// the resource is also used in an interrupt handler (profiler).
|
|
// If we own the spinlock in this routine, and we service
|
|
// the profiler interrupt (which will wait for the spinlock forever),
|
|
// then we have a hosed system.
|
|
//
|
|
HalpAcquireCmosSpinLock();
|
|
|
|
for (offset = SourceAddress, bufOffset = 0; offset < upperAddrBound; offset++, bufOffset++) {
|
|
|
|
WRITE_PORT_UCHAR((PUCHAR)AddrPort, (UCHAR)offset);
|
|
WRITE_PORT_UCHAR((PUCHAR)DataPort, (UCHAR)(ReturnBuffer[bufOffset]));
|
|
|
|
}
|
|
|
|
HalpReleaseCmosSpinLock();
|
|
|
|
return bufOffset;
|
|
}
|
|
|
|
|
|
ULONG
|
|
HalpReadStdCmosData(
|
|
IN ULONG SourceAddress,
|
|
IN PUCHAR ReturnBuffer,
|
|
IN ULONG ByteCount
|
|
)
|
|
{
|
|
return HalpReadCmosDataByPort(
|
|
CmosStdAddrPort,
|
|
CmosStdDataPort,
|
|
SourceAddress,
|
|
ReturnBuffer,
|
|
ByteCount
|
|
);
|
|
}
|
|
|
|
ULONG
|
|
HalpWriteStdCmosData(
|
|
IN ULONG SourceAddress,
|
|
IN PUCHAR ReturnBuffer,
|
|
IN ULONG ByteCount
|
|
)
|
|
{
|
|
return HalpWriteCmosDataByPort(
|
|
CmosStdAddrPort,
|
|
CmosStdDataPort,
|
|
SourceAddress,
|
|
ReturnBuffer,
|
|
ByteCount
|
|
);
|
|
}
|
|
|
|
|
|
ULONG
|
|
HalpReadRtcStdPCAT(
|
|
IN ULONG SourceAddress,
|
|
IN PUCHAR ReturnBuffer,
|
|
IN ULONG ByteCount
|
|
)
|
|
/*++
|
|
This routine handles reads into the standard PC/AT RTC range.
|
|
|
|
Arguments:
|
|
|
|
SourceAddress : address in CMOS where data is to be read from
|
|
|
|
ReturnBuffer : address in system memory for return data
|
|
|
|
ByteCount : number of bytes to be read
|
|
|
|
Returns:
|
|
|
|
Number of bytes actually read.
|
|
|
|
--*/
|
|
{
|
|
ULONG offset;
|
|
ULONG bufOffset;
|
|
ULONG status; // register status
|
|
ULONG uip; // update in progress bit
|
|
ULONG upperAddrBound;
|
|
|
|
upperAddrBound = SourceAddress + ByteCount;
|
|
|
|
//
|
|
// NOTE: The spinlock is needed even in the UP case, because
|
|
// the resource is also used in an interrupt handler (profiler).
|
|
// If we own the spinlock in this routine, and we service
|
|
// the profiler interrupt (which will wait for the spinlock forever),
|
|
// then we have a hosed system.
|
|
//
|
|
HalpAcquireCmosSpinLock();
|
|
|
|
//
|
|
// According to "ISA System Architecture"
|
|
// by Mindshare, Inc. (ISBN:0-201-40996-8) Chaper 21.
|
|
// the access method for reading standard PC/AT RTC is:
|
|
//
|
|
// 1. wait for the Update In Progress bit to clear
|
|
// this is bit 7 of register A
|
|
//
|
|
// 2. read
|
|
//
|
|
|
|
//
|
|
// wait until the rtc is done updating
|
|
//
|
|
do {
|
|
WRITE_PORT_UCHAR((PUCHAR)CmosStdAddrPort, CMOS_RAM_STDPCAT_REGISTER_A);
|
|
status = READ_PORT_UCHAR((PUCHAR)CmosStdDataPort);
|
|
uip = status & CMOS_RAM_STDPCAT_REGISTER_A_UIP_BIT;
|
|
} while (uip);
|
|
|
|
//
|
|
// read
|
|
//
|
|
for (offset = SourceAddress, bufOffset = 0; offset < upperAddrBound; offset++, bufOffset++) {
|
|
|
|
WRITE_PORT_UCHAR((PUCHAR)CmosStdAddrPort, (UCHAR)offset);
|
|
|
|
ReturnBuffer[bufOffset] = READ_PORT_UCHAR((PUCHAR)CmosStdDataPort);
|
|
|
|
}
|
|
|
|
HalpReleaseCmosSpinLock();
|
|
|
|
return bufOffset;
|
|
}
|
|
|
|
ULONG
|
|
HalpWriteRtcStdPCAT(
|
|
IN ULONG SourceAddress,
|
|
IN PUCHAR ReturnBuffer,
|
|
IN ULONG ByteCount
|
|
)
|
|
/*++
|
|
This routine handles writes into the standard PC/AT RTC range.
|
|
|
|
Arguments:
|
|
|
|
SourceAddress : address in CMOS where data is to be read from
|
|
|
|
ReturnBuffer : address in system memory for return data
|
|
|
|
ByteCount : number of bytes to be read
|
|
|
|
Returns:
|
|
|
|
Number of bytes actually read.
|
|
|
|
--*/
|
|
{
|
|
ULONG offset;
|
|
ULONG bufOffset;
|
|
ULONG status; // register status
|
|
ULONG uip; // update in progress bit
|
|
ULONG upperAddrBound;
|
|
|
|
upperAddrBound = SourceAddress + ByteCount;
|
|
|
|
//
|
|
// NOTE: The spinlock is needed even in the UP case, because
|
|
// the resource is also used in an interrupt handler (profiler).
|
|
// If we own the spinlock in this routine, and we service
|
|
// the profiler interrupt (which will wait for the spinlock forever),
|
|
// then we have a hosed system.
|
|
//
|
|
|
|
HalpAcquireCmosSpinLock();
|
|
|
|
//
|
|
// According to "ISA System Architecture"
|
|
// by Mindshare, Inc. (ISBN:0-201-40996-8) Chapter 21.
|
|
// the access method for writing to standard PC/AT RTC is:
|
|
//
|
|
// 1. wait for the Update In Progress bit (UIP) to clear,
|
|
// where UIP is bit 7 of register A
|
|
//
|
|
// 2. set the SET bit to notify the RTC that the registers
|
|
// are being updated. The SET bit is bit 7 of register B
|
|
//
|
|
// 3. update the rtc registers
|
|
//
|
|
// 4. clear the SET bit, notifying the RTC that we are done writing
|
|
//
|
|
|
|
//
|
|
// wait until the rtc is done updating
|
|
//
|
|
do {
|
|
WRITE_PORT_UCHAR((PUCHAR)CmosStdAddrPort, CMOS_RAM_STDPCAT_REGISTER_A);
|
|
status = READ_PORT_UCHAR((PUCHAR)CmosStdDataPort);
|
|
uip = status & CMOS_RAM_STDPCAT_REGISTER_A_UIP_BIT;
|
|
} while (uip);
|
|
|
|
//
|
|
// set the SET bit of register B
|
|
//
|
|
WRITE_PORT_UCHAR((PUCHAR)CmosStdAddrPort, CMOS_RAM_STDPCAT_REGISTER_B);
|
|
status = READ_PORT_UCHAR((PUCHAR)CmosStdDataPort);
|
|
status |= CMOS_RAM_STDPCAT_REGISTER_B_SET_BIT;
|
|
WRITE_PORT_UCHAR((PUCHAR)CmosStdAddrPort, CMOS_RAM_STDPCAT_REGISTER_B);
|
|
WRITE_PORT_UCHAR((PUCHAR)CmosStdDataPort, (UCHAR)(status));
|
|
|
|
//
|
|
// update the rtc registers
|
|
//
|
|
for (offset = SourceAddress, bufOffset = 0; offset < upperAddrBound; offset++, bufOffset++) {
|
|
|
|
WRITE_PORT_UCHAR((PUCHAR)CmosStdAddrPort, (UCHAR)offset);
|
|
WRITE_PORT_UCHAR((PUCHAR)CmosStdDataPort, (UCHAR)(ReturnBuffer[bufOffset]));
|
|
|
|
}
|
|
|
|
//
|
|
// clear the SET bit of register B
|
|
//
|
|
WRITE_PORT_UCHAR((PUCHAR)CmosStdAddrPort, CMOS_RAM_STDPCAT_REGISTER_B);
|
|
status = READ_PORT_UCHAR((PUCHAR)CmosStdDataPort);
|
|
status &= ~CMOS_RAM_STDPCAT_REGISTER_B_SET_BIT;
|
|
WRITE_PORT_UCHAR((PUCHAR)CmosStdAddrPort, CMOS_RAM_STDPCAT_REGISTER_B);
|
|
WRITE_PORT_UCHAR((PUCHAR)CmosStdDataPort, (UCHAR)(status));
|
|
|
|
|
|
HalpReleaseCmosSpinLock();
|
|
|
|
return bufOffset;
|
|
}
|
|
|
|
|
|
ULONG
|
|
HalpReadRtcIntelPIIX4(
|
|
IN ULONG SourceAddress,
|
|
IN PUCHAR ReturnBuffer,
|
|
IN ULONG ByteCount
|
|
)
|
|
/*++
|
|
This routine reads the RTC range for the Intel PIIX4 CMOS/RTC chip
|
|
|
|
Arguments:
|
|
|
|
SourceAddress : address in CMOS where data is to be read from
|
|
|
|
ReturnBuffer : address in system memory for return data
|
|
|
|
ByteCount : number of bytes to be read
|
|
|
|
Returns:
|
|
|
|
Number of bytes actually read.
|
|
|
|
--*/
|
|
{
|
|
|
|
//
|
|
// Use the access method for the Standard PC/AT since it is
|
|
// equivalent to the Intel PIIX4 access method.
|
|
//
|
|
|
|
return HalpReadRtcStdPCAT(
|
|
SourceAddress,
|
|
ReturnBuffer,
|
|
ByteCount
|
|
);
|
|
|
|
}
|
|
|
|
ULONG
|
|
HalpWriteRtcIntelPIIX4(
|
|
IN ULONG SourceAddress,
|
|
IN PUCHAR ReturnBuffer,
|
|
IN ULONG ByteCount
|
|
)
|
|
/*++
|
|
This routine handles writes into the RTC range for the Intel PIIX4 CMOS/RTC chip
|
|
|
|
Arguments:
|
|
|
|
SourceAddress : address in CMOS where data is to be read from
|
|
|
|
ReturnBuffer : address in system memory for return data
|
|
|
|
ByteCount : number of bytes to be read
|
|
|
|
Returns:
|
|
|
|
Number of bytes actually read.
|
|
|
|
--*/
|
|
{
|
|
|
|
//
|
|
// Use the access method for the Standard PC/AT since it is
|
|
// equivalent to the Intel PIIX4 access method.
|
|
//
|
|
|
|
return HalpWriteRtcStdPCAT(
|
|
SourceAddress,
|
|
ReturnBuffer,
|
|
ByteCount
|
|
);
|
|
|
|
}
|
|
|
|
ULONG
|
|
HalpReadExtCmosIntelPIIX4(
|
|
IN ULONG SourceAddress,
|
|
IN PUCHAR ReturnBuffer,
|
|
IN ULONG ByteCount
|
|
)
|
|
/*++
|
|
This routine reads the RTC registers for the Intel PIIX4 CMOS/RTC chip.
|
|
|
|
Arguments:
|
|
|
|
SourceAddress : address in CMOS where data is to be read from
|
|
|
|
ReturnBuffer : address in system memory for return data
|
|
|
|
ByteCount : number of bytes to be read
|
|
|
|
Returns:
|
|
|
|
Number of bytes actually read.
|
|
|
|
--*/
|
|
{
|
|
|
|
//
|
|
// The Intel PIIX4 Extended SRAM is accessed using
|
|
// next pair of IO ports above the standard addr/data ports.
|
|
// Hence, we can simply forward the request with the correct pair.
|
|
//
|
|
|
|
return HalpReadCmosDataByPort(
|
|
CmosStdAddrPort + 2,
|
|
CmosStdDataPort + 2,
|
|
SourceAddress,
|
|
ReturnBuffer,
|
|
ByteCount
|
|
);
|
|
}
|
|
|
|
ULONG
|
|
HalpWriteExtCmosIntelPIIX4(
|
|
IN ULONG SourceAddress,
|
|
IN PUCHAR ReturnBuffer,
|
|
IN ULONG ByteCount
|
|
)
|
|
/*++
|
|
This routine handles writes into the RTC registers for the Intel PIIX4 CMOS/RTC chip.
|
|
|
|
Arguments:
|
|
|
|
SourceAddress : address in CMOS where data is to be read from
|
|
|
|
ReturnBuffer : address in system memory for return data
|
|
|
|
ByteCount : number of bytes to be read
|
|
|
|
Returns:
|
|
|
|
Number of bytes actually read.
|
|
|
|
--*/
|
|
{
|
|
|
|
//
|
|
// The Intel PIIX4 Extended SRAM is accessed using
|
|
// next pair of IO ports above the standard addr/data ports.
|
|
// Hence, we can simply forward the request with the correct pair.
|
|
//
|
|
|
|
return HalpWriteCmosDataByPort(
|
|
CmosStdAddrPort + 2,
|
|
CmosStdDataPort + 2,
|
|
SourceAddress,
|
|
ReturnBuffer,
|
|
ByteCount
|
|
);
|
|
}
|
|
|
|
|
|
ULONG
|
|
HalpReadRtcDal1501(
|
|
IN ULONG SourceAddress,
|
|
IN PUCHAR ReturnBuffer,
|
|
IN ULONG ByteCount
|
|
)
|
|
/*++
|
|
This routine reads the RTC registers for the Dallas 1501 CMOS/RTC chip.
|
|
|
|
Arguments:
|
|
|
|
SourceAddress : address in CMOS where data is to be read from
|
|
|
|
ReturnBuffer : address in system memory for return data
|
|
|
|
ByteCount : number of bytes to be read
|
|
|
|
Returns:
|
|
|
|
Number of bytes actually read.
|
|
|
|
--*/
|
|
{
|
|
ULONG offset;
|
|
ULONG bufOffset;
|
|
ULONG status; // register status
|
|
ULONG upperAddrBound;
|
|
|
|
upperAddrBound = SourceAddress + ByteCount;
|
|
|
|
//
|
|
// NOTE: The spinlock is needed even in the UP case, because
|
|
// the resource is also used in an interrupt handler (profiler).
|
|
// If we own the spinlock in this routine, and we service
|
|
// the profiler interrupt (which will wait for the spinlock forever),
|
|
// then we have a hosed system.
|
|
//
|
|
|
|
HalpAcquireCmosSpinLock();
|
|
|
|
//
|
|
// NOTE: The recommended procedure for reading the Dallas 1501 RTC is to stop
|
|
// external register updates while reading. Internally, updates in the RTC
|
|
// continue as normal. This procedure prevents reading the registers while
|
|
// they are in transition
|
|
//
|
|
|
|
//
|
|
// Clear the TE bit of register B to stop external updates
|
|
//
|
|
WRITE_PORT_UCHAR((PUCHAR)CmosStdAddrPort, CMOS_RAM_DAL1501_REGISTER_B);
|
|
status = READ_PORT_UCHAR((PUCHAR)CmosStdDataPort);
|
|
status &= ~CMOS_RAM_DAL1501_REGISTER_B_TE_BIT;
|
|
WRITE_PORT_UCHAR((PUCHAR)CmosStdAddrPort, CMOS_RAM_DAL1501_REGISTER_B);
|
|
WRITE_PORT_UCHAR((PUCHAR)CmosStdDataPort, (UCHAR)status);
|
|
|
|
for (offset = SourceAddress, bufOffset = 0; offset < upperAddrBound; offset++, bufOffset++) {
|
|
|
|
WRITE_PORT_UCHAR((PUCHAR)CmosStdAddrPort, (UCHAR)offset);
|
|
|
|
ReturnBuffer[bufOffset] = READ_PORT_UCHAR((PUCHAR)CmosStdDataPort);
|
|
|
|
}
|
|
|
|
//
|
|
// Set the TE bit of register B to enable external updates
|
|
//
|
|
WRITE_PORT_UCHAR((PUCHAR)CmosStdAddrPort, CMOS_RAM_DAL1501_REGISTER_B);
|
|
status = READ_PORT_UCHAR((PUCHAR)CmosStdDataPort);
|
|
status |= CMOS_RAM_DAL1501_REGISTER_B_TE_BIT;
|
|
WRITE_PORT_UCHAR((PUCHAR)CmosStdAddrPort, CMOS_RAM_DAL1501_REGISTER_B);
|
|
WRITE_PORT_UCHAR((PUCHAR)CmosStdDataPort, (UCHAR)status);
|
|
|
|
HalpReleaseCmosSpinLock();
|
|
|
|
return bufOffset;
|
|
}
|
|
|
|
ULONG
|
|
HalpWriteRtcDal1501(
|
|
IN ULONG SourceAddress,
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IN PUCHAR ReturnBuffer,
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IN ULONG ByteCount
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)
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/*++
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This routine handles writes into the RTC region for the Dallas 1501 CMOS/RTC chip.
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Arguments:
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SourceAddress : address in CMOS where data is to be read from
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ReturnBuffer : address in system memory for return data
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ByteCount : number of bytes to be read
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Returns:
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Number of bytes actually read.
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--*/
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{
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ULONG offset;
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ULONG bufOffset;
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ULONG status; // register status
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ULONG upperAddrBound;
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upperAddrBound = SourceAddress + ByteCount;
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//
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// NOTE: The spinlock is needed even in the UP case, because
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// the resource is also used in an interrupt handler (profiler).
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// If we own the spinlock in this routine, and we service
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// the profiler interrupt (which will wait for the spinlock forever),
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// then we have a hosed system.
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//
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HalpAcquireCmosSpinLock();
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//
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// NOTE: The recommended procedure for writing the Dallas 1501 RTC is to stop
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// external register updates while writing. The modified register values
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// are transferred into the internal registers when the TE bit is set. Operation
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// then continues normally.
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//
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//
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// Clear the TE bit of register B to stop external updates
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//
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WRITE_PORT_UCHAR((PUCHAR)CmosStdAddrPort, CMOS_RAM_DAL1501_REGISTER_B);
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status = READ_PORT_UCHAR((PUCHAR)CmosStdDataPort);
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status &= ~CMOS_RAM_DAL1501_REGISTER_B_TE_BIT;
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WRITE_PORT_UCHAR((PUCHAR)CmosStdAddrPort, CMOS_RAM_DAL1501_REGISTER_B);
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WRITE_PORT_UCHAR((PUCHAR)CmosStdDataPort, (UCHAR)status);
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for (offset = SourceAddress, bufOffset = 0; offset < upperAddrBound; offset++, bufOffset++) {
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WRITE_PORT_UCHAR((PUCHAR)CmosStdAddrPort, (UCHAR)offset);
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WRITE_PORT_UCHAR((PUCHAR)CmosStdDataPort, (UCHAR)(ReturnBuffer[bufOffset]));
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}
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//
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// Set the TE bit of register B to enable external updates
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//
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WRITE_PORT_UCHAR((PUCHAR)CmosStdAddrPort, CMOS_RAM_DAL1501_REGISTER_B);
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status = READ_PORT_UCHAR((PUCHAR)CmosStdDataPort);
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status |= CMOS_RAM_DAL1501_REGISTER_B_TE_BIT;
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WRITE_PORT_UCHAR((PUCHAR)CmosStdAddrPort, CMOS_RAM_DAL1501_REGISTER_B);
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WRITE_PORT_UCHAR((PUCHAR)CmosStdDataPort, (UCHAR)status);
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HalpReleaseCmosSpinLock();
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return bufOffset;
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}
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ULONG
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HalpReadExtCmosDal1501(
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IN ULONG SourceAddress,
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IN PUCHAR ReturnBuffer,
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IN ULONG ByteCount
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)
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{
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ULONG offset;
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ULONG bufOffset;
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ULONG status; // register status
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ULONG upperAddrBound;
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upperAddrBound = SourceAddress + ByteCount;
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//
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// NOTE: The spinlock is needed even in the UP case, because
|
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// the resource is also used in an interrupt handler (profiler).
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|
// If we own the spinlock in this routine, and we service
|
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// the profiler interrupt (which will wait for the spinlock forever),
|
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// then we have a hosed system.
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//
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HalpAcquireCmosSpinLock();
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//
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// reading from Dallas 1501 SRAM is a 2 step process:
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// 1. First, we write the address to the RAM_ADDR_LSB register in the standard CMOS region.
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// 2. Then we read the data byte from the RAM_DATA register in the standard CMOS region.
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//
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for (offset = SourceAddress, bufOffset = 0; offset < upperAddrBound; offset++, bufOffset++) {
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//
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// specify the offset into SRAM
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//
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WRITE_PORT_UCHAR((PUCHAR)CmosStdAddrPort, CMOS_RAM_DAL1501_RAM_ADDR_LSB);
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WRITE_PORT_UCHAR((PUCHAR)CmosStdDataPort, (UCHAR)offset);
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//
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// read the data from SRAM[offset]
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//
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WRITE_PORT_UCHAR((PUCHAR)CmosStdAddrPort, CMOS_RAM_DAL1501_RAM_DATA);
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ReturnBuffer[bufOffset] = READ_PORT_UCHAR((PUCHAR)CmosStdDataPort);
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}
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HalpReleaseCmosSpinLock();
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return bufOffset;
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}
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ULONG
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HalpWriteExtCmosDal1501(
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IN ULONG SourceAddress,
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IN PUCHAR ReturnBuffer,
|
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IN ULONG ByteCount
|
|
)
|
|
{
|
|
ULONG offset;
|
|
ULONG bufOffset;
|
|
ULONG status; // register status
|
|
ULONG upperAddrBound;
|
|
|
|
upperAddrBound = SourceAddress + ByteCount;
|
|
|
|
//
|
|
// NOTE: The spinlock is needed even in the UP case, because
|
|
// the resource is also used in an interrupt handler (profiler).
|
|
// If we own the spinlock in this routine, and we service
|
|
// the profiler interrupt (which will wait for the spinlock forever),
|
|
// then we have a hosed system.
|
|
//
|
|
|
|
HalpAcquireCmosSpinLock();
|
|
|
|
//
|
|
// writing to Dallas 1501 SRAM is a 2 step process:
|
|
// 1. First, we write the address to the RAM_ADDR_LSB register in the standard CMOS region.
|
|
// 2. Then we write the data byte to the RAM_DATA register in the standard CMOS region.
|
|
//
|
|
for (offset = SourceAddress, bufOffset = 0; offset < upperAddrBound; offset++, bufOffset++) {
|
|
|
|
//
|
|
// specify the offset into SRAM
|
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//
|
|
WRITE_PORT_UCHAR((PUCHAR)CmosStdAddrPort, CMOS_RAM_DAL1501_RAM_ADDR_LSB);
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WRITE_PORT_UCHAR((PUCHAR)CmosStdDataPort, (UCHAR)offset);
|
|
|
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//
|
|
// specify the data to be written into SRAM[offset]
|
|
//
|
|
WRITE_PORT_UCHAR((PUCHAR)CmosStdAddrPort, CMOS_RAM_DAL1501_RAM_DATA);
|
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WRITE_PORT_UCHAR((PUCHAR)CmosStdDataPort, (UCHAR)(ReturnBuffer[bufOffset]));
|
|
|
|
}
|
|
|
|
HalpReleaseCmosSpinLock();
|
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|
|
return bufOffset;
|
|
}
|
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|
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#endif // ACPI_CMOS_ACTIVATE
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