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170 lines
3.7 KiB
170 lines
3.7 KiB
/*++
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Copyright (c) 1997 Microsoft Corporation
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Module Name:
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ixthrotl.c
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Abstract:
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This module implements the code for throttling the processors
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Author:
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Jake Oshins (jakeo) 17-July-1997
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Environment:
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Kernel mode only.
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Revision History:
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--*/
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#include "halp.h"
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#include "acpitabl.h"
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#include "xxacpi.h"
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#include "pci.h"
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VOID
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FASTCALL
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HalProcessorThrottle (
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IN UCHAR Throttle
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)
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/*++
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Routine Description:
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This function limits the speed of the processor.
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Arguments:
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(ecx) = Throttle setting
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Return Value:
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none
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--*/
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{
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PKPRCB PrcB;
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PHALPMPRCB HalPrcB;
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ULONG ThrottleSetting;
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ULONG Addr;
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ULONG Mask;
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ULONG i;
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ULONG PblkAddr;
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#if DBG
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// debug
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WRITE_PORT_UCHAR ((PUCHAR) 0x80, Throttle);
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#endif
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PrcB = KeGetPcr()->Prcb;
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HalPrcB = (PHALPMPRCB) PrcB->HalReserved;
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PblkAddr = HalPrcB->PBlk.Addr;
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ThrottleSetting = READ_PORT_ULONG ((PULONG) PblkAddr);
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if (Throttle == HalpThrottleScale) {
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//
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// If this is a piix4 and we're no longer going to
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// throttle, set the break events (a piix4 thing) to
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// get any interrupt to wake a C2 to C3 stopped
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// processor. (note that piix4 can only be set on a
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// UP system). Then clear the bit to allow C2 and C3
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// idle handlers to work again.
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//
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if (HalpPiix4 == 1) {
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HalSetBusDataByOffset (
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PCIConfiguration,
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HalpPiix4BusNumber,
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HalpPiix4SlotNumber,
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&HalpPiix4DevActB,
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0x58,
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sizeof (ULONG)
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);
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HalPrcB->PBlk.AddrAndFlags &= ~PIIX4_THROTTLE_FIX;
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}
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//
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// Throttling is off
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//
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ThrottleSetting &= ~PBLK_THT_EN;
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WRITE_PORT_ULONG ((PULONG) PblkAddr, ThrottleSetting);
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} else {
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//
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// Throttling is on.
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//
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if (HalpPiix4 == 1) {
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//
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// These piix4's have the thottle setting backwards, so
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// invert the value
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//
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Throttle = (UCHAR) HalpThrottleScale - Throttle;
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//
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// Piix4 will hang on a high throttle setting, so make
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// sure we don't do that
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//
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if (Throttle < 3) {
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Throttle = 3;
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}
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}
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//
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// Shift the throttle and build a mask to be in the proper location
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// for this platform
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//
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Throttle = Throttle << HalpFixedAcpiDescTable.duty_offset;
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Mask = (HalpThrottleScale - 1) << HalpFixedAcpiDescTable.duty_offset;
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//
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// Set the rate
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//
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ThrottleSetting &= ~Mask;
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ThrottleSetting |= Throttle | PBLK_THT_EN;
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WRITE_PORT_ULONG ((PULONG) PblkAddr, ThrottleSetting);
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//
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// If this is a piix4 we need to disable all the break events
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// (a piix4 thing) and then read the level2 processor stop
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// register to get it to start throttling. Oh yes, also set
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// the bit in the Paddr to stop doing C2 & C3 stops at the
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// same time.
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//
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if (HalpPiix4 == 1) {
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HalPrcB->PBlk.AddrAndFlags |= PIIX4_THROTTLE_FIX;
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i = HalpPiix4DevActB & ~0x23;
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HalSetBusDataByOffset (
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PCIConfiguration,
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HalpPiix4BusNumber,
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HalpPiix4SlotNumber,
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&i,
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0x58,
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sizeof(ULONG)
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);
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READ_PORT_UCHAR ((PUCHAR) PblkAddr + P_LVL2);
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}
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}
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}
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