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1406 lines
41 KiB
1406 lines
41 KiB
/*++
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Copyright (c) 1989 Microsoft Corporation
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Module Name:
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i64pcibus.c
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Abstract:
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Get/Set bus data routines for the PCI bus
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Author:
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Ken Reneris (kenr) 14-June-1994
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Chris Hyser ([email protected]) 1-Feb-98
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Environment:
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Kernel mode
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Revision History:
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--*/
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#include "halp.h"
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#include "pci.h"
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#include "pcip.h"
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#include "i64fw.h"
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//
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// Prototypes
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//
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ULONG
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HalpGetPCIData(
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PCI_SLOT_NUMBER SlotNumber,
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IN PVOID Buffer,
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IN ULONG Offset,
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IN ULONG Length
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);
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ULONG
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HalpSetPCIData(
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PCI_SLOT_NUMBER SlotNumber,
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IN PVOID Buffer,
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IN ULONG Offset,
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IN ULONG Length
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);
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NTSTATUS
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HalpAssignPCISlotResources(
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PUNICODE_STRING RegistryPath,
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IN PUNICODE_STRING DriverClassName OPTIONAL,
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IN PDRIVER_OBJECT DriverObject,
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IN PDEVICE_OBJECT DeviceObject OPTIONAL,
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IN ULONG SlotNumber,
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IN OUT PCM_RESOURCE_LIST *AllocatedResources
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);
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VOID
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HalpInitializePciBus(
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VOID
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);
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BOOLEAN
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HalpIsValidPCIDevice(
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IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot
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);
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BOOLEAN
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HalpValidPCISlot(
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IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot
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);
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//
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// PCI Configuration Space Accessor types
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//
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typedef enum {
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PCI_READ,
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PCI_WRITE
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} PCI_ACCESS_TYPE;
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VOID
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HalpPCIConfig(
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IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PUCHAR Buffer,
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IN ULONG Offset,
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IN ULONG Length,
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IN PCI_ACCESS_TYPE Acctype
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);
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#if DBG
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#if !defined(NO_LEGACY_DRIVERS)
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VOID
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HalpTestPci(
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ULONG
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);
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#endif
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#endif
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#ifdef ALLOC_PRAGMA
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#pragma alloc_text(INIT,HalpInitializePciBus)
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#pragma alloc_text(INIT,HalpAllocateAndInitPciBusHandler)
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#pragma alloc_text(INIT,HalpIsValidPCIDevice)
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#pragma alloc_text(PAGE,HalpAssignPCISlotResources)
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#endif
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ULONG
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HalpGetPCIData(
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PUCHAR Buffer,
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IN ULONG Offset,
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IN ULONG Length
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)
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/*++
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Routine Description:
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The function returns the PCI bus data for a specified PCI "slot". This
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function is called on behalf of
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Arguments:
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BusHandler - An encapsulation of data and manipulation functions specific to
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this bus.
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RootHandler - ???
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Slot - A PCI "slot" description (ie bus number, device number and function
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number.)
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Buffer - A pointer to the space to store the data.
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Offset - The byte offset into the configuration space for this PCI "slot".
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Length - Supplies a count in bytes of the maximum amount to return. (ie
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equal or less than the size of the Buffer.)
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Return Value:
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Returns the amount of data stored into the buffer.
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If this PCI slot has never been set, then the configuration information
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returned is zeroed.
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--*/
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{
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PPCI_COMMON_CONFIG PciData;
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UCHAR iBuffer[PCI_COMMON_HDR_LENGTH];
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PPCIPBUSDATA BusData;
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ULONG Len;
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ULONG i, bit;
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if (Length > sizeof(PCI_COMMON_CONFIG))
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Length = sizeof(PCI_COMMON_CONFIG);
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Len = 0;
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PciData = (PPCI_COMMON_CONFIG)iBuffer;
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//
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// If the requested offset does not lie in the PCI onfiguration space common
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// header, we will read the vendor ID from the common header to ensure this
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// is a valid device. Note: The common header is from 0 to
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// PCI_COMMON_HEADER_LENGTH inclusive. We know Offset is > 0 because it is
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// unsigned.
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//
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if (Offset >= PCI_COMMON_HDR_LENGTH) {
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//
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// No data was requested from the common header. Verify the PCI device
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// exists, then continue in the device specific area.
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//
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HalpReadPCIConfig(BusHandler, Slot, PciData, 0, sizeof(ULONG));
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if (PciData->VendorID == PCI_INVALID_VENDORID)
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return(0);
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} else {
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//
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// Caller requested at least some data within the common header. Read
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// the whole header, effect the fields we need to and then copy the
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// user's requested bytes from the header
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//
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BusData = (PPCIPBUSDATA)BusHandler->BusData;
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//
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// Read this PCI devices slot data
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//
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Len = PCI_COMMON_HDR_LENGTH;
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HalpReadPCIConfig(BusHandler, Slot, PciData, 0, Len);
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if (PciData->VendorID == PCI_INVALID_VENDORID) {
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PciData->VendorID = PCI_INVALID_VENDORID;
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Len = 2; // only return invalid id
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} else {
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BusData->CommonData.Pin2Line(BusHandler, RootHandler, Slot, PciData);
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}
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//
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// Copy whatever data overlaps into the callers buffer
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//
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if (Len < Offset)
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return(0);
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Len -= Offset;
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if (Len > Length)
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Len = Length;
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RtlMoveMemory(Buffer, iBuffer + Offset, Len);
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Offset += Len;
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Buffer += Len;
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Length -= Len;
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}
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if (Length) {
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if (Offset >= PCI_COMMON_HDR_LENGTH) {
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//
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// The remaining Buffer comes from the Device Specific
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// area - put on the kitten gloves and read from it.
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//
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// Specific read/writes to the PCI device specific area
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// are guarenteed:
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//
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// Not to read/write any byte outside the area specified
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// by the caller. (this may cause WORD or BYTE references
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// to the area in order to read the non-dword aligned
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// ends of the request)
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//
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// To use a WORD access if the requested length is exactly
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// a WORD long.
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//
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// To use a BYTE access if the requested length is exactly
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// a BYTE long.
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//
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HalpReadPCIConfig(BusHandler, Slot, Buffer, Offset, Length);
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Len += Length;
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}
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}
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return(Len);
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}
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ULONG
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HalpSetPCIData(
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PUCHAR Buffer,
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IN ULONG Offset,
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IN ULONG Length
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)
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/*++
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Routine Description:
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The function sets the PCI bus data for a specified PCI "slot".
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Arguments:
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BusHandler - An encapsulation of data and manipulation functions specific to
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this bus.
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RootHandler - ???
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Slot - A PCI "slot" description (ie bus number, device number and function
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number.)
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Buffer - Supplies the space to store the data.
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Length - Supplies a count in bytes of the maximum amount to return.
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Return Value:
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Returns the amount of data stored into the buffer. ???
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--*/
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{
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PPCI_COMMON_CONFIG PciData, PciData2;
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UCHAR iBuffer[PCI_COMMON_HDR_LENGTH];
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UCHAR iBuffer2[PCI_COMMON_HDR_LENGTH];
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PPCIPBUSDATA BusData;
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ULONG Len, cnt;
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if (Length > sizeof(PCI_COMMON_CONFIG))
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Length = sizeof(PCI_COMMON_CONFIG);
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Len = 0;
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PciData = (PPCI_COMMON_CONFIG)iBuffer;
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PciData2 = (PPCI_COMMON_CONFIG)iBuffer2;
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if (Offset >= PCI_COMMON_HDR_LENGTH) {
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//
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// The user did not request any data from the common
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// header. Verify the PCI device exists, then continue in
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// the device specific area.
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//
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HalpReadPCIConfig(BusHandler, Slot, PciData, 0, sizeof(ULONG));
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if (PciData->VendorID == PCI_INVALID_VENDORID)
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return(0);
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} else {
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//
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// Caller requested to set at least some data within the
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// common header.
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//
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Len = PCI_COMMON_HDR_LENGTH;
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HalpReadPCIConfig(BusHandler, Slot, PciData, 0, Len);
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//
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// return error if no device or header type unknown
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//
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if (PciData->VendorID == PCI_INVALID_VENDORID ||
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PCI_CONFIG_TYPE(PciData) != PCI_DEVICE_TYPE)
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return(0);
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//
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// Set this device as configured
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//
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BusData = (PPCIPBUSDATA)BusHandler->BusData;
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#if DBG1
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cnt = PciBitIndex(Slot.u.bits.DeviceNumber, Slot.u.bits.FunctionNumber);
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RtlSetBits(&BusData->DeviceConfigured, cnt, 1);
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#endif
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//
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// Copy COMMON_HDR values to buffer2, then overlay callers changes.
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//
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RtlMoveMemory(iBuffer2, iBuffer, Len);
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BusData->CommonData.Pin2Line(BusHandler, RootHandler, Slot, PciData2);
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Len -= Offset;
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if (Len > Length)
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Len = Length;
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RtlMoveMemory(iBuffer2+Offset, Buffer, Len);
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//
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// in case interrupt line or pin was edited
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//
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BusData->CommonData.Line2Pin(BusHandler, RootHandler, Slot, PciData2, PciData);
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#if DBG1
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//
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// Verify R/O fields haven't changed
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//
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if (PciData2->VendorID != PciData->VendorID ||
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PciData2->DeviceID != PciData->DeviceID ||
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PciData2->RevisionID != PciData->RevisionID ||
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PciData2->ProgIf != PciData->ProgIf ||
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PciData2->SubClass != PciData->SubClass ||
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PciData2->BaseClass != PciData->BaseClass ||
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PciData2->HeaderType != PciData->HeaderType ||
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PciData2->BaseClass != PciData->BaseClass ||
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PciData2->u.type0.MinimumGrant != PciData->u.type0.MinimumGrant ||
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PciData2->u.type0.MaximumLatency != PciData->u.type0.MaximumLatency) {
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HalDebugPrint(( HAL_INFO, "HAL: PCI SetBusData - Read-Only configuration value changed\n" ));
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}
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#endif
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//
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// Set new PCI configuration
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//
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HalpWritePCIConfig(BusHandler, Slot, iBuffer2+Offset, Offset, Len);
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Offset += Len;
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Buffer += Len;
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Length -= Len;
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}
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if (Length) {
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if (Offset >= PCI_COMMON_HDR_LENGTH) {
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//
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// The remaining Buffer comes from the Device Specific
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// area - put on the kitten gloves and write it
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//
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// Specific read/writes to the PCI device specific area
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// are guarenteed:
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//
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// Not to read/write any byte outside the area specified
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// by the caller. (this may cause WORD or BYTE references
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// to the area in order to read the non-dword aligned
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// ends of the request)
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//
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// To use a WORD access if the requested length is exactly
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// a WORD long.
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//
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// To use a BYTE access if the requested length is exactly
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// a BYTE long.
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//
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HalpWritePCIConfig(BusHandler, Slot, Buffer, Offset, Length);
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Len += Length;
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}
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}
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return(Len);
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}
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NTSTATUS
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HalpAssignPCISlotResources(
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PUNICODE_STRING RegistryPath,
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IN PUNICODE_STRING DriverClassName OPTIONAL,
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IN PDRIVER_OBJECT DriverObject,
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IN PDEVICE_OBJECT DeviceObject OPTIONAL,
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IN ULONG Slot,
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IN OUT PCM_RESOURCE_LIST *pAllocatedResources
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)
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/*++
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Routine Description:
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Reads the targeted device to determine it's required resources.
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Calls IoAssignResources to allocate them.
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Sets the targeted device with it's assigned resoruces
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and returns the assignments to the caller.
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Note: This function assumes all of a PCI "slots" resources as indicated by
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it's configuration space are REQUIRED.
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Arguments:
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Return Value:
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STATUS_SUCCESS or error
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--*/
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{
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NTSTATUS status;
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PUCHAR WorkingPool;
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PPCI_COMMON_CONFIG PciData, PciOrigData, PciData2;
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PCI_SLOT_NUMBER PciSlot;
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PPCIPBUSDATA BusData;
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PIO_RESOURCE_REQUIREMENTS_LIST CompleteList;
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PIO_RESOURCE_DESCRIPTOR Descriptor;
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PCM_PARTIAL_RESOURCE_DESCRIPTOR CmDescriptor;
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ULONG BusNumber;
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ULONG i, j, m, length, memtype;
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ULONG NoBaseAddress, RomIndex, Option;
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PULONG BaseAddress[PCI_TYPE0_ADDRESSES + 1];
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PULONG OrigAddress[PCI_TYPE0_ADDRESSES + 1];
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BOOLEAN Match, EnableRomBase, RequestedInterrupt;
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*pAllocatedResources = NULL;
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PciSlot = *((PPCI_SLOT_NUMBER) &Slot);
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BusNumber = BusHandler->BusNumber;
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BusData = (PPCIPBUSDATA) BusHandler->BusData;
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//
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// Allocate some pool for working space
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//
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i = sizeof(IO_RESOURCE_REQUIREMENTS_LIST) +
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sizeof(IO_RESOURCE_DESCRIPTOR) * (PCI_TYPE0_ADDRESSES + 2) * 2 +
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PCI_COMMON_HDR_LENGTH * 3;
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WorkingPool = (PUCHAR)ExAllocatePool(PagedPool, i);
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if (!WorkingPool)
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return(STATUS_INSUFFICIENT_RESOURCES);
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|
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//
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// Zero initialize pool, and get pointers into memory
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//
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RtlZeroMemory(WorkingPool, i);
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CompleteList = (PIO_RESOURCE_REQUIREMENTS_LIST)WorkingPool;
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PciData = (PPCI_COMMON_CONFIG) (WorkingPool + i - PCI_COMMON_HDR_LENGTH * 3);
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PciData2 = (PPCI_COMMON_CONFIG) (WorkingPool + i - PCI_COMMON_HDR_LENGTH * 2);
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PciOrigData = (PPCI_COMMON_CONFIG) (WorkingPool + i - PCI_COMMON_HDR_LENGTH * 1);
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|
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//
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// Read the PCI device's configuration
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//
|
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HalpReadPCIConfig(BusHandler, PciSlot, PciData, 0, PCI_COMMON_HDR_LENGTH);
|
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if (PciData->VendorID == PCI_INVALID_VENDORID) {
|
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ExFreePool(WorkingPool);
|
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return(STATUS_NO_SUCH_DEVICE);
|
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}
|
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|
|
//
|
|
// For now since there's not PnP support in the OS, if the BIOS hasn't
|
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// enable a VGA device don't allow it to get enabled via this interface.
|
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//
|
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if ((PciData->BaseClass == 0 && PciData->SubClass == 1) ||
|
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(PciData->BaseClass == 3 && PciData->SubClass == 0)) {
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|
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if ((PciData->Command & (PCI_ENABLE_IO_SPACE | PCI_ENABLE_MEMORY_SPACE)) == 0) {
|
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ExFreePool (WorkingPool);
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return(STATUS_DEVICE_NOT_CONNECTED);
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}
|
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}
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|
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//
|
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// Make a copy of the device's current settings
|
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//
|
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RtlMoveMemory(PciOrigData, PciData, PCI_COMMON_HDR_LENGTH);
|
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|
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//
|
|
// Initialize base addresses base on configuration data type
|
|
//
|
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switch (PCI_CONFIG_TYPE(PciData)) {
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case 0 :
|
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NoBaseAddress = PCI_TYPE0_ADDRESSES+1;
|
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for (j=0; j < PCI_TYPE0_ADDRESSES; j++) {
|
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BaseAddress[j] = &PciData->u.type0.BaseAddresses[j];
|
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OrigAddress[j] = &PciOrigData->u.type0.BaseAddresses[j];
|
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}
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BaseAddress[j] = &PciData->u.type0.ROMBaseAddress;
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OrigAddress[j] = &PciOrigData->u.type0.ROMBaseAddress;
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RomIndex = j;
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break;
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case 1:
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NoBaseAddress = PCI_TYPE1_ADDRESSES+1;
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for (j=0; j < PCI_TYPE1_ADDRESSES; j++) {
|
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BaseAddress[j] = &PciData->u.type1.BaseAddresses[j];
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OrigAddress[j] = &PciOrigData->u.type1.BaseAddresses[j];
|
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}
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BaseAddress[j] = &PciData->u.type1.ROMBaseAddress;
|
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OrigAddress[j] = &PciOrigData->u.type1.ROMBaseAddress;
|
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RomIndex = j;
|
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break;
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|
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default:
|
|
ExFreePool (WorkingPool);
|
|
return(STATUS_NO_SUCH_DEVICE);
|
|
}
|
|
|
|
//
|
|
// If the BIOS doesn't have the device's ROM enabled, then we won't enable
|
|
// it either. Remove it from the list.
|
|
//
|
|
EnableRomBase = TRUE;
|
|
if (!(*BaseAddress[RomIndex] & PCI_ROMADDRESS_ENABLED)) {
|
|
ASSERT (RomIndex+1 == NoBaseAddress);
|
|
EnableRomBase = FALSE;
|
|
NoBaseAddress -= 1;
|
|
}
|
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|
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//
|
|
// Set resources to all bits on to see what type of resources are required.
|
|
//
|
|
for (j=0; j < NoBaseAddress; j++)
|
|
*BaseAddress[j] = 0xFFFFFFFF;
|
|
|
|
PciData->Command &= ~(PCI_ENABLE_IO_SPACE | PCI_ENABLE_MEMORY_SPACE);
|
|
*BaseAddress[RomIndex] &= ~PCI_ROMADDRESS_ENABLED;
|
|
HalpWritePCIConfig (BusHandler, PciSlot, PciData, 0, PCI_COMMON_HDR_LENGTH);
|
|
HalpReadPCIConfig (BusHandler, PciSlot, PciData, 0, PCI_COMMON_HDR_LENGTH);
|
|
|
|
//
|
|
// note type0 & type1 overlay ROMBaseAddress, InterruptPin, and InterruptLine
|
|
//
|
|
BusData->CommonData.Pin2Line (BusHandler, RootHandler, PciSlot, PciData);
|
|
|
|
//
|
|
// Build an IO_RESOURCE_REQUIREMENTS_LIST for the PCI device
|
|
//
|
|
CompleteList->InterfaceType = PCIBus;
|
|
CompleteList->BusNumber = BusNumber;
|
|
CompleteList->SlotNumber = Slot;
|
|
CompleteList->AlternativeLists = 1;
|
|
|
|
CompleteList->List[0].Version = 1;
|
|
CompleteList->List[0].Revision = 1;
|
|
|
|
Descriptor = CompleteList->List[0].Descriptors;
|
|
|
|
//
|
|
// If PCI device has an interrupt resource, add it
|
|
//
|
|
RequestedInterrupt = FALSE;
|
|
if (PciData->u.type0.InterruptPin &&
|
|
PciData->u.type0.InterruptLine != (0 ^ IRQXOR) &&
|
|
PciData->u.type0.InterruptLine != (0xFF ^ IRQXOR)) {
|
|
|
|
RequestedInterrupt = TRUE;
|
|
CompleteList->List[0].Count++;
|
|
|
|
Descriptor->Option = 0;
|
|
Descriptor->Type = CmResourceTypeInterrupt;
|
|
Descriptor->ShareDisposition = CmResourceShareShared;
|
|
Descriptor->Flags = CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE;
|
|
|
|
// Fill in any vector here - we'll pick it back up in
|
|
// HalAdjustResourceList and adjust it to it's allowed settings
|
|
Descriptor->u.Interrupt.MinimumVector = 0;
|
|
Descriptor->u.Interrupt.MaximumVector = 0xff;
|
|
Descriptor++;
|
|
}
|
|
|
|
//
|
|
// Add a memory/port resoruce for each PCI resource
|
|
//
|
|
|
|
// Clear ROM reserved bits
|
|
|
|
*BaseAddress[RomIndex] &= ~0x7FF;
|
|
|
|
for (j=0; j < NoBaseAddress; j++) {
|
|
if (*BaseAddress[j]) {
|
|
i = *BaseAddress[j];
|
|
|
|
//
|
|
// scan for first set bit, that's the length & alignment
|
|
//
|
|
length = 1 << (i & PCI_ADDRESS_IO_SPACE ? 2 : 4);
|
|
while (!(i & length) && length)
|
|
length <<= 1;
|
|
|
|
//
|
|
// scan for last set bit, that's the maxaddress + 1
|
|
//
|
|
for (m = length; i & m; m <<= 1) ;
|
|
m--;
|
|
|
|
//
|
|
// check for hosed PCI configuration requirements
|
|
//
|
|
if (length & ~m) {
|
|
#if DBG
|
|
HalDebugPrint(( HAL_INFO, "HAL: PCI - defective device! Bus %d, Slot %d, Function %d\n",
|
|
BusNumber,
|
|
PciSlot.u.bits.DeviceNumber,
|
|
PciSlot.u.bits.FunctionNumber
|
|
));
|
|
|
|
HalDebugPrint(( HAL_INFO, "HAL: PCI - BaseAddress[%d] = %08lx\n", j, i ));
|
|
#endif
|
|
//
|
|
// The device is in error - punt. don't allow this
|
|
// resource any option - it either gets set to whatever
|
|
// bits it was able to return, or it doesn't get set.
|
|
//
|
|
|
|
if (i & PCI_ADDRESS_IO_SPACE) {
|
|
m = i & ~0x3;
|
|
Descriptor->u.Port.MinimumAddress.LowPart = m;
|
|
} else {
|
|
m = i & ~0xf;
|
|
Descriptor->u.Memory.MinimumAddress.LowPart = m;
|
|
}
|
|
|
|
m += length; // max address is min address + length
|
|
}
|
|
|
|
//
|
|
// Add requested resource
|
|
//
|
|
Descriptor->Option = 0;
|
|
if (i & PCI_ADDRESS_IO_SPACE) {
|
|
memtype = 0;
|
|
|
|
if (!Is64BitBaseAddress(i) &&
|
|
PciOrigData->Command & PCI_ENABLE_IO_SPACE) {
|
|
|
|
//
|
|
// The IO range is/was already enabled at some location, add that
|
|
// as it's preferred setting.
|
|
//
|
|
Descriptor->Type = CmResourceTypePort;
|
|
Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
|
|
Descriptor->Flags = CM_RESOURCE_PORT_IO;
|
|
Descriptor->Option = IO_RESOURCE_PREFERRED;
|
|
|
|
Descriptor->u.Port.Length = length;
|
|
Descriptor->u.Port.Alignment = length;
|
|
Descriptor->u.Port.MinimumAddress.LowPart = *OrigAddress[j] & ~0x3;
|
|
Descriptor->u.Port.MaximumAddress.LowPart =
|
|
Descriptor->u.Port.MinimumAddress.LowPart + length - 1;
|
|
|
|
CompleteList->List[0].Count++;
|
|
Descriptor++;
|
|
|
|
Descriptor->Option = IO_RESOURCE_ALTERNATIVE;
|
|
}
|
|
|
|
//
|
|
// Add this IO range
|
|
//
|
|
Descriptor->Type = CmResourceTypePort;
|
|
Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
|
|
Descriptor->Flags = CM_RESOURCE_PORT_IO;
|
|
|
|
Descriptor->u.Port.Length = length;
|
|
Descriptor->u.Port.Alignment = length;
|
|
Descriptor->u.Port.MaximumAddress.LowPart = m;
|
|
|
|
} else {
|
|
|
|
memtype = i & PCI_ADDRESS_MEMORY_TYPE_MASK;
|
|
|
|
Descriptor->Flags = CM_RESOURCE_MEMORY_READ_WRITE;
|
|
if (j == RomIndex) {
|
|
// this is a ROM address
|
|
Descriptor->Flags = CM_RESOURCE_MEMORY_READ_ONLY;
|
|
}
|
|
|
|
if (i & PCI_ADDRESS_MEMORY_PREFETCHABLE) {
|
|
Descriptor->Flags |= CM_RESOURCE_MEMORY_PREFETCHABLE;
|
|
}
|
|
|
|
if (!Is64BitBaseAddress(i) &&
|
|
(j == RomIndex ||
|
|
PciOrigData->Command & PCI_ENABLE_MEMORY_SPACE)) {
|
|
|
|
//
|
|
// The memory range is/was already enabled at some location, add that
|
|
// as it's preferred setting.
|
|
//
|
|
Descriptor->Type = CmResourceTypeMemory;
|
|
Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
|
|
Descriptor->Option = IO_RESOURCE_PREFERRED;
|
|
|
|
Descriptor->u.Port.Length = length;
|
|
Descriptor->u.Port.Alignment = length;
|
|
Descriptor->u.Port.MinimumAddress.LowPart = *OrigAddress[j] & ~0xF;
|
|
Descriptor->u.Port.MaximumAddress.LowPart =
|
|
Descriptor->u.Port.MinimumAddress.LowPart + length - 1;
|
|
|
|
CompleteList->List[0].Count++;
|
|
Descriptor++;
|
|
|
|
Descriptor->Flags = Descriptor[-1].Flags;
|
|
Descriptor->Option = IO_RESOURCE_ALTERNATIVE;
|
|
}
|
|
|
|
//
|
|
// Add this memory range
|
|
//
|
|
Descriptor->Type = CmResourceTypeMemory;
|
|
Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
|
|
|
|
Descriptor->u.Memory.Length = length;
|
|
Descriptor->u.Memory.Alignment = length;
|
|
Descriptor->u.Memory.MaximumAddress.LowPart = m;
|
|
|
|
if (memtype == PCI_TYPE_20BIT && m > 0xFFFFF) {
|
|
// limit to 20 bit address
|
|
Descriptor->u.Memory.MaximumAddress.LowPart = 0xFFFFF;
|
|
}
|
|
}
|
|
|
|
CompleteList->List[0].Count++;
|
|
Descriptor++;
|
|
|
|
|
|
if (Is64BitBaseAddress(i)) {
|
|
//
|
|
// Eventually we may want to do some work here for 64-bit
|
|
// configs...
|
|
//
|
|
// skip upper half of 64 bit address since this processor
|
|
// only supports 32 bits of address space
|
|
//
|
|
j++;
|
|
}
|
|
}
|
|
}
|
|
|
|
CompleteList->ListSize = (ULONG)
|
|
((PUCHAR) Descriptor - (PUCHAR) CompleteList);
|
|
|
|
//
|
|
// Restore the device settings as we found them, enable memory
|
|
// and io decode after setting base addresses. This is done in
|
|
// case HalAdjustResourceList wants to read the current settings
|
|
// in the device.
|
|
//
|
|
HalpWritePCIConfig (
|
|
BusHandler,
|
|
PciSlot,
|
|
&PciOrigData->Status,
|
|
FIELD_OFFSET (PCI_COMMON_CONFIG, Status),
|
|
PCI_COMMON_HDR_LENGTH - FIELD_OFFSET (PCI_COMMON_CONFIG, Status)
|
|
);
|
|
|
|
HalpWritePCIConfig (
|
|
BusHandler,
|
|
PciSlot,
|
|
PciOrigData,
|
|
0,
|
|
FIELD_OFFSET (PCI_COMMON_CONFIG, Status)
|
|
);
|
|
|
|
//
|
|
// Have the IO system allocate resource assignments
|
|
//
|
|
status = IoAssignResources (
|
|
RegistryPath,
|
|
DriverClassName,
|
|
DriverObject,
|
|
DeviceObject,
|
|
CompleteList,
|
|
pAllocatedResources
|
|
);
|
|
|
|
if (!NT_SUCCESS(status)) {
|
|
goto CleanUp;
|
|
}
|
|
|
|
//
|
|
// Slurp the assigments back into the PciData structure and perform them
|
|
//
|
|
CmDescriptor = (*pAllocatedResources)->List[0].PartialResourceList.PartialDescriptors;
|
|
|
|
//
|
|
// If PCI device has an interrupt resource then that was passed in as the
|
|
// first requested resource
|
|
//
|
|
if (RequestedInterrupt) {
|
|
PciData->u.type0.InterruptLine = (UCHAR) CmDescriptor->u.Interrupt.Vector;
|
|
BusData->CommonData.Line2Pin (BusHandler, RootHandler, PciSlot, PciData, PciOrigData);
|
|
CmDescriptor++;
|
|
}
|
|
|
|
//
|
|
// Pull out resources in the order they were passed to IoAssignResources
|
|
//
|
|
for (j=0; j < NoBaseAddress; j++) {
|
|
i = *BaseAddress[j];
|
|
if (i) {
|
|
if (i & PCI_ADDRESS_IO_SPACE) {
|
|
*BaseAddress[j] = CmDescriptor->u.Port.Start.LowPart;
|
|
} else {
|
|
*BaseAddress[j] = CmDescriptor->u.Memory.Start.LowPart;
|
|
}
|
|
CmDescriptor++;
|
|
}
|
|
|
|
if (Is64BitBaseAddress(i)) {
|
|
// skip upper 32 bits
|
|
j++;
|
|
}
|
|
}
|
|
|
|
//
|
|
// Turn off decodes, then set new addresses
|
|
//
|
|
HalpWritePCIConfig (BusHandler, PciSlot, PciData, 0, PCI_COMMON_HDR_LENGTH);
|
|
|
|
//
|
|
// Read configuration back and verify address settings took
|
|
//
|
|
HalpReadPCIConfig(BusHandler, PciSlot, PciData2, 0, PCI_COMMON_HDR_LENGTH);
|
|
|
|
Match = TRUE;
|
|
if (PciData->u.type0.InterruptLine != PciData2->u.type0.InterruptLine ||
|
|
PciData->u.type0.InterruptPin != PciData2->u.type0.InterruptPin ||
|
|
PciData->u.type0.ROMBaseAddress != PciData2->u.type0.ROMBaseAddress) {
|
|
Match = FALSE;
|
|
}
|
|
|
|
for (j=0; j < NoBaseAddress; j++) {
|
|
if (*BaseAddress[j]) {
|
|
if (*BaseAddress[j] & PCI_ADDRESS_IO_SPACE) {
|
|
i = (ULONG) ~0x3;
|
|
} else {
|
|
i = (ULONG) ~0xF;
|
|
}
|
|
|
|
if (( (*BaseAddress[j]) & i) !=
|
|
(*((PULONG) ((PUCHAR) BaseAddress[j] -
|
|
(PUCHAR) PciData +
|
|
(PUCHAR) PciData2)) & i)) {
|
|
|
|
Match = FALSE;
|
|
}
|
|
|
|
if (Is64BitBaseAddress(*BaseAddress[j])) {
|
|
//
|
|
// Eventually we may want to do something with the upper
|
|
// 32 bits
|
|
//
|
|
j++;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (!Match) {
|
|
HalDebugPrint(( HAL_INFO, "HAL: PCI - defective device! Bus %d, Slot %d, Function %d\n",
|
|
BusNumber,
|
|
PciSlot.u.bits.DeviceNumber,
|
|
PciSlot.u.bits.FunctionNumber
|
|
));
|
|
status = STATUS_DEVICE_PROTOCOL_ERROR;
|
|
goto CleanUp;
|
|
}
|
|
|
|
//
|
|
// Settings took - turn on the appropiate decodes
|
|
//
|
|
if (EnableRomBase && *BaseAddress[RomIndex]) {
|
|
|
|
//
|
|
// A rom address was allocated and should be enabled
|
|
//
|
|
*BaseAddress[RomIndex] |= PCI_ROMADDRESS_ENABLED;
|
|
HalpWritePCIConfig(
|
|
BusHandler,
|
|
PciSlot,
|
|
BaseAddress[RomIndex],
|
|
(ULONG) ((PUCHAR) BaseAddress[RomIndex] - (PUCHAR) PciData),
|
|
sizeof (ULONG)
|
|
);
|
|
}
|
|
|
|
//
|
|
// Enable IO, Memory, and BUS_MASTER decodes
|
|
// (use HalSetBusData since valid settings now set)
|
|
//
|
|
PciData->Command |= PCI_ENABLE_IO_SPACE |
|
|
PCI_ENABLE_MEMORY_SPACE |
|
|
PCI_ENABLE_BUS_MASTER;
|
|
|
|
HalSetBusDataByOffset(
|
|
PCIConfiguration,
|
|
BusHandler->BusNumber,
|
|
PciSlot.u.AsULONG,
|
|
&PciData->Command,
|
|
FIELD_OFFSET (PCI_COMMON_CONFIG, Command),
|
|
sizeof (PciData->Command)
|
|
);
|
|
|
|
CleanUp:
|
|
if (!NT_SUCCESS(status)) {
|
|
|
|
//
|
|
// Failure, if there are any allocated resources free them
|
|
//
|
|
if (*pAllocatedResources) {
|
|
IoAssignResources(
|
|
RegistryPath,
|
|
DriverClassName,
|
|
DriverObject,
|
|
DeviceObject,
|
|
NULL,
|
|
NULL
|
|
);
|
|
|
|
ExFreePool(*pAllocatedResources);
|
|
*pAllocatedResources = NULL;
|
|
}
|
|
|
|
//
|
|
// Restore the device settings as we found them, enable memory
|
|
// and io decode after setting base addresses
|
|
//
|
|
HalpWritePCIConfig(
|
|
BusHandler,
|
|
PciSlot,
|
|
&PciOrigData->Status,
|
|
FIELD_OFFSET(PCI_COMMON_CONFIG, Status),
|
|
PCI_COMMON_HDR_LENGTH - FIELD_OFFSET (PCI_COMMON_CONFIG, Status)
|
|
);
|
|
|
|
HalpWritePCIConfig(
|
|
BusHandler,
|
|
PciSlot,
|
|
PciOrigData,
|
|
0,
|
|
FIELD_OFFSET(PCI_COMMON_CONFIG, Status)
|
|
);
|
|
}
|
|
|
|
ExFreePool(WorkingPool);
|
|
return(status);
|
|
}
|
|
|
|
BOOLEAN
|
|
HalpValidPCISlot(
|
|
IN PBUS_HANDLER BusHandler,
|
|
IN PCI_SLOT_NUMBER Slot
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
The function validates the information specifying a PCI "slot".
|
|
|
|
Arguments:
|
|
|
|
BusHandler - An encapsulation of data and manipulation functions specific to
|
|
this bus.
|
|
|
|
Slot - A PCI "slot" description (ie bus number, device number and function
|
|
number.)
|
|
|
|
Return Value:
|
|
|
|
Returns TRUE if "slot" valid, otherwise FALSE.
|
|
|
|
--*/
|
|
|
|
{
|
|
PCI_SLOT_NUMBER Slot2;
|
|
PPCIPBUSDATA BusData;
|
|
UCHAR HeaderType;
|
|
ULONG i;
|
|
|
|
BusData = (PPCIPBUSDATA)BusHandler->BusData;
|
|
|
|
if (Slot.u.bits.Reserved != 0)
|
|
return(FALSE);
|
|
|
|
if (Slot.u.bits.DeviceNumber >= BusData->MaxDevice)
|
|
return(FALSE);
|
|
|
|
if (Slot.u.bits.FunctionNumber == 0)
|
|
return(TRUE);
|
|
|
|
//
|
|
// Read DeviceNumber, Function zero, to determine if the
|
|
// PCI supports multifunction devices
|
|
//
|
|
Slot.u.bits.FunctionNumber = 0;
|
|
|
|
HalpPCIConfig(
|
|
BusHandler,
|
|
Slot,
|
|
&HeaderType,
|
|
FIELD_OFFSET(PCI_COMMON_CONFIG, HeaderType),
|
|
sizeof(UCHAR),
|
|
PCI_READ
|
|
);
|
|
|
|
//
|
|
// FALSE if this device doesn't exist or doesn't support MULTIFUNCTION types
|
|
//
|
|
if (!(HeaderType & PCI_MULTIFUNCTION) || HeaderType == 0xFF)
|
|
return(FALSE);
|
|
|
|
return(TRUE);
|
|
}
|
|
|
|
//
|
|
// This table is used to determine correct access size to PCI configuration
|
|
// space given (offset % 4) and (length % 4).
|
|
//
|
|
// usage: PCIDeref[offset%4][length%4];
|
|
//
|
|
// Key:
|
|
// 4 - implies a ULONG access and is the number of bytes returned
|
|
// 1 - implies a UCHAR access and is the number of bytes returned
|
|
// 2 - implies a USHORT access and is the number of bytes returned
|
|
//
|
|
UCHAR PCIDeref[4][4] = {{4,1,2,2}, {1,1,1,1}, {2,1,2,2}, {1,1,1,1}};
|
|
#define SIZEOF_PARTIAL_INFO_HEADER FIELD_OFFSET(KEY_VALUE_PARTIAL_INFORMATION, Data)
|
|
|
|
VOID
|
|
HalpPCIConfig(
|
|
IN PBUS_HANDLER BusHandler,
|
|
IN PCI_SLOT_NUMBER Slot,
|
|
IN OUT PUCHAR Buffer,
|
|
IN ULONG Offset,
|
|
IN ULONG Length,
|
|
IN PCI_ACCESS_TYPE AccType
|
|
)
|
|
{
|
|
KIRQL Irql;
|
|
ULONG Size;
|
|
ULONG SALFunc;
|
|
ULONG CfgAddr;
|
|
ULONG WriteVal;
|
|
SAL_PAL_RETURN_VALUES RetVals;
|
|
SAL_STATUS Stat;
|
|
|
|
//
|
|
// Generate a PCI configuration address
|
|
//
|
|
CfgAddr = (BusHandler->BusNumber << 16) |
|
|
(Slot.u.bits.DeviceNumber << 11) |
|
|
(Slot.u.bits.FunctionNumber << 8);
|
|
|
|
//
|
|
// SAL or HalpSalCall will do whatever locking required.
|
|
//
|
|
|
|
while (Length) {
|
|
|
|
Size = PCIDeref[Offset % sizeof(ULONG)][Length % sizeof(ULONG)];
|
|
|
|
//
|
|
// Set up input parameters
|
|
//
|
|
if (AccType == PCI_READ) {
|
|
SALFunc = SAL_PCI_CONFIG_READ;
|
|
WriteVal = 0;
|
|
|
|
} else {
|
|
|
|
switch (Size) {
|
|
case 4: WriteVal = *((ULONG UNALIGNED *)Buffer); break;
|
|
case 2: WriteVal = *((USHORT UNALIGNED *)Buffer); break;
|
|
case 1: WriteVal = *Buffer; break;
|
|
}
|
|
|
|
SALFunc = SAL_PCI_CONFIG_WRITE;
|
|
}
|
|
|
|
//
|
|
// Make SAL call
|
|
//
|
|
Stat = HalpSalCall(SALFunc, CfgAddr | Offset, Size, WriteVal, 0, 0, 0, 0, &RetVals);
|
|
|
|
//
|
|
// Retrieve SAL return data
|
|
//
|
|
if (AccType == PCI_READ) {
|
|
switch (Size) {
|
|
case 4: *((ULONG UNALIGNED *)Buffer) = (ULONG)RetVals.ReturnValues[1]; break;
|
|
case 2: *((USHORT UNALIGNED *)Buffer) = (USHORT)RetVals.ReturnValues[1]; break;
|
|
case 1: *Buffer = (UCHAR)RetVals.ReturnValues[1]; break;
|
|
}
|
|
}
|
|
|
|
Offset += Size;
|
|
Buffer += Size;
|
|
Length -= Size;
|
|
}
|
|
}
|
|
|
|
|
|
VOID
|
|
HalpReadPCIConfig(
|
|
IN PBUS_HANDLER BusHandler,
|
|
IN PCI_SLOT_NUMBER Slot,
|
|
OUT PVOID Buffer,
|
|
IN ULONG Offset,
|
|
IN ULONG Length
|
|
)
|
|
{
|
|
//
|
|
// If request for an invalid slot, fill return buffer with -1
|
|
//
|
|
if (!HalpValidPCISlot(BusHandler, Slot)) {
|
|
RtlFillMemory(Buffer, Length, (UCHAR)-1);
|
|
return;
|
|
}
|
|
|
|
HalpPCIConfig(BusHandler, Slot, Buffer, Offset, Length, PCI_READ);
|
|
}
|
|
|
|
VOID
|
|
HalpWritePCIConfig(
|
|
IN PBUS_HANDLER BusHandler,
|
|
IN PCI_SLOT_NUMBER Slot,
|
|
IN PVOID Buffer,
|
|
IN ULONG Offset,
|
|
IN ULONG Length
|
|
)
|
|
{
|
|
//
|
|
// If request for an invalid slot, do nothing
|
|
//
|
|
if (!HalpValidPCISlot(BusHandler, Slot))
|
|
return;
|
|
|
|
HalpPCIConfig(BusHandler, Slot, Buffer, Offset, Length, PCI_WRITE);
|
|
}
|
|
|
|
|
|
BOOLEAN
|
|
HalpIsValidPCIDevice(
|
|
IN PBUS_HANDLER BusHandler,
|
|
IN PCI_SLOT_NUMBER Slot
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
Reads the device configuration data for the given slot and
|
|
returns TRUE if the configuration data appears to be valid for
|
|
a PCI device; otherwise returns FALSE.
|
|
|
|
Arguments:
|
|
|
|
BusHandler - Bus to check
|
|
Slot - Slot to check
|
|
|
|
--*/
|
|
|
|
{
|
|
PPCI_COMMON_CONFIG PciData;
|
|
UCHAR iBuffer[PCI_COMMON_HDR_LENGTH];
|
|
ULONG i, j;
|
|
|
|
PciData = (PPCI_COMMON_CONFIG)iBuffer;
|
|
|
|
//
|
|
// Read device common header.
|
|
//
|
|
HalpReadPCIConfig(BusHandler, Slot, PciData, 0, PCI_COMMON_HDR_LENGTH);
|
|
|
|
//
|
|
// Valid device header?
|
|
//
|
|
if (PciData->VendorID == PCI_INVALID_VENDORID ||
|
|
PCI_CONFIG_TYPE(PciData) != PCI_DEVICE_TYPE) {
|
|
return(FALSE);
|
|
}
|
|
|
|
//
|
|
// Check fields for reasonable values.
|
|
//
|
|
|
|
//
|
|
// Do these values make sense for IA64
|
|
//
|
|
if ((PciData->u.type0.InterruptPin && PciData->u.type0.InterruptPin > 4) ||
|
|
(PciData->u.type0.InterruptLine & 0x70)) {
|
|
return(FALSE);
|
|
}
|
|
|
|
for (i=0; i < PCI_TYPE0_ADDRESSES; i++) {
|
|
j = PciData->u.type0.BaseAddresses[i];
|
|
|
|
if (j & PCI_ADDRESS_IO_SPACE) {
|
|
if (j > 0xffff) {
|
|
// IO port > 64k?
|
|
return(FALSE);
|
|
}
|
|
} else {
|
|
if (j > 0xf && j < 0x80000) {
|
|
// Mem address < 0x8000h?
|
|
return(FALSE);
|
|
}
|
|
}
|
|
|
|
if (Is64BitBaseAddress(j))
|
|
i++;
|
|
}
|
|
|
|
//
|
|
// Guess it's a valid device..
|
|
//
|
|
return(TRUE);
|
|
}
|
|
|
|
#if !defined(NO_LEGACY_DRIVERS)
|
|
|
|
#if DBG
|
|
VOID
|
|
HalpTestPci (ULONG flag2)
|
|
{
|
|
PCI_SLOT_NUMBER SlotNumber;
|
|
PCI_COMMON_CONFIG PciData, OrigData;
|
|
ULONG i, f, j, k, bus;
|
|
BOOLEAN flag;
|
|
|
|
|
|
if (!flag2) {
|
|
return ;
|
|
}
|
|
|
|
DbgBreakPoint ();
|
|
SlotNumber.u.bits.Reserved = 0;
|
|
|
|
//
|
|
// Read every possible PCI Device/Function and display it's
|
|
// default info.
|
|
//
|
|
// (note this destories it's current settings)
|
|
//
|
|
|
|
flag = TRUE;
|
|
for (bus = 0; flag; bus++) {
|
|
|
|
for (i = 0; i < PCI_MAX_DEVICES; i++) {
|
|
SlotNumber.u.bits.DeviceNumber = i;
|
|
|
|
for (f = 0; f < PCI_MAX_FUNCTION; f++) {
|
|
SlotNumber.u.bits.FunctionNumber = f;
|
|
|
|
//
|
|
// Note: This is reading the DeviceSpecific area of
|
|
// the device's configuration - normally this should
|
|
// only be done on device for which the caller understands.
|
|
// I'm doing it here only for debugging.
|
|
//
|
|
|
|
j = HalGetBusData (
|
|
PCIConfiguration,
|
|
bus,
|
|
SlotNumber.u.AsULONG,
|
|
&PciData,
|
|
sizeof (PciData)
|
|
);
|
|
|
|
if (j == 0) {
|
|
// out of buses
|
|
flag = FALSE;
|
|
break;
|
|
}
|
|
|
|
if (j < PCI_COMMON_HDR_LENGTH) {
|
|
continue;
|
|
}
|
|
|
|
HalSetBusData (
|
|
PCIConfiguration,
|
|
bus,
|
|
SlotNumber.u.AsULONG,
|
|
&PciData,
|
|
1
|
|
);
|
|
|
|
HalGetBusData (
|
|
PCIConfiguration,
|
|
bus,
|
|
SlotNumber.u.AsULONG,
|
|
&PciData,
|
|
sizeof (PciData)
|
|
);
|
|
|
|
HalDebugPrint(( HAL_INFO, "HAL: PCI Bus %d Slot %2d %2d ID:%04lx-%04lx Rev:%04lx",
|
|
bus, i, f, PciData.VendorID, PciData.DeviceID,
|
|
PciData.RevisionID ));
|
|
|
|
|
|
if (PciData.u.type0.InterruptPin) {
|
|
HalDebugPrint(( HAL_INFO, " IntPin:%x", PciData.u.type0.InterruptPin ));
|
|
}
|
|
|
|
if (PciData.u.type0.InterruptLine) {
|
|
HalDebugPrint(( HAL_INFO, " IntLine:%x", PciData.u.type0.InterruptLine ));
|
|
}
|
|
|
|
if (PciData.u.type0.ROMBaseAddress) {
|
|
HalDebugPrint(( HAL_INFO, " ROM:%08lx", PciData.u.type0.ROMBaseAddress ));
|
|
}
|
|
|
|
HalDebugPrint(( HAL_INFO, "\nHAL: Cmd:%04x Status:%04x ProgIf:%04x SubClass:%04x BaseClass:%04lx\n",
|
|
PciData.Command, PciData.Status, PciData.ProgIf,
|
|
PciData.SubClass, PciData.BaseClass ));
|
|
|
|
k = 0;
|
|
for (j=0; j < PCI_TYPE0_ADDRESSES; j++) {
|
|
if (PciData.u.type0.BaseAddresses[j]) {
|
|
HalDebugPrint(( HAL_INFO, " Ad%d:%08lx", j, PciData.u.type0.BaseAddresses[j] ));
|
|
k = 1;
|
|
}
|
|
}
|
|
|
|
if (k) {
|
|
HalDebugPrint(( HAL_INFO, "\n" ));
|
|
}
|
|
|
|
if (PciData.VendorID == 0x8086) {
|
|
// dump complete buffer
|
|
HalDebugPrint(( HAL_INFO, "HAL: Command %x, Status %x, BIST %x\n",
|
|
PciData.Command, PciData.Status,
|
|
PciData.BIST
|
|
));
|
|
|
|
HalDebugPrint(( HAL_INFO, "HAL: CacheLineSz %x, LatencyTimer %x",
|
|
PciData.CacheLineSize, PciData.LatencyTimer
|
|
));
|
|
|
|
for (j=0; j < 192; j++) {
|
|
if ((j & 0xf) == 0) {
|
|
HalDebugPrint(( HAL_INFO, "\n%02x: ", j + 0x40 ));
|
|
}
|
|
HalDebugPrint(( HAL_INFO, "%02x ", PciData.DeviceSpecific[j] ));
|
|
}
|
|
HalDebugPrint(( HAL_INFO, "\n" ));
|
|
}
|
|
|
|
//
|
|
// Next
|
|
//
|
|
|
|
if (k) {
|
|
HalDebugPrint(( HAL_INFO, "\n\n" ));
|
|
}
|
|
}
|
|
}
|
|
}
|
|
DbgBreakPoint ();
|
|
}
|
|
|
|
#endif
|
|
|
|
#endif // NO_LEGACY_DRIVERS
|
|
|
|
//------------------------------------------------------------------------------
|
|
|