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1302 lines
36 KiB
1302 lines
36 KiB
/*++
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Copyright (c) 1989 Microsoft Corporation
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Module Name:
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mpsysbus.c
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Abstract:
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Author:
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Environment:
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Revision History:
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--*/
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#include "halp.h"
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#include "pci.h"
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#include "apic.inc"
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#include "pcmp_nt.inc"
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ULONG HalpDefaultInterruptAffinity = 0;
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#ifndef ACPI_HAL
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ULONG
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HalpGetEisaInterruptVector(
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN ULONG BusInterruptLevel,
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IN ULONG BusInterruptVector,
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OUT PKIRQL Irql,
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OUT PKAFFINITY Affinity
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);
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#else
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#undef HalpGetEisaInterruptVector
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#define HalpGetEisaInterruptVector HalpGetSystemInterruptVector
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extern BUS_HANDLER HalpFakePciBusHandler;
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#endif
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extern UCHAR HalpVectorToIRQL[];
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extern UCHAR HalpIRQLtoTPR[];
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extern USHORT HalpVectorToINTI[];
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extern KSPIN_LOCK HalpAccountingLock;
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extern struct HalpMpInfo HalpMpInfoTable;
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extern UCHAR HalpMaxProcsPerCluster;
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extern INTERRUPT_DEST HalpIntDestMap[];
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ULONG HalpINTItoVector[MAX_INTI];
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UCHAR HalpPICINTToVector[16];
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extern ULONG HalpMaxNode;
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extern KAFFINITY HalpNodeAffinity[MAX_NODES];
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UCHAR HalpNodeBucket[MAX_NODES];
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#ifdef ALLOC_PRAGMA
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#pragma alloc_text(PAGELK,HalpGetSystemInterruptVector)
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#pragma alloc_text(PAGE, HalIrqTranslateResourceRequirementsRoot)
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#pragma alloc_text(PAGE, HalTranslatorReference)
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#pragma alloc_text(PAGE, HalTranslatorDereference)
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#endif
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BOOLEAN
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HalpFindBusAddressTranslation(
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IN PHYSICAL_ADDRESS BusAddress,
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IN OUT PULONG AddressSpace,
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OUT PPHYSICAL_ADDRESS TranslatedAddress,
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IN OUT PULONG_PTR Context,
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IN BOOLEAN NextBus
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)
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/*++
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Routine Description:
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This routine performs a very similar function to HalTranslateBusAddress
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except that InterfaceType and BusNumber are not known by the caller.
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This function will walk all busses known by the HAL looking for a
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valid translation for the input BusAddress of type AddressSpace.
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This function is recallable using the input/output Context parameter.
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On the first call to this routine for a given translation the ULONG_PTR
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Context should be NULL. Note: Not the address of it but the contents.
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If the caller decides the returned translation is not the desired
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translation, it calls this routine again passing Context in as it
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was returned on the previous call. This allows this routine to
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traverse the bus structures until the correct translation is found
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and is provided because on multiple bus systems, it is possible for
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the same resource to exist in the independent address spaces of
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multiple busses.
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Arguments:
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BusAddress Address to be translated.
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AddressSpace 0 = Memory
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1 = IO (There are other possibilities).
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N.B. This argument is a pointer, the value
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will be modified if the translated address
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is of a different address space type from
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the untranslated bus address.
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TranslatedAddress Pointer to where the translated address
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should be stored.
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Context Pointer to a ULONG_PTR. On the initial call,
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for a given BusAddress, it should contain
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0. It will be modified by this routine,
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on subsequent calls for the same BusAddress
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the value should be handed in again,
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unmodified by the caller.
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NextBus FALSE if we should attempt this translation
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on the same bus as indicated by Context,
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TRUE if we should be looking for another
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bus.
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Return Value:
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TRUE if translation was successful,
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FALSE otherwise.
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--*/
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{
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//
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// First, make sure the context parameter was supplied and is
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// being used correctly. This also ensures that the caller
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// doesn't get stuck in a loop looking for subsequent translations
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// for the same thing. We won't succeed the same translation twice
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// unless the caller reinits the context.
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//
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if ((!Context) || (*Context && (NextBus == TRUE))) {
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return FALSE;
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}
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*Context = 1;
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//
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// PC/AT (halx86) case is simplest, there is no translation.
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//
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*TranslatedAddress = BusAddress;
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return TRUE;
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}
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BOOLEAN
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HalpTranslateSystemBusAddress(
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PHYSICAL_ADDRESS BusAddress,
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IN OUT PULONG AddressSpace,
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OUT PPHYSICAL_ADDRESS TranslatedAddress
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)
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/*++
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Routine Description:
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This function translates a bus-relative address space and address into
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a system physical address.
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Arguments:
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BusAddress - Supplies the bus-relative address
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AddressSpace - Supplies the address space number.
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Returns the host address space number.
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AddressSpace == 0 => memory space
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AddressSpace == 1 => I/O space
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TranslatedAddress - Supplies a pointer to return the translated address
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Return Value:
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A return value of TRUE indicates that a system physical address
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corresponding to the supplied bus relative address and bus address
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number has been returned in TranslatedAddress.
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A return value of FALSE occurs if the translation for the address was
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not possible
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--*/
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{
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BOOLEAN status;
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PSUPPORTED_RANGE pRange;
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status = FALSE;
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switch (*AddressSpace) {
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case 0:
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if (BusHandler->InterfaceType != PCIBus) {
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// verify memory address is within buses memory limits
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pRange = &BusHandler->BusAddresses->Memory;
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while (!status && pRange) {
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status = BusAddress.QuadPart >= pRange->Base &&
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BusAddress.QuadPart <= pRange->Limit;
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pRange = pRange->Next;
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}
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pRange = &BusHandler->BusAddresses->PrefetchMemory;
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while (!status && pRange) {
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status = BusAddress.QuadPart >= pRange->Base &&
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BusAddress.QuadPart <= pRange->Limit;
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pRange = pRange->Next;
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}
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} else {
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//
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// This is a PCI bus and SystemBase is constant for all ranges
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//
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pRange = &BusHandler->BusAddresses->Memory;
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status = TRUE;
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}
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break;
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case 1:
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if (BusHandler->InterfaceType != PCIBus) {
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// verify IO address is within buses IO limits
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pRange = &BusHandler->BusAddresses->IO;
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while (!status && pRange) {
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status = BusAddress.QuadPart >= pRange->Base &&
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BusAddress.QuadPart <= pRange->Limit;
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pRange = pRange->Next;
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}
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} else {
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//
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// This is a PCI bus and SystemBase is constant for all ranges
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//
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pRange = &BusHandler->BusAddresses->IO;
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status = TRUE;
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}
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break;
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default:
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status = FALSE;
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break;
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}
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if (status) {
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*TranslatedAddress = BusAddress;
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}
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#if !defined(_WIN64)
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else {
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_asm { nop }; // good for debugging
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}
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#endif
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return status;
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}
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#define MAX_SYSTEM_IRQL 31
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#define MAX_FREE_IRQL 26
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#define MIN_FREE_IRQL 4
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#define MAX_FREE_IDTENTRY 0xbf
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#define MIN_FREE_IDTENTRY 0x51
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#define IDTENTRY_BASE 0x50
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#define MAX_VBUCKET 7
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#define AllocateVectorIn(index) \
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vBucket[index]++; \
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ASSERT (vBucket[index] < 16);
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#define GetIDTEntryFrom(index) \
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(UCHAR) ( index*16 + IDTENTRY_BASE + vBucket[index] )
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// note: device levels 50,60,70,80,90,A0,B0 are not allocatable
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#define GetIrqlFrom(index) (KIRQL) ( index + MIN_FREE_IRQL )
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UCHAR nPriority[MAX_NODES][MAX_VBUCKET];
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ULONG
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HalpGetSystemInterruptVector (
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN ULONG InterruptLevel,
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IN ULONG InterruptVector,
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OUT PKIRQL Irql,
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OUT PKAFFINITY Affinity
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)
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/*++
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Routine Description:
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This function returns the system interrupt vector and IRQL
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corresponding to the specified bus interrupt level and/or
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vector. The system interrupt vector and IRQL are suitable
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for use in a subsequent call to KeInitializeInterrupt.
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Arguments:
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InterruptLevel - Supplies the bus specific interrupt level.
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InterruptVector - Supplies the bus specific interrupt vector.
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Irql - Returns the system request priority.
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Affinity - Returns the system wide irq affinity.
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Return Value:
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Returns the system interrupt vector corresponding to the specified device.
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--*/
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{
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ULONG SystemVector;
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USHORT ApicInti;
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UCHAR IDTEntry;
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ULONG Bucket, i, OldLevel;
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BOOLEAN Found;
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PVOID LockHandle;
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ULONG Node;
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PUCHAR vBucket;
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UNREFERENCED_PARAMETER( InterruptVector );
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//
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// TODO: Remove when Affinity becomes IN OUT.
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*Affinity = ~0;
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//
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// Restrict Affinity if required.
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if (HalpMaxProcsPerCluster == 0) {
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*Affinity &= HalpDefaultInterruptAffinity;
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}
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//
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// Find closest child bus to this handler
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//
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if (RootHandler != BusHandler) {
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while (RootHandler->ParentHandler != BusHandler) {
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RootHandler = RootHandler->ParentHandler;
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}
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}
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//
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// Find Interrupt's APIC Inti connection
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//
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Found = HalpGetApicInterruptDesc (
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RootHandler->InterfaceType,
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RootHandler->BusNumber,
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InterruptLevel,
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&ApicInti
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);
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if (!Found) {
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return 0;
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}
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//
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// If device interrupt vector mapping is not already allocated,
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// then do it now
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//
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if (!HalpINTItoVector[ApicInti]) {
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//
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// Vector is not allocated - synchronize and check again
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//
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LockHandle = MmLockPagableCodeSection (&HalpGetSystemInterruptVector);
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OldLevel = HalpAcquireHighLevelLock (&HalpAccountingLock);
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if (!HalpINTItoVector[ApicInti]) {
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//
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// Still not allocated
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//
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//
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// Pick a node. In the future, Affinity will be INOUT and
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// we will have to screen the node against the input affinity.
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if (HalpMaxNode == 1) {
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Node = 1;
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} else {
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//
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// Find a node that meets the affinity requirements.
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// Nodes are numbered 1..n, so 0 means we are done.
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for (i = HalpMaxNode; i; i--) {
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if ((*Affinity & HalpNodeAffinity[i-1]) == 0)
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continue;
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Node = i;
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break;
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}
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ASSERT(Node != 0);
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//
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// Look for a "less busy" alternative.
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for (i = Node-1; i; i--) {
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//
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// Check input Affinity to see if this node is permitted.
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if ((*Affinity & HalpNodeAffinity[i-1]) == 0)
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continue;
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//
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// Take the least busy of the permitted nodes.
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if (HalpNodeBucket[i-1] < HalpNodeBucket[Node-1]) {
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Node = i;
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}
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}
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}
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HalpNodeBucket[Node-1]++;
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*Affinity = HalpNodeAffinity[Node-1];
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vBucket = nPriority[Node-1];
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//
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// Choose the least busy priority on the node.
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Bucket = MAX_VBUCKET-1;
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for (i = Bucket-1; i; i--) {
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if (vBucket[i] < vBucket[Bucket]) {
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Bucket = i;
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}
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}
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AllocateVectorIn (Bucket);
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//
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// Now form the vector for the kernel.
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IDTEntry = GetIDTEntryFrom (Bucket);
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SystemVector = HalpVector(Node, IDTEntry);
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ASSERT(IDTEntry <= MAX_FREE_IDTENTRY);
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ASSERT(IDTEntry >= MIN_FREE_IDTENTRY);
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#if defined(_AMD64_)
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*Irql = (KIRQL)(IDTEntry >> 4);
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#else
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*Irql = GetIrqlFrom (Bucket);
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#endif
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ASSERT(*Irql <= MAX_FREE_IRQL);
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#if !defined(_WIN64)
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ASSERT((UCHAR) (HalpIRQLtoTPR[*Irql] & 0xf0) == (UCHAR) (IDTEntry & 0xf0) );
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#endif
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HalpVectorToIRQL[IDTEntry >> 4] = (UCHAR) *Irql;
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HalpVectorToINTI[SystemVector] = (USHORT) ApicInti;
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HalpINTItoVector[ApicInti] = SystemVector;
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//
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// If this assigned interrupt is connected to the machines PIC,
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// then remember the PIC->SystemVector mapping.
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//
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if (RootHandler->BusNumber == 0 && InterruptLevel < 16 &&
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RootHandler->InterfaceType == DEFAULT_PC_BUS) {
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HalpPICINTToVector[InterruptLevel] = (UCHAR) SystemVector;
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}
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}
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HalpReleaseHighLevelLock (&HalpAccountingLock, OldLevel);
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MmUnlockPagableImageSection (LockHandle);
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}
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//
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// Return this ApicInti's system vector & irql
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//
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SystemVector = HalpINTItoVector[ApicInti];
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*Irql = HalpVectorToIRQL[HalVectorToIDTEntry(SystemVector) >> 4];
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ASSERT(HalpVectorToINTI[SystemVector] == (USHORT) ApicInti);
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//
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// Find an appropriate affinity.
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//
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Node = HalpVectorToNode(SystemVector);
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*Affinity &= HalpNodeAffinity[Node-1];
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if (!*Affinity) {
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return 0;
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}
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return SystemVector;
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}
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VOID
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HalpSetInternalVector (
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IN ULONG InternalVector,
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IN PHAL_INTERRUPT_SERVICE_ROUTINE HalInterruptServiceRoutine,
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IN PVOID Context,
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IN KIRQL Irql
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)
|
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/*++
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Routine Description:
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Used at init time to set IDT vectors for internal use.
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--*/
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{
|
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//
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// Remember this vector so it's reported as Hal internal usage
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//
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// HalpRegisterVector (
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// InternalUsage,
|
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// InternalVector,
|
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// InternalVector,
|
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// HalpVectorToIRQL[InternalVector >> 4]
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// );
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|
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//
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// Connect the IDT
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//
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KiSetHandlerAddressToIDTIrql(InternalVector,
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HalInterruptServiceRoutine,
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Context,
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Irql);
|
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}
|
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|
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//
|
|
// This section implements a "translator," which is the PnP-WDM way
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// of doing the same thing that the first part of this file does.
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//
|
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VOID
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HalTranslatorReference(
|
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PVOID Context
|
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)
|
|
{
|
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return;
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}
|
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|
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VOID
|
|
HalTranslatorDereference(
|
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PVOID Context
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)
|
|
{
|
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return;
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}
|
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|
|
NTSTATUS
|
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HalIrqTranslateResourcesRoot(
|
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IN PVOID Context,
|
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IN PCM_PARTIAL_RESOURCE_DESCRIPTOR Source,
|
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IN RESOURCE_TRANSLATION_DIRECTION Direction,
|
|
IN ULONG AlternativesCount, OPTIONAL
|
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IN IO_RESOURCE_DESCRIPTOR Alternatives[], OPTIONAL
|
|
IN PDEVICE_OBJECT PhysicalDeviceObject,
|
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OUT PCM_PARTIAL_RESOURCE_DESCRIPTOR Target
|
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)
|
|
/*++
|
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|
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Routine Description:
|
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|
|
This function takes a CM_PARTIAL_RESOURCE_DESCRIPTOR and translates
|
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it to an IO-bus-relative from a Processor-bus-relative form, or the other
|
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way around. In this x86-specific example, an IO-bus-relative form is the
|
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ISA IRQ and the Processor-bus-relative form is the IDT entry and the
|
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associated IRQL.
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N.B. This funtion has an associated "Direction." These are not exactly
|
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reciprocals. This has to be the case because the output from
|
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HalIrqTranslateResourceRequirementsRoot will be used as the input
|
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for the ParentToChild case.
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ChildToParent:
|
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|
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Level (ISA IRQ) -> IRQL
|
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Vector (ISA IRQ) -> x86 IDT entry
|
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Affinity (not refereced)-> KAFFINITY
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ParentToChild:
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Level (not referenced) -> (ISA IRQ)
|
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Vector (IDT entry) -> (ISA IRQ)
|
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Affinity -> 0xffffffff
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Arguments:
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Context - unused
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Source - descriptor that we are translating
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Direction - direction of translation (parent to child or child to parent)
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AlternativesCount - unused
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Alternatives - unused
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PhysicalDeviceObject- unused
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Target - translated descriptor
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Return Value:
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|
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status
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|
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--*/
|
|
{
|
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NTSTATUS status = STATUS_SUCCESS;
|
|
PBUS_HANDLER bus;
|
|
KAFFINITY affinity;
|
|
KIRQL irql;
|
|
ULONG vector;
|
|
USHORT inti;
|
|
#ifdef ACPI_HAL
|
|
BUS_HANDLER fakeIsaBus;
|
|
#endif
|
|
|
|
PAGED_CODE();
|
|
|
|
UNREFERENCED_PARAMETER(AlternativesCount);
|
|
UNREFERENCED_PARAMETER(Alternatives);
|
|
UNREFERENCED_PARAMETER(PhysicalDeviceObject);
|
|
|
|
ASSERT(Source->Type == CmResourceTypeInterrupt);
|
|
|
|
switch (Direction) {
|
|
case TranslateChildToParent:
|
|
|
|
#ifdef ACPI_HAL
|
|
|
|
RtlCopyMemory(&fakeIsaBus, &HalpFakePciBusHandler, sizeof(BUS_HANDLER));
|
|
fakeIsaBus.InterfaceType = Isa;
|
|
fakeIsaBus.ParentHandler = &fakeIsaBus;
|
|
bus = &fakeIsaBus;
|
|
#else
|
|
|
|
if ((INTERFACE_TYPE)Context == InterfaceTypeUndefined) { // special "IDE" cookie
|
|
|
|
ASSERT(Source->u.Interrupt.Level == Source->u.Interrupt.Vector);
|
|
|
|
bus = HalpFindIdeBus(Source->u.Interrupt.Vector);
|
|
|
|
} else {
|
|
|
|
bus = HaliHandlerForBus((INTERFACE_TYPE)Context, 0);
|
|
}
|
|
|
|
if (!bus) {
|
|
return STATUS_NOT_FOUND;
|
|
}
|
|
#endif
|
|
|
|
//
|
|
// Copy everything
|
|
//
|
|
*Target = *Source;
|
|
|
|
//
|
|
// Translate the IRQ
|
|
//
|
|
|
|
vector = HalpGetEisaInterruptVector(bus,
|
|
bus,
|
|
Source->u.Interrupt.Level,
|
|
Source->u.Interrupt.Vector,
|
|
&irql,
|
|
&affinity);
|
|
|
|
if (vector == 0) {
|
|
return STATUS_UNSUCCESSFUL;
|
|
}
|
|
|
|
Target->u.Interrupt.Level = irql;
|
|
Target->u.Interrupt.Vector = vector;
|
|
Target->u.Interrupt.Affinity = affinity;
|
|
|
|
if (NT_SUCCESS(status)) {
|
|
status = STATUS_TRANSLATION_COMPLETE;
|
|
}
|
|
|
|
break;
|
|
|
|
case TranslateParentToChild:
|
|
|
|
//
|
|
// Copy everything
|
|
//
|
|
*Target = *Source;
|
|
|
|
//
|
|
// There is no inverse to HalpGetSystemInterruptVector, so we
|
|
// just do what that function would do.
|
|
//
|
|
|
|
inti = HalpVectorToINTI[Source->u.Interrupt.Vector];
|
|
|
|
Target->u.Interrupt.Level = Target->u.Interrupt.Vector =
|
|
HalpInti2BusInterruptLevel(inti);
|
|
|
|
Target->u.Interrupt.Affinity = 0xFFFFFFFF;
|
|
|
|
status = STATUS_SUCCESS;
|
|
|
|
break;
|
|
|
|
default:
|
|
status = STATUS_INVALID_PARAMETER;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
NTSTATUS
|
|
HalIrqTranslateResourceRequirementsRoot(
|
|
IN PVOID Context,
|
|
IN PIO_RESOURCE_DESCRIPTOR Source,
|
|
IN PDEVICE_OBJECT PhysicalDeviceObject,
|
|
OUT PULONG TargetCount,
|
|
OUT PIO_RESOURCE_DESCRIPTOR *Target
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function takes an IO_RESOURCE_DESCRIPTOR and translates
|
|
it from an IO-bus-relative to a Processor-bus-relative form. In this
|
|
x86-specific example, an IO-bus-relative form is the ISA IRQ and the
|
|
Processor-bus-relative form is the IDT entry and the associated IRQL.
|
|
This is essentially a PnP form of HalGetInterruptVector.
|
|
|
|
Arguments:
|
|
|
|
Context - unused
|
|
|
|
Source - descriptor that we are translating
|
|
|
|
PhysicalDeviceObject- unused
|
|
|
|
TargetCount - 1
|
|
|
|
Target - translated descriptor
|
|
|
|
Return Value:
|
|
|
|
status
|
|
|
|
--*/
|
|
{
|
|
PBUS_HANDLER bus;
|
|
KAFFINITY affinity;
|
|
KIRQL irql;
|
|
ULONG vector;
|
|
BOOLEAN success = TRUE;
|
|
#ifdef ACPI_HAL
|
|
BUS_HANDLER fakeIsaBus;
|
|
#endif
|
|
|
|
PAGED_CODE();
|
|
|
|
ASSERT(Source->Type == CmResourceTypeInterrupt);
|
|
|
|
#ifdef ACPI_HAL
|
|
|
|
RtlCopyMemory(&fakeIsaBus, &HalpFakePciBusHandler, sizeof(BUS_HANDLER));
|
|
fakeIsaBus.InterfaceType = Isa;
|
|
fakeIsaBus.ParentHandler = &fakeIsaBus;
|
|
bus = &fakeIsaBus;
|
|
#else
|
|
|
|
if ((INTERFACE_TYPE)Context == InterfaceTypeUndefined) { // special "IDE" cookie
|
|
|
|
ASSERT(Source->u.Interrupt.MinimumVector == Source->u.Interrupt.MaximumVector);
|
|
|
|
bus = HalpFindIdeBus(Source->u.Interrupt.MinimumVector);
|
|
|
|
} else {
|
|
|
|
bus = HaliHandlerForBus((INTERFACE_TYPE)Context, 0);
|
|
}
|
|
|
|
if (!bus) {
|
|
|
|
//
|
|
// There is no valid translation.
|
|
//
|
|
|
|
*TargetCount = 0;
|
|
return STATUS_TRANSLATION_COMPLETE;
|
|
}
|
|
#endif
|
|
|
|
//
|
|
// The interrupt requirements were obtained by calling HalAdjustResourceList
|
|
// so we don't need to call it again.
|
|
//
|
|
|
|
*Target = ExAllocatePoolWithTag(PagedPool,
|
|
sizeof(IO_RESOURCE_DESCRIPTOR),
|
|
HAL_POOL_TAG
|
|
);
|
|
|
|
if (!*Target) {
|
|
return STATUS_INSUFFICIENT_RESOURCES;
|
|
}
|
|
|
|
*TargetCount = 1;
|
|
|
|
//
|
|
// Copy the requirement unchanged
|
|
//
|
|
|
|
**Target = *Source;
|
|
|
|
//
|
|
// Perform the translation of the minimum & maximum
|
|
//
|
|
|
|
vector = HalpGetEisaInterruptVector(bus,
|
|
bus,
|
|
Source->u.Interrupt.MinimumVector,
|
|
Source->u.Interrupt.MinimumVector,
|
|
&irql,
|
|
&affinity);
|
|
|
|
if (!vector) {
|
|
success = FALSE;
|
|
}
|
|
|
|
(*Target)->u.Interrupt.MinimumVector = vector;
|
|
|
|
vector = HalpGetEisaInterruptVector(bus,
|
|
bus,
|
|
Source->u.Interrupt.MaximumVector,
|
|
Source->u.Interrupt.MaximumVector,
|
|
&irql,
|
|
&affinity);
|
|
|
|
if (!vector) {
|
|
success = FALSE;
|
|
}
|
|
|
|
(*Target)->u.Interrupt.MaximumVector = vector;
|
|
|
|
if (!success) {
|
|
|
|
ExFreePool(*Target);
|
|
*TargetCount = 0;
|
|
}
|
|
|
|
return STATUS_TRANSLATION_COMPLETE;
|
|
}
|
|
|
|
#if 0
|
|
|
|
// HALMPS doesn't provide this function. It is left here as documentation
|
|
// for HALs which must provide translation.
|
|
|
|
NTSTATUS
|
|
HalpTransMemIoResourceRequirement(
|
|
IN PVOID Context,
|
|
IN PIO_RESOURCE_DESCRIPTOR Source,
|
|
IN PDEVICE_OBJECT PhysicalDeviceObject,
|
|
OUT PULONG TargetCount,
|
|
OUT PIO_RESOURCE_DESCRIPTOR *Target
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This routine translates memory and IO resource requirements.
|
|
|
|
Parameters:
|
|
|
|
Context - The context from the TRANSLATOR_INTERFACE
|
|
|
|
Source - The interrupt requirement to translate
|
|
|
|
PhysicalDeviceObject - The device requesting the resource
|
|
|
|
TargetCount - Pointer to where to return the number of descriptors this
|
|
requirement translates into
|
|
|
|
Target - Pointer to where a pointer to a callee allocated buffer containing
|
|
the translated descriptors should be placed.
|
|
|
|
Return Value:
|
|
|
|
STATUS_SUCCESS or an error status
|
|
|
|
Note:
|
|
|
|
We do not perform any translation.
|
|
|
|
--*/
|
|
|
|
{
|
|
ASSERT(Source);
|
|
ASSERT(Target);
|
|
ASSERT(TargetCount);
|
|
ASSERT(Source->Type == CmResourceTypeMemory ||
|
|
Source->Type == CmResourceTypePort);
|
|
|
|
|
|
//
|
|
// Allocate space for the target
|
|
//
|
|
|
|
*Target = ExAllocatePoolWithTag(PagedPool,
|
|
sizeof(IO_RESOURCE_DESCRIPTOR),
|
|
HAL_POOL_TAG
|
|
);
|
|
|
|
if (!*Target) {
|
|
return STATUS_INSUFFICIENT_RESOURCES;
|
|
}
|
|
|
|
//
|
|
// Copy the source to target and update the fields that have changed
|
|
//
|
|
|
|
**Target = *Source;
|
|
*TargetCount = 1;
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
NTSTATUS
|
|
HalpTransMemIoResource(
|
|
IN PVOID Context,
|
|
IN PCM_PARTIAL_RESOURCE_DESCRIPTOR Source,
|
|
IN RESOURCE_TRANSLATION_DIRECTION Direction,
|
|
IN ULONG AlternativesCount, OPTIONAL
|
|
IN IO_RESOURCE_DESCRIPTOR Alternatives[], OPTIONAL
|
|
IN PDEVICE_OBJECT PhysicalDeviceObject,
|
|
OUT PCM_PARTIAL_RESOURCE_DESCRIPTOR Target
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This routine translates memory and IO resources. On generic x86
|
|
machines, such as those that use this HAL, there isn't actually
|
|
any translation.
|
|
|
|
Parameters:
|
|
|
|
Context - The context from the TRANSLATOR_INTERFACE
|
|
|
|
Source - The interrupt resource to translate
|
|
|
|
Direction - The direction in relation to the Pnp device tree translation
|
|
should occur in.
|
|
|
|
AlternativesCount - The number of alternatives this resource was selected
|
|
from.
|
|
|
|
Alternatives - Array of alternatives this resource was selected from.
|
|
|
|
PhysicalDeviceObject - The device requesting the resource
|
|
|
|
Target - Pointer to a caller allocated buffer to hold the translted resource
|
|
descriptor.
|
|
|
|
Return Value:
|
|
|
|
STATUS_SUCCESS or an error status
|
|
|
|
--*/
|
|
|
|
{
|
|
NTSTATUS status;
|
|
|
|
//
|
|
// Copy the target to the source
|
|
//
|
|
|
|
*Target = *Source;
|
|
|
|
switch (Direction) {
|
|
case TranslateChildToParent:
|
|
|
|
//
|
|
// Make sure PnP knows it doesn't have to walk up the tree
|
|
// translating at each point.
|
|
//
|
|
|
|
status = STATUS_TRANSLATION_COMPLETE;
|
|
break;
|
|
|
|
case TranslateParentToChild:
|
|
|
|
//
|
|
// We do not translate requirements so do nothing...
|
|
//
|
|
|
|
status = STATUS_SUCCESS;
|
|
break;
|
|
|
|
default:
|
|
status = STATUS_INVALID_PARAMETER;
|
|
}
|
|
return status;
|
|
}
|
|
#endif
|
|
|
|
NTSTATUS
|
|
HaliGetInterruptTranslator(
|
|
IN INTERFACE_TYPE ParentInterfaceType,
|
|
IN ULONG ParentBusNumber,
|
|
IN INTERFACE_TYPE BridgeInterfaceType,
|
|
IN USHORT Size,
|
|
IN USHORT Version,
|
|
OUT PTRANSLATOR_INTERFACE Translator,
|
|
IN OUT PULONG BridgeBusNumber
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
|
|
Arguments:
|
|
|
|
ParentInterfaceType - The type of the bus the bridge lives on (normally PCI).
|
|
|
|
ParentBusNumber - The number of the bus the bridge lives on.
|
|
|
|
BridgeInterfaceType - The bus type the bridge provides (ie ISA for a PCI-ISA bridge).
|
|
|
|
ResourceType - The resource type we want to translate.
|
|
|
|
Size - The size of the translator buffer.
|
|
|
|
Version - The version of the translator interface requested.
|
|
|
|
Translator - Pointer to the buffer where the translator should be returned
|
|
|
|
BridgeBusNumber - Pointer the bus number of the bus that the bridge represents
|
|
|
|
Return Value:
|
|
|
|
Returns the status of this operation.
|
|
|
|
--*/
|
|
#define BRIDGE_HEADER_BUFFER_SIZE (FIELD_OFFSET(PCI_COMMON_CONFIG, u.type1.SubordinateBus) + 1)
|
|
#define USE_INT_LINE_REGISTER_TOKEN 0xffffffff
|
|
#define DEFAULT_BRIDGE_TRANSLATOR 0x80000000
|
|
{
|
|
PAGED_CODE();
|
|
|
|
ASSERT(Version == HAL_IRQ_TRANSLATOR_VERSION);
|
|
ASSERT(Size >= sizeof(TRANSLATOR_INTERFACE));
|
|
|
|
//
|
|
// Fill in the common bits.
|
|
//
|
|
|
|
RtlZeroMemory(Translator, sizeof(TRANSLATOR_INTERFACE));
|
|
|
|
Translator->Size = sizeof(TRANSLATOR_INTERFACE);
|
|
Translator->Version = HAL_IRQ_TRANSLATOR_VERSION;
|
|
Translator->Context = (PVOID)BridgeInterfaceType;
|
|
Translator->InterfaceReference = HalTranslatorReference;
|
|
Translator->InterfaceDereference = HalTranslatorDereference;
|
|
|
|
switch (BridgeInterfaceType) {
|
|
case Eisa:
|
|
case Isa:
|
|
case InterfaceTypeUndefined: // special "IDE" cookie
|
|
|
|
//
|
|
// Set IRQ translator for (E)ISA interrupts.
|
|
//
|
|
|
|
Translator->TranslateResources = HalIrqTranslateResourcesIsa;
|
|
Translator->TranslateResourceRequirements =
|
|
HalIrqTranslateResourceRequirementsIsa;
|
|
|
|
return STATUS_SUCCESS;
|
|
|
|
case MicroChannel:
|
|
|
|
//
|
|
// Set IRQ translator for MCA interrupts.
|
|
//
|
|
|
|
Translator->TranslateResources = HalIrqTranslateResourcesRoot;
|
|
Translator->TranslateResourceRequirements =
|
|
HalIrqTranslateResourceRequirementsRoot;
|
|
|
|
return STATUS_SUCCESS;
|
|
|
|
case PCIBus:
|
|
|
|
#ifndef ACPI_HAL
|
|
//
|
|
// Set of of two IRQ translators for PCI busses.
|
|
//
|
|
|
|
{
|
|
UCHAR mpsBusNumber = 0;
|
|
UCHAR pciBusNumber, parentPci, childPci;
|
|
PCI_SLOT_NUMBER bridgeSlot;
|
|
PCI_COMMON_CONFIG pciData;
|
|
ULONG bytesRead, d, f, possibleContext;
|
|
BOOLEAN describedByMps;
|
|
NTSTATUS status;
|
|
|
|
Translator->TranslateResources = HalpIrqTranslateResourcesPci;
|
|
Translator->TranslateResourceRequirements =
|
|
HalpIrqTranslateRequirementsPci;
|
|
|
|
//
|
|
// Look for this bus in the MPS tables.
|
|
//
|
|
|
|
status = HalpPci2MpsBusNumber((UCHAR)*BridgeBusNumber,
|
|
&mpsBusNumber);
|
|
|
|
if (NT_SUCCESS(status)) {
|
|
|
|
//
|
|
// This bus has corresponding entries for its PCI
|
|
// devices in the MPS tables. So eject the translator
|
|
// that understands them.
|
|
//
|
|
|
|
if (HalpInterruptsDescribedByMpsTable(mpsBusNumber)) {
|
|
|
|
Translator->Context = (PVOID)mpsBusNumber;
|
|
return STATUS_SUCCESS;
|
|
}
|
|
}
|
|
|
|
//
|
|
// Do a quick check to see if we can avoid searching PCI
|
|
// configuration space for a bridge. This code is really
|
|
// redundant, but it's worth trying to avoid touching
|
|
// PCI space.
|
|
//
|
|
|
|
if (ParentInterfaceType != PCIBus) {
|
|
|
|
//
|
|
// This was a PCI bus that doesn't contain
|
|
// mappings for PCI devices.
|
|
//
|
|
|
|
Translator->TranslateResources =
|
|
HalpIrqTranslateResourcesPci;
|
|
Translator->TranslateResourceRequirements =
|
|
HalpIrqTranslateRequirementsPci;
|
|
|
|
Translator->Context = (PVOID)USE_INT_LINE_REGISTER_TOKEN;
|
|
|
|
return STATUS_SUCCESS;
|
|
|
|
}
|
|
|
|
//
|
|
// We didn't find this PCI bus in the MPS tables. So there
|
|
// are two cases.
|
|
//
|
|
// 1) This matters, because the parent bus is fully described
|
|
// in the MPS tables and we need to do translations on
|
|
// the vector as it passes through the bridges.
|
|
//
|
|
// 2) This doesn't matter, because the parent busses, while
|
|
// they may be in the MPS tables, they don't have any
|
|
// of their interrupts described. So we just use the
|
|
// interrupt line register anyhow.
|
|
//
|
|
// At this point we need to find the PCI bridge that
|
|
// generates this bus, either because we will eventually
|
|
// need to know the slot number to fill in the context, or
|
|
// because we will need to know the primary bus number to
|
|
// look up the tree.
|
|
//
|
|
|
|
parentPci = (UCHAR)ParentBusNumber;
|
|
childPci = (UCHAR)(*BridgeBusNumber);
|
|
|
|
while (TRUE) {
|
|
|
|
//
|
|
// Find the bridge.
|
|
//
|
|
|
|
bridgeSlot.u.AsULONG = 0;
|
|
|
|
for (d = 0; d < PCI_MAX_DEVICES; d++) {
|
|
for (f = 0; f < PCI_MAX_FUNCTION; f++) {
|
|
|
|
bridgeSlot.u.bits.DeviceNumber = d;
|
|
bridgeSlot.u.bits.FunctionNumber = f;
|
|
|
|
bytesRead = HalGetBusDataByOffset(PCIConfiguration,
|
|
parentPci,
|
|
bridgeSlot.u.AsULONG,
|
|
&pciData,
|
|
0,
|
|
BRIDGE_HEADER_BUFFER_SIZE);
|
|
|
|
if (bytesRead == (ULONG)BRIDGE_HEADER_BUFFER_SIZE) {
|
|
|
|
if ((pciData.VendorID != PCI_INVALID_VENDORID) &&
|
|
(PCI_CONFIGURATION_TYPE((&pciData)) != PCI_DEVICE_TYPE)) {
|
|
|
|
//
|
|
// This is a bridge of some sort.
|
|
//
|
|
|
|
if (pciData.u.type1.SecondaryBus == childPci) {
|
|
|
|
//
|
|
// And it is the bridge we are looking for.
|
|
// Store information about
|
|
//
|
|
|
|
if (childPci == *BridgeBusNumber) {
|
|
|
|
//
|
|
// It is also the bridge that creates the
|
|
// PCI bus that the translator is describing.
|
|
//
|
|
// N.B. This should only happen the first time
|
|
// we search through a bus. (i.e. the first
|
|
// trip through the outer while loop)
|
|
//
|
|
|
|
possibleContext = ((bridgeSlot.u.AsULONG & 0xffff) |
|
|
(ParentBusNumber << 16));
|
|
|
|
}
|
|
|
|
goto HGITFoundBridge1;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
//
|
|
// No bridge found.
|
|
//
|
|
|
|
if (parentPci == 0) {
|
|
return STATUS_NOT_FOUND;
|
|
}
|
|
|
|
parentPci--;
|
|
continue;
|
|
|
|
HGITFoundBridge1:
|
|
|
|
status = HalpPci2MpsBusNumber(parentPci, &mpsBusNumber);
|
|
|
|
if (NT_SUCCESS(status)) {
|
|
|
|
if (HalpInterruptsDescribedByMpsTable(mpsBusNumber)) {
|
|
|
|
//
|
|
// Case 1 above.
|
|
//
|
|
|
|
Translator->TranslateResources = HalIrqTranslateResourcesPciBridge;
|
|
Translator->TranslateResourceRequirements =
|
|
HalIrqTranslateRequirementsPciBridge;
|
|
|
|
Translator->Context = (PVOID)possibleContext;
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
if (HalpMpsBusIsRootBus(mpsBusNumber)) {
|
|
|
|
Translator->TranslateResources =
|
|
HalpIrqTranslateResourcesPci;
|
|
Translator->TranslateResourceRequirements =
|
|
HalpIrqTranslateRequirementsPci;
|
|
|
|
Translator->Context = (PVOID)USE_INT_LINE_REGISTER_TOKEN;
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|
|
}
|
|
|
|
//
|
|
// Try again one bus higher.
|
|
//
|
|
|
|
childPci = parentPci;
|
|
parentPci--;
|
|
}
|
|
}
|
|
#endif
|
|
break;
|
|
}
|
|
|
|
|
|
//
|
|
// If we got here, we don't have an interface.
|
|
//
|
|
|
|
return STATUS_NOT_IMPLEMENTED;
|
|
}
|
|
|
|
|