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862 lines
21 KiB
862 lines
21 KiB
;/*++
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;
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;Module Name:
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;
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; ntapic.inc
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;
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;Abstract:
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;
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; This header file is intended to be included by any HAL
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; that uses APICs.
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;
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;Author:
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;
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; Ron Mosgrove (Intel)
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;
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;Environment:
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;
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; Kernel mode only.
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;
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;Revision History:
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;
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; Separated out from pcmp_nt.inc -- 6-2-98 (jakeo)
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;
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;
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if 0 ; Begin C only code */
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#if !defined(_NTAPIC_INC_)
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#define _NTAPIC_INC_ 1
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//#define DEBUGGING 1
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#ifndef DBGMSG
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#ifdef DEBUGGING
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extern CHAR Cbuf[];
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#define DBGMSG(x) DbgPrint(x);
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#else
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#define DBGMSG(x)
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#endif
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#endif
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//
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// To allow the user to specify command line options to the HAL.
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//
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#define USER_SETABLE_OPTIONS
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// #define BUILD_FOR_OLD_IDW
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//
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// Default BusType
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//
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#ifndef MCA
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#define DEFAULT_PC_BUS Eisa
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#else
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#define DEFAULT_PC_BUS MicroChannel
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#endif
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//
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// Well known virtual address of local processor apic
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//
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#if defined(_WIN64)
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#define LOCALAPIC 0xfffffffffffe0000
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#else
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#define LOCALAPIC 0xfffe0000
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#endif
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#define pLocalApic ((ULONG volatile *) LOCALAPIC)
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#define LOCAL_APIC(x) (*((ULONG volatile *)&pLocalApic[(x)/sizeof(ULONG)]))
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//
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// Additional CpuFlags Bits used by NT in PC+MP Table
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//
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#define CPU_NT_STARTED 0x40 // CPU Has Been Started
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#define CPU_NT_RUNNING 0x80 // CPU is Runing NT
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#define MAX_PROCESSORS 32
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#define MAX_CLUSTERS 15
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#define MAX_IOAPICS 64
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//
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// This OS specific structure holds useful MP information. This information
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// is obtained from the PC+MP table and stored here for convenience.
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//
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typedef struct HalpMpInfo {
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ULONG ApicVersion; // 82489Dx or Not
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ULONG ProcessorCount; // Number of Enabled Processors
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ULONG NtProcessors; // Number of Running Processors
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ULONG BusCount; // Number of buses in system
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ULONG IOApicCount; // Number of Io Apics in system
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ULONG IntiCount; // Number of Io Apic interrupt input entries
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ULONG LintiCount; // Number of Local Apic interrupt input entries
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ULONG IMCRPresent; // Indicates if the IMCR is present
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ULONG LocalApicBase; // Base of local APIC
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PULONG IoApicBase[MAX_IOAPICS]; // The virtual addresses of the IoApics
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ULONG IoApicPhys[MAX_IOAPICS]; // The physical addresses of the IoApics
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#ifdef ACPI_HAL
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ULONG IoApicIntiBase[MAX_IOAPICS]; // The 'number' of the first INTI -- only used for ACPI
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#else
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PPCMPPROCESSOR ProcessorEntryPtr; // Ptr to 1st PC+MP processor entry
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PPCMPBUS BusEntryPtr; // Ptr to 1st PC+MP bus entry
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PPCMPIOAPIC IoApicEntryPtr; // Ptr to 1st PC+MP IoApic entry
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PPCMPINTI IntiEntryPtr; // Ptr to 1st PC+MP Inti entry
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PPCMPLINTI LintiEntryPtr; // Ptr to 1st PC+MP Linti entry
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PMPS_EXTENTRY ExtensionTable; // Ptr to 1st extension table entry
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PMPS_EXTENTRY EndOfExtensionTable;
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#endif
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} MP_INFO, *PMP_INFO;
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typedef struct {
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PUCHAR PcMpType;
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BOOLEAN PhysicalInstance;
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UCHAR Level;
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INTERFACE_TYPE NtType;
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PINSTALL_BUS_HANDLER NewInstance;
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BUS_DATA_TYPE NtConfig;
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ULONG BusExtensionSize;
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} PCMPBUSTRANS, *PPCMPBUSTRANS;
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#define CFG_MUST_BE 0x02
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#define CFG_ERROR 0x80
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#define CFG_HIGH 0x01
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#define CFG_LOW 0x00
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#define CFG_EDGE 0x00
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#define CFG_LEVEL 0x01
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#define CFG_MB_EDGE (CFG_MUST_BE | CFG_EDGE)
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#define CFG_MB_LEVEL (CFG_MUST_BE | CFG_LEVEL)
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#define CFG_ERR_EDGE (CFG_ERROR | CFG_EDGE)
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#define CFG_ERR_LEVEL (CFG_ERROR | CFG_LEVEL)
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#define CFG_ERR_MB_EDGE (CFG_ERROR | CFG_MUST_BE | CFG_EDGE)
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#define CFG_ERR_MB_LEVEL (CFG_ERROR | CFG_MUST_BE | CFG_LEVEL)
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#define CFG_TYPE(a) (a & 1)
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typedef union _INTERRUPT_DEST {
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union _Cluster {
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struct _Hw {
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UCHAR DestId:4;
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UCHAR ClusterId:4;
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} Hw;
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UCHAR AsUchar;
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} Cluster;
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UCHAR LogicalId;
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} INTERRUPT_DEST, *PINTERRUPT_DEST;
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#if defined(_X86_)
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//
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// The kernel leaves some space (64 byte) of the PCR for the HAL to use
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// as it needs. Currently this space is used for some efficiency in
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// some of the MP specific code and is highly implementation-dependent.
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//
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typedef struct _HALPCR {
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UCHAR PcrNumber; // Processor's number
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UCHAR ShortDpc; // Short circut dpc interrupt
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UCHAR DpcPending; // Dpc interrupt pending
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UCHAR Reserved; // force dword alignment
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//
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// The next three dwords are used to manipulate the APIC counter
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//
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ULONG ApicClockFreqHz; // Counter Freq in Hertz
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ULONG ApicClockFreqKhz; // Counter Freq in Khertz (rounded)
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ULONG ProfileCountDown; // Current Countdown Interval
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ULONGLONG TSCHz; // Time stamp counter hertz
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ULONG PerfCounterLow; // PerProcessor Counter
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ULONG PerfCounterHigh;
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} HALPCR, *PHALPCR;
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#elif defined(_AMD64_)
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typedef struct _HALPCR {
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ULONG64 PerfCounter;
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ULONG64 TSCHz; // time stamp counter frequency
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ULONG ProfileCountDown; // current profile countdown interval
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ULONG ApicClockFreqHz; // counter frequency
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ULONG StallScaleFactor;
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ULONG ApicId; // APIC Id assigned this processor
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} HALPCR, *PHALPCR;
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C_ASSERT(sizeof(HALPCR) <= RTL_FIELD_SIZE(KPCR,HalReserved));
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#else
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#error "Platform not supported"
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#endif
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//
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// The kernel leaves some space (64 byte) of the PCRB for the HAL to use
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// as it needs. Currently this space is used for some efficiency in
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// some of the MP specific code and is highly implementation-dependent.
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//
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typedef struct {
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UCHAR PCMPApicID;
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UCHAR na[3];
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} HALPRCB, *PHALPRCB;
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#if defined(_AMD64_)
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#define ZERO_VECTOR 0x00 // IRQL 0 placeholder
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#define APC_VECTOR 0x1f // IRQL 1 APC
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#define DPC_VECTOR 0x2f // IRQL 2 DPC
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#define APIC_SPURIOUS_VECTOR 0x3f // IRQL 3 Spurious handler
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#define APIC_REBOOT_VECTOR 0x50 // IRQL 5 Vector used to reboot
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#define APIC_GENERIC_VECTOR 0xC1 // IRQL 12 broadcast function call
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#define APIC_CLOCK_VECTOR 0xD1 // IRQL 13 APIC INTI0 - CLOCK2_LEVEL
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#define APIC_SYNCH_VECTOR 0xD1 // IRQL 13 IPI_LEVEL-1
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#define APIC_IPI_VECTOR 0xE1 // IRQL 14 APIC IPI
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#define APIC_FAULT_VECTOR 0xE3 // IRQL 14
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#define POWERFAIL_VECTOR 0xEF // IRQL 14 reserved. not used
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#define APIC_PROFILE_VECTOR 0xFD // IRQL 15
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#define APIC_PERF_VECTOR 0xFE // IRQL 15
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#define NMI_VECTOR 0xFF // IRQL 15
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//
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// The APIC hard-wires the four low-order bits of the spurious interrupt
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// vector to 1.
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//
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C_ASSERT((APIC_SPURIOUS_VECTOR & 0x0f) == 0x0f);
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#else
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//
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// interrupt vector definitions for C
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//
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#define ZERO_VECTOR 0x00 // IRQL 00 placeholder
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#define APIC_SPURIOUS_VECTOR 0x1f // IRQL Spurious handler
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#define APC_VECTOR 0x3D // IRQL 01 APC
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#define DPC_VECTOR 0x41 // IRQL 02 DPC
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#define APIC_REBOOT_VECTOR 0x50 // IRQL Vector used to reboot
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#define APIC_GENERIC_VECTOR 0xC1 // IRQL 27 broadcast function call
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#define APIC_CLOCK_VECTOR 0xD1 // IRQL 28 APIC INTI0 - CLOCK2_LEVEL
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//
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// If MP, define APIC_SYNCH_LEVEL as SYNCH_LEVEL, otherwise define
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// to be the same as DPC_LEVEL.
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//
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#if (SYNCH_LEVEL != DISPATCH_LEVEL)
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#define APIC_SYNCH_VECTOR 0xC1 // IRQL 28 IPI_LEVEL-1
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#else
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#define APIC_SYNCH_VECTOR DPC_VECTOR // IRQL 02 if UNIPROCESSOR
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#endif
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#define APIC_IPI_VECTOR 0xE1 // IRQL 29 APIC IPI
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#define APIC_FAULT_VECTOR 0xE3 //
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#define POWERFAIL_VECTOR 0xEF // IRQL 30 reserved. not used
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#define APIC_PROFILE_VECTOR 0xFD // IRQL 31
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#define APIC_PERF_VECTOR 0xFE // IRQL 31
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#define NMI_VECTOR 0xFF // IRQL 31
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#endif
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//
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// 8259/ISP interrupt controller register addresses
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//
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#define PIC1_PORT0 0x20
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#define PIC1_PORT1 0x21
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#define PIC2_PORT0 0xA0
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#define PIC2_PORT1 0xA1
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#define PIC_SLAVE_IRQ 2
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#define RTC_IRQ 8
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#define PIC1_ELCR_PORT 0x04D0 // ISP edge/level control registers
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#define PIC2_ELCR_PORT 0x04D1
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#define PIC1_SPURIOUS_VECTOR 0x37
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//
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// Defines for HalpFeatureBits
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//
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extern ULONG HalpFeatureBits;
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//
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//
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//
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#if defined(_AMD64_) && defined(NT_UP)
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#define HalpAcquireHighLevelLock(lock) HalpDisableInterrupts()
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#define HalpReleaseHighLevelLock(lock,irql) HalpRestoreInterrupts(irql)
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#else
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ULONG FASTCALL HalpAcquireHighLevelLock(PKSPIN_LOCK);
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VOID FASTCALL HalpReleaseHighLevelLock(PKSPIN_LOCK, ULONG);
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#endif
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extern KSPIN_LOCK HalpAccountingLock;
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extern KAFFINITY HalpActiveProcessors;
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//
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// Prototypes
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//
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#define MAX_INTI (MAX_IOAPICS*32) // Max interrupt inputs from APICs
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#define MAX_SOURCE_IRQS MAX_INTI // Max different interrupts supported
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//
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// HalVectorToIDTEntry(vector) is defined in i386.h, because the kernel needs
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// it.
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#define MAX_NODES MAX_PROCESSORS
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#define HalpVectorToNode(vector) ((vector)>>8)
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#define HalpVector(node, idtentry) ((node)<<8|(idtentry))
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extern struct HalpMpInfo HalpMpInfoTable;
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extern UCHAR HalpMaxProcsPerCluster;
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extern BOOLEAN HalpELCRChecked;
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extern USHORT HalpGlobal8259Mask;
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extern USHORT HalpVectorToINTI[];
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extern UCHAR HalpInitLevel[4][4];
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extern UCHAR HalpDevPolarity[4][2];
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extern UCHAR HalpDevLevel[2][4];
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//
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// Initialized from MPS table
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//
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typedef struct _INTI_INFO {
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UCHAR Type:4;
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UCHAR Level:2;
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UCHAR Polarity:2;
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UCHAR Destinations;
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USHORT Entry;
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} INTI_INFO, *PINTI_INFO;
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extern INTI_INFO HalpIntiInfo[];
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extern USHORT HalpMaxApicInti[];
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extern PCMPBUSTRANS HalpTypeTranslation[];
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extern ULONG HalpIpiClock;
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#define BusIrq2Id(bus,no,irq) \
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((bus << 16) | (no << 8) | irq)
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#define Id2BusIrq(id) \
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(id & 0xff)
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VOID
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HalpInitIntiInfo (
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VOID
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);
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ULONG
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HalpGetIoApicId(
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ULONG ApicNo
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);
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VOID
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HalpSet8259Mask(
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IN USHORT Mask
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);
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VOID
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HalpInitializeLocalUnit (
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VOID
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);
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VOID
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HalpInitializeIOUnits (
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VOID
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);
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VOID
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HalpRestoreIoApicRedirTable (
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VOID
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);
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VOID
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HalpEnableNMI (
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VOID
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);
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VOID
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HalpEnableLocalNmiSources(
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VOID
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);
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VOID
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HalpSet8259Mask(
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IN USHORT Mask
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);
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BOOLEAN
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HalpGetApicInterruptDesc (
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IN INTERFACE_TYPE BusType,
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IN ULONG BusNumber,
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IN ULONG BusInterruptLevel,
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OUT PUSHORT PcMpInti
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);
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VOID
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HalpCheckELCR (
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VOID
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);
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VOID
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HalpGenericCall (
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VOID (*Fnc)(ULONG_PTR),
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ULONG Context,
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KAFFINITY Processors
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);
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VOID
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HalpPollForBroadcast (
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VOID
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);
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ULONG
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FASTCALL
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HalpWaitForPending (
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IN ULONG Count,
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IN volatile ULONG *LuICR
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);
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//
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// Warning 4131 is "uses old-style declarator"
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//
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#pragma warning(disable:4131)
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//
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// Warning 4218 is "nonstandard extension used"
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//
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#pragma warning(disable:4218)
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HAL_INTERRUPT_SERVICE_PROTOTYPE(HalpPerfInterrupt);
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VOID
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HalpEnablePerfInterupt (
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ULONG_PTR Context
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);
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VOID
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HalpEnableNMI (
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VOID
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);
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NTSTATUS
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HalpSetSystemInformation (
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IN HAL_SET_INFORMATION_CLASS InformationClass,
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IN ULONG BufferSize,
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IN PVOID Buffer
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);
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ULONG
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HalpInti2BusInterruptLevel(
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ULONG Inti
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);
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VOID
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HalpUnMapIOApics(
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VOID
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);
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VOID
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HalpInitializeIOUnits (
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VOID
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);
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VOID
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HalpPostSleepMP(
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IN LONG NumberProcessors,
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IN volatile PLONG Number
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);
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VOID
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HalpSetRedirEntry (
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IN USHORT InterruptInput,
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IN ULONG Entry,
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IN ULONG Destination
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);
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VOID
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HalpGetRedirEntry (
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IN USHORT InterruptInput,
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IN PULONG Entry,
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IN PULONG Destination
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);
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/*++
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HalpStallWhileApicBusy (
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VOID
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)
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Routine Description:
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This routine waits until the local apic has completed sending
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an IPI.
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Parameters:
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None.
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Return Value:
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None.
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--*/
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#define HalpStallWhileApicBusy() \
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while ((LOCAL_APIC(LU_INT_CMD_LOW) & DELIVERY_PENDING) != 0) { }
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#if defined(_AMD64_)
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#define HalpGetHalPcr(pcr) ((PHALPCR)(pcr->HalReserved))
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#define HalpGetCurrentHalPcr() HalpGetHalPcr(KeGetPcr())
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#endif
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#endif // _NTAPIC_INC_
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/*
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endif
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;
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; Begin assembly part of the definitions
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;
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;
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; Well known virtual address of local processor apic
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;
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LOCALAPIC equ 0fffe0000h
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APIC equ ds:[LOCALAPIC]
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DEBUGGING equ 0
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if DEBUGGING
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IRQL_METRICS equ 0
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endif
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;
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; To allow the user to specify command line options to the HAL.
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;
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USER_SETABLE_OPTIONS equ 1
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MAX_PROCESSORS equ 32
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MAX_NODES equ MAX_PROCESSORS
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MAX_IOAPICS equ 64
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;
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; This OS specific structure holds useful MP information. This information
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|
; is obtained from the PC+MP table and stored here for convenience.
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|
;
|
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|
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HalpMpInfo struc
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ApicVersion dd 0 ; 82489Dx or Not
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ProcessorCount dd 0 ; Number of Enabled Processors
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NtProcessors dd 0 ; Number of Running Processors
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BusCount dd 0 ; Number of buses in system
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|
IOApicCount dd 0 ; Number of Io Apics in system
|
|
IntiCount dd 0 ; Num of Io Apic interrupt inputs
|
|
LintiCount dd 0 ; Num of Local Apic interrupt inputs
|
|
IMCRPresent dd 0 ; Indicates if the IMCR is present
|
|
LocalApicBase dd 0 ; Base of local apic
|
|
IoApicBase dd MAX_IOAPICS dup (0) ; Virtual addresses of IoApics
|
|
IoApicPhys dd MAX_IOAPICS dup (0) ; Physical addresses of IoApics
|
|
ifdef ACPI_HAL
|
|
IoApicIntiBase dd MAX_IOAPICS dup (0) ; ACPI only. First GSIV.
|
|
else
|
|
ProcessorEntryPtr dd 0 ; Ptr to 1st PC+MP processor entry
|
|
BusEntryPtr dd 0 ; Ptr to 1st PC+MP bus entry
|
|
IoApicEntryPtr dd 0 ; Ptr to 1st PC+MP IoApic entry
|
|
IntiEntryPtr dd 0 ; Ptr to 1st PC+MP Inti entry
|
|
LintiEntryPtr dd 0 ; Ptr to 1st PC+MP Linti entry
|
|
ExtensionTable dd 0 ; Ptr to 1st extension table entry
|
|
EndExtensionTable dd 0 ; Ptr to 1st extension table entry
|
|
endif
|
|
HalpMpInfo ends
|
|
|
|
|
|
;
|
|
; interrupt vector definitions for assembler
|
|
;
|
|
|
|
ZERO_VECTOR equ 000h ; IRQL 00 placeholder
|
|
APIC_SPURIOUS_VECTOR equ 01fh ; Vector used for spurious handler
|
|
APC_VECTOR equ 03Dh ; IRQL 01 APC
|
|
DPC_VECTOR equ 041h ; IRQL 02 DPC
|
|
APIC_REBOOT_VECTOR equ 050h ; Vector used to reboot
|
|
DEVICE_LEVEL1 equ 051h
|
|
DEVICE_LEVEL2 equ 061h
|
|
DEVICE_LEVEL3 equ 071h
|
|
DEVICE_LEVEL4 equ 081h
|
|
DEVICE_LEVEL5 equ 091h
|
|
DEVICE_LEVEL6 equ 0A1h
|
|
DEVICE_LEVEL7 equ 0B1h
|
|
APIC_GENERIC_VECTOR equ 0C1h ; IRQL 27 broadcast function call
|
|
APIC_CLOCK_VECTOR equ 0D1h ; IRQL 28 APIC INTI0 - CLOCK2_LEVEL
|
|
|
|
if SYNCH_LEVEL-DISPATCH_LEVEL
|
|
|
|
APIC_SYNCH_VECTOR equ 0C1h ; IRQL 28 IPI_LEVEL-1
|
|
|
|
else
|
|
|
|
APIC_SYNCH_VECTOR equ DPC_VECTOR
|
|
|
|
endif
|
|
|
|
APIC_IPI_VECTOR equ 0E1h ; IRQL 29 APIC IPI
|
|
|
|
APIC_FAULT_VECTOR equ 0E3h ;
|
|
POWERFAIL_VECTOR equ 0EFh ; IRQL 30 reserved
|
|
|
|
APIC_PROFILE_VECTOR equ 0FDh ; IRQL 27
|
|
APIC_PERF_VECTOR equ 0FEh ; IRQL 27
|
|
NMI_VECTOR equ 0FFh ; IRQL 31
|
|
|
|
HAL_PROFILE_LEVEL equ HIGH_LEVEL
|
|
|
|
;
|
|
; 8259/ISP interrupt controller register addresses
|
|
;
|
|
|
|
PIC1_PORT0 equ 020H
|
|
PIC1_PORT1 equ 021H
|
|
PIC2_PORT0 equ 0A0H
|
|
PIC2_PORT1 equ 0A1H
|
|
|
|
PIC1_ELCR_PORT equ 04D0H ; ISP edge/level control registers
|
|
PIC2_ELCR_PORT equ 04D1H
|
|
|
|
;
|
|
; Initialization control words for the PICs
|
|
;
|
|
|
|
ICW1_ICW4_NEEDED equ 01H
|
|
ICW1_CASCADE equ 00H
|
|
ICW1_INTERVAL8 equ 00H
|
|
ICW1_LEVEL_TRIG equ 08H
|
|
ICW1_EDGE_TRIG equ 00H
|
|
ICW1_ICW equ 10H
|
|
|
|
ICW4_8086_MODE equ 001H
|
|
ICW4_AUTO_EOI equ 002H
|
|
ICW4_NORM_EOI equ 000H
|
|
ICW4_NON_BUF_MODE equ 000H
|
|
ICW4_SPEC_FULLY_NESTED equ 010H
|
|
ICW4_NOT_SPEC_FULLY_NESTED equ 000H
|
|
|
|
PIC_SLAVE_IRQ equ 2
|
|
|
|
PIC1_BASE equ 30H
|
|
PIC2_BASE equ 38H
|
|
PIC_CLOCK_VECTOR equ 30H
|
|
PIC_DMA_VECTOR equ 3DH
|
|
PIC1_SPURIOUS_VECTOR equ 37H
|
|
PIC2_SPURIOUS_VECTOR equ 3FH
|
|
|
|
;
|
|
; Operation control words for the PICs
|
|
;
|
|
|
|
OCW2_NON_SPECIFIC_EOI equ 020H
|
|
OCW2_SPECIFIC_EOI equ 060H
|
|
OCW3_READ_ISR equ 0BH
|
|
OCW3_READ_IRR equ 0AH
|
|
OCW3_READ_POLLED equ 0CH
|
|
|
|
;
|
|
; A couple of definitions that shouldn't change on a Compatible
|
|
;
|
|
|
|
TimerPicInti equ 0
|
|
DmaPic2Inti equ 5
|
|
SlavePicInti equ 2
|
|
DmaPicInti equ 13 ; DMA input relative to 0
|
|
|
|
cr equ 0ah
|
|
lf equ 0dh
|
|
|
|
;
|
|
; The kernel leaves some space (64 byte) of the PCR for the HAL to use
|
|
; as it needs. Currently this space is used for some efficiency in
|
|
; some of the MP specific code and is highly implementation-dependent.
|
|
;
|
|
|
|
|
|
PcrE struc
|
|
PcrNumber db 0 ; Processor's number
|
|
ShortDpc db 0 ; Short circut dpc interrupt
|
|
DpcPending db 0 ; Dpc interrupt pending
|
|
|
|
db 0 ; force dword alignment
|
|
;
|
|
; The next three dwords are used to manipulate the APIC counter
|
|
;
|
|
|
|
ApicClockFreqHz dd 0 ; Counter Freq in Hertz
|
|
ApicClockFreqKhz dd 0 ; Counter Freq in Khertz (rounded)
|
|
ProfileCountDown dd 0 ; Current Countdown Interval
|
|
|
|
TSCHz dq 0 ; Time stamp counter hertz
|
|
|
|
|
|
PerfCounterLow dd 0 ; PerProcessor Counter
|
|
PerfCounterHigh dd 0 ;
|
|
; ProfileCountLast dd 0
|
|
|
|
OEMPcr db size OEMPcr dup(?)
|
|
|
|
PcrE ends
|
|
|
|
PrcbE struc
|
|
PrcbPCMPApicID db 0 ; Processor's PCMP ApicID
|
|
db 3 dup (0) ; force dword alignment
|
|
PrcbE ends
|
|
|
|
|
|
MsrTSC equ 10h
|
|
|
|
;++
|
|
;
|
|
; STALL_WHILE_APIC_BUSY
|
|
;
|
|
; Wait for the APIC DELIVERY_PENDING bit to be clear
|
|
;
|
|
;--
|
|
|
|
STALL_WHILE_APIC_BUSY macro
|
|
local a, b
|
|
if 0
|
|
|
|
push eax
|
|
mov eax, 5000h
|
|
|
|
a: test dword ptr APIC[LU_INT_CMD_LOW],DELIVERY_PENDING
|
|
jz short b
|
|
|
|
dec eax
|
|
jnz short a
|
|
|
|
int 3
|
|
jmp short a
|
|
|
|
b: pop eax
|
|
|
|
else
|
|
|
|
a: test dword ptr APIC[LU_INT_CMD_LOW],DELIVERY_PENDING
|
|
jnz short a
|
|
|
|
endif
|
|
endm
|
|
|
|
;++
|
|
;
|
|
; APICFIX
|
|
;
|
|
; Macro Description:
|
|
;
|
|
; For internal testing use
|
|
;
|
|
; Arguments:
|
|
;
|
|
; None
|
|
;
|
|
;--
|
|
|
|
APICFIX macro reg1
|
|
; inc dword ptr PCR[PcKernel] ; Count # of times patched
|
|
endm
|
|
|
|
;++
|
|
;
|
|
; CHECKTPR
|
|
;
|
|
; Macro Description:
|
|
;
|
|
; For internal testing use
|
|
;
|
|
; Arguments:
|
|
;
|
|
; None
|
|
;
|
|
;--
|
|
|
|
CHECKTPR macro reg1, reg2
|
|
if DBG
|
|
cmp reg1, reg2
|
|
je short @f
|
|
int 3
|
|
@@:
|
|
endif
|
|
endm
|
|
|
|
;++
|
|
;
|
|
; IODELAY
|
|
;
|
|
; Macro Description:
|
|
;
|
|
; This macro delays the CPU just a little so the PIC has time to settle
|
|
; between IO port accesses. Current mechanism is to read an APIC local
|
|
; unit register (eax is saved). Note that PUSHF/POPF is worth 10 clocks.
|
|
;
|
|
; Arguments:
|
|
;
|
|
; None
|
|
;
|
|
;--
|
|
|
|
IODELAY macro
|
|
pushf
|
|
popf
|
|
jmp $+2
|
|
endm
|
|
|
|
;++
|
|
;
|
|
; SET_8259_MASK
|
|
;
|
|
; Macro Description:
|
|
;
|
|
; This macro sets the 8259 PIC interrupt mask register with the mask
|
|
; passed from eax register. Bits 7:0 are the mask for the master PIC
|
|
; and bits 15:8 are the mask for the slave PIC.
|
|
;
|
|
; Arguments:
|
|
;
|
|
; (eax) = mask for setting 8259 PIC interrupt mask register
|
|
;
|
|
;--
|
|
|
|
SET_8259_MASK macro
|
|
|
|
out PIC1_PORT1, al ; set master 8259 mask
|
|
shr eax, 8 ; shift slave 8259 mask to al
|
|
out PIC2_PORT1, al ; set slave 8259 mask
|
|
endm
|
|
|
|
;*/
|