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475 lines
12 KiB
475 lines
12 KiB
;/*
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;++
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;
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; Copyright (c) 1992 Intel Corporation
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; All rights reserved
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;
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; INTEL CORPORATION PROPRIETARY INFORMATION
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;
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; This software is supplied to Microsoft under the terms
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; of a license agreement with Intel Corporation and may not be
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; copied nor disclosed except in accordance with the terms
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; of that agreement.
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;
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;
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; Module Name:
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;
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; pcmp.inc
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;
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; Abstract:
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;
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; include file for PC+MP system.
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;
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; WARNING: This file is included by both ASM and C files.
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;
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; Author:
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;
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; Ron Mosgrove and Rajesh Shah (Intel) 30-July-1993
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;
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;--
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;
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if 0 ; Begin C only code */
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#pragma pack(1)
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//
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// IMCR (Interrupt Mode Control Register) access definitions
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//
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#define ImcrDisableApic 0x00
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#define ImcrEnableApic 0x01
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#define ImcrRegPortAddr 0x22
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#if defined(NEC_98)
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#define ImcrDataPortAddr 0x700
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#else // defined(NEC_98)
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#define ImcrDataPortAddr 0x23
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#endif // defined(NEC_98)
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#define ImcrPort 0x70
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// Physical location where the Extended BIOS Data Area segment adress is stored
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#define EBDA_SEGMENT_PTR 0x40e
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#define BASE_MEM_PTR 0x413
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//
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// The PC+MP configuration table Possible Entry Types
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//
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#define ENTRY_PROCESSOR 0
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#define ENTRY_BUS 1
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#define ENTRY_IOAPIC 2
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#define ENTRY_INTI 3
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#define ENTRY_LINTI 4
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#define HEADER_SIZE 0x2c
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// Number of default configurations for PC+MP version 1.1
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#define NUM_DEFAULT_CONFIGS 7
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//
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// Processor Entry definitions
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//
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typedef struct _CPUIDENTIFIER {
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ULONG Stepping : 4;
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ULONG Model : 4;
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ULONG Family : 4;
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ULONG Reserved : 20;
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} CPUIDENTIFIER, *PCPUIDENTIFIER;
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//
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// Bits used in the CpuFlags field of the Processor entry
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//
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#define CPU_DISABLED 0x0 // 1 Bit - CPU Disabled
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#define CPU_ENABLED 0x1 // 1 Bit - CPU Enabled
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#define BSP_CPU 0x2 // Bit #2 - CPU is BSP
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//
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// APIC Versions used by PC+MP systems - this is used in the
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// Processor entries and the IoApic Entries
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//
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#define APIC_INTEGRATED 0x10 // 8 Bits-Apic Version Register
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#define APIC_82489DX 0x0 // 8 Bits-Apic Version Register
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typedef struct _PcMpProcessorEntry {
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UCHAR EntryType;
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UCHAR LocalApicId;
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UCHAR LocalApicVersion;
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UCHAR CpuFlags;
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CPUIDENTIFIER CpuIdentification; // CPU Identification
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ULONG FeatureFlags;
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UCHAR Reserved[8];
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} PCMPPROCESSOR , *PPCMPPROCESSOR;
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//
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// Bus Entry definitions
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//
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typedef struct _PcMpBusEntry {
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UCHAR EntryType;
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UCHAR BusId;
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CHAR BusType[6];
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} PCMPBUS, *PPCMPBUS;
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//
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// Io Apic Entry definitions
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//
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// Valid IoApicFlag values
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//
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#define IO_APIC_ENABLED 0x1
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#define IO_APIC_DISABLED 0x0
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//
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// Default value for Io Apic ID.
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//
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#define IOUNIT_APIC_ID 0xE
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typedef struct _PcMpIoApicEntry {
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UCHAR EntryType;
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UCHAR IoApicId;
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UCHAR IoApicVersion;
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UCHAR IoApicFlag;
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PVOID IoApicAddress;
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} PCMPIOAPIC, *PPCMPIOAPIC;
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//
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// Bits that define the Interrupt logically
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//
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typedef struct _PolarityAndLevel {
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USHORT Polarity : 2;
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USHORT Level : 2;
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USHORT Reserved : 12;
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} POLARITYANDLEVEL, *PPOLARITYANDLEVEL;
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typedef struct _PcMpApicIntiEntry {
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UCHAR EntryType;
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UCHAR IntType;
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POLARITYANDLEVEL Signal;
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UCHAR SourceBusId;
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UCHAR SourceBusIrq;
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UCHAR IoApicId;
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UCHAR IoApicInti;
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} PCMPINTI, *PPCMPINTI;
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//
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// Local Apic Interrupt Entry definitions
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//
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typedef struct _PcMpLintiEntry {
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UCHAR EntryType;
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UCHAR IntType;
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POLARITYANDLEVEL Signal;
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UCHAR SourceBusId;
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UCHAR SourceBusIrq;
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UCHAR DestLocalApicId;
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UCHAR DestLocalApicInti;
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} PCMPLINTI, *PPCMPLINTI;
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//
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// The PC+MP table definition
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//
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struct PcMpTable {
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//
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// PC+MP config table HEADER part (HEADER_SIZE bytes long)
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//
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ULONG Signature; // Must contain "P","C","M","P"
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USHORT TableLength; // Length including the header
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UCHAR Revision; // Rev 1.0 == 1
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UCHAR Checksum; // Entire table including checksum byte
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CHAR OemId[8]; // OEM defined
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CHAR OemProductId[12]; // OEM defined
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PVOID OemTablePtr; // OEM specific data
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USHORT OemTableSize; // length in bytes of the OEM table
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USHORT NumOfEntries; // Number of entries in the data portion
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PVOID LocalApicAddress; // Physical address of Local units
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USHORT ExtTableLength; // Extension table size
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UCHAR ExtTableChecksum; // Complete checksum including extension table
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UCHAR Reserved; // Not Used
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};
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//
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// PC+MP Signature used to verify the PC+MP table
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// as valid
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//
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// "P"=50H,"C"=43H,"M"=4dH,"P"=50H
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//
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#define PCMP_SIGNATURE 0x504d4350
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//
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// PC+MP Signature used to identify the floating pointer
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// structure (in extended BIOS data segment) that contains
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// a pointer to the PC+MP table.
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//
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// "_"=5fH, "M"=4dH, "P"=50H, "_"=5fH
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//
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#define MP_PTR_SIGNATURE 0x5f504d5f
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//
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// This is the floating pointer structure
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//
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// For PC+MP version 1.0
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struct PcMpTableLocator {
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ULONG MpPtrSignature; // Must be "_MP_" (0x5f504d5f)
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PUCHAR TablePtr; // ptr to the PC+MP Table
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UCHAR MpTableLength; // Floating pointer structure length
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UCHAR TableRevision; // Rev 1.0 == 1
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UCHAR TableChecksum; // Checksum of PcMpTableLocator
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UCHAR Pad;
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ULONG Reserved;
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};
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struct FloatPtrStruct {
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ULONG MpPtrSignature; // Must be "_MP_" (0x5f504d5f)
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PUCHAR TablePtr; // ptr to the PC+MP Table
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UCHAR MpTableLength; // Floating pointer structure length
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UCHAR TableRevision; // Rev 1.0 == 1
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UCHAR TableChecksum; // Checksum of PcMpTableLocator
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UCHAR MpFeatureInfoByte1; // MP feature info. byte 1
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UCHAR MpFeatureInfoByte2; // MP feature info. byte 2
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UCHAR Pad;
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USHORT Reserved;
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};
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//
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// Extension table definitions
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//
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#define EXTTYPE_BUS_ADDRESS_MAP 128
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#define EXTTYPE_BUS_HIERARCHY 129
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#define EXTTYPE_BUS_COMPATIBLE_MAP 130
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#define EXTTYPE_PERSISTENT_STORE 131
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typedef struct {
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UCHAR Type;
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UCHAR Length;
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union {
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struct {
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UCHAR BusId;
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UCHAR Type;
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LONGLONG Base;
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LONGLONG Length;
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} AddressMap;
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struct {
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UCHAR BusId;
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UCHAR SubtractiveDecode:1;
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UCHAR ParentBusId;
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} BusHierarchy;
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struct {
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LONGLONG Address;
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LONGLONG Length;
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} PersistentStore;
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struct {
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UCHAR BusId;
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UCHAR Modifier:1;
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UCHAR Reserved:7;
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ULONG List;
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} CompatibleMap;
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} u;
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} MPS_EXTENTRY, *PMPS_EXTENTRY;
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#define MPS_ADDRESS_MAP_IO 0
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#define MPS_ADDRESS_MAP_MEMORY 1
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#define MPS_ADDRESS_MAP_PREFETCH_MEMORY 2
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#define MPS_ADDRESS_MAP_UNDEFINED 9
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//
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// The System configuration table as used by a PC_MP system
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//
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//
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// The offset is relative to the BIOS starting at f0000H
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//
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#define PTR_OFFSET 0x0000e6f5
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#define BIOS_BASE 0x000f0000
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#define PCMP_IMPLEMENTED 0x01 // In MpFeatureInfoByte1
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#define PCMP_CONFIG_MASK 0x0e // In MpFeatureInfoByte1
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#define IMCR_MASK 0x80 // In MpFeatureInfoByte2
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#define MULT_CLOCKS_MASK 0x40 // In MpFeatureInfoByte2
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struct SystemConfigTable {
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UCHAR Reserved[PTR_OFFSET];
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USHORT NumOfBytes; // Table can be variable length.
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UCHAR ModelType; // AT=0xfc, unknown board=0xff
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UCHAR SubModelType;
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UCHAR BIOSRevision; // First release = 0x0
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UCHAR FeatureInfoByte[3]; // Standard AT features
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UCHAR MpFeatureInfoByte1; // MP feature info. byte 1
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UCHAR MpFeatureInfoByte2; // MP feature info. byte 2
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} ;
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#pragma pack()
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NTSTATUS
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HalpPci2MpsBusNumber(
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IN UCHAR PciBusNumber,
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OUT UCHAR *MpsBusNumber
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);
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PBUS_HANDLER
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HalpFindIdeBus(
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IN ULONG Vector
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);
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BOOLEAN
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HalpInterruptsDescribedByMpsTable(
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IN UCHAR MpsBusNumber
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);
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NTSTATUS
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HalpMpsGetParentBus(
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IN UCHAR MpsBus,
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OUT UCHAR *ParentMpsBus
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);
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BOOLEAN
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HalpMpsBusIsRootBus(
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IN UCHAR MpsBus
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);
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VOID
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HalpMPSPCIChildren (
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VOID
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);
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/*
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endif
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;
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; IMCR (Interrupt Mode Control Register) access definitions
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;
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ImcrDisableApic equ 00H
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ImcrEnableApic equ 01H
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ImcrRegPortAddr equ 22H
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ifdef NEC_98
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ImcrDataPortAddr equ 700H
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else ; NEC_98
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ImcrDataPortAddr equ 23H
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endif ; NEC_98
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ImcrPort equ 70H
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;
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; MP Configuration Table - Built by an MP BIOS for OS Support
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;
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; PC+MP Signature used to identify the floating pointer
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; structure (in extended BIOS data segment) that contains
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; a pointer to the PC+MP table.
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;
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; "_"=5fH, "M"=4dH, "P"=50H, "_"=5fH
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;
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MP_PTR_SIGNATURE equ 5f504d5fH
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;
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; PC+MP Signature used to verify the PC+MP table
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; as valid
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;
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; "P"=50H,"C"=43H,"M"=4dH,"P"=50H
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;
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PCMP_SIGNATURE equ 504d4350H
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;
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; The PC+MP configuration table Possible Entry Types
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;
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ENTRY_PROCESSOR equ 0H
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ENTRY_BUS equ 1H
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ENTRY_IOAPIC equ 2H
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ENTRY_INTI equ 3H
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ENTRY_LINTI equ 4H
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;
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; Bits used in the CpuFlags field of the Processor entry
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;
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CPU_ENABLED equ 01H
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CPU_DISABLED equ 00H
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BSP_CPU equ 02H
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;
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; APIC Versions used by PC+MP systems - this is used in the
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; Processor entries and the IoApic Entries
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;
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APIC_INTEGRATED equ 10H
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APIC_82489DX equ 00H
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;
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; Macros used in table definitions
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;
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HEADER_SIZE equ 2CH
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; Number of default configurations for PC+MP version 1.1
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NUM_DEFAULT_CONFIGS equ 7
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;
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; Io Apic Entry definitions
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;
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IO_APIC_ENABLED equ 01H
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IO_APIC_DISABLED equ 00H
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;
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; Default value for Io Apic ID.
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;
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IOUNIT_APIC_ID equ 0EH ; ID of the IO Unit
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PcMpTable struc
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; HEADER portion of the PC+MP config table
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;
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Signature db 4 dup (0) ; Must be "P","C","M","P"
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TableLength dw 0 ; Length in bytes of table
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Revision db 0 ; Table revision #
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Checksum db 0 ; Table checksum
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OemId db 8 dup (0) ; OemId string
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OemProductId db 12 dup (0) ; Oem product id
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OemTablePtr dd 0 ; Ptr to OEM table
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OemTableSize dw 0 ; Size of OEM table
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NumOfEntries dw 0 ; # of entries in table
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LocalApicAddress dd 0 ; Physical address of Local units
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ExtTableLength dw 0 ; Extension table size
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ExtTableChecksum db 0 ; Complete checksum including extension table
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Reserved db 0 ; Not Used
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PcMpTable ends
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;
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; Bios Constants. The offset is relative to the BIOS starting at
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; f0000H.
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;
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PTR_OFFSET equ 0e6f5H
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BIOS_BASE equ 0f0000H
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PCMP_IMPLEMENTED equ 01H
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PCMP_CONFIG_MASK equ 0eH
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IMCR_MASK equ 80H
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MULT_CLOCKS_MASK equ 40H
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PcMpTableLocator struc
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MpPtrSignature dd 0 ; Must be "_MP_" (0x5f504d5f)
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TablePtr dd 0
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MpTableLength db 0
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TableRevision db 0
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TableChecksum db 0
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Pad db 0
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Reserved dd 0
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PcMpTableLocator ends
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SystemConfigTable struc
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db PTR_OFFSET dup (0) ;Skip to 0e6f5
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NumOfBytes db 2 ; Table Length
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ModelType db 0 ; AT=0fc, unknown=0ff
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SubModelType db 0
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BIOSRevision db 0 ; 00=first release
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FeatureInfoByte db 3 dup (0) ; AT features
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MpFeatureInfoByte1 db 0 ; MP feature info. byte 1
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MpFeatureInfoByte2 db 0 ; MP feature info. byte 2
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SystemConfigTable ends
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; */
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