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354 lines
7.2 KiB
354 lines
7.2 KiB
/*++
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Copyright (c) 1989 Microsoft Corporation
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Module Name:
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cyrix.c
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Abstract:
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Detects and initializes Cryix processors
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Author:
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Ken Reneris (kenr) 24-Feb-1994
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Environment:
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Kernel mode only.
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Revision History:
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--*/
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#include "ki.h"
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#define Cx486_SLC 0x0
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#define Cx486_DLC 0x1
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#define Cx486_SLC2 0x2
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#define Cx486_DLC2 0x3
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#define Cx486_SRx 0x4 // Retail Upgrade Cx486SLC
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#define Cx486_DRx 0x5 // Retail Upgrade Cx486DLC
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#define Cx486_SRx2 0x6 // Retail Upgrade 2x Cx486SLC
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#define Cx486_DRx2 0x7 // Retail Upgrade 2x Cx486DLC
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#define Cx486DX 0x1a
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#define Cx486DX2 0x1b
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#define M1 0x30
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#define CCR0 0xC0
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#define CCR1 0xC1
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#define CCR2 0xC2
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#define CCR3 0xC3
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#define DIR0 0xFE
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#define DIR1 0xFF
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// SRx & DRx flags
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#define CCR0_NC0 0x01 // No cache 64k @ 1M boundaries
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#define CCR0_NC1 0x02 // No cache 640k - 1M
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#define CCR0_A20M 0x04 // Enables A20M#
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#define CCR0_KEN 0x08 // Enables KEN#
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#define CCR0_FLUSH 0x10 // Enables FLUSH#
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// DX flags
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#define CCR1_NO_LOCK 0x10 // Ignore lock prefixes
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ULONG
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Ke386CyrixId (
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VOID
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);
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static
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UCHAR
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ReadCyrixRegister (
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IN UCHAR Register
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);
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static
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VOID
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WriteCyrixRegister (
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IN UCHAR Register,
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IN UCHAR Value
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);
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VOID
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Ke386ConfigureCyrixProcessor (
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VOID
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);
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#ifdef ALLOC_PRAGMA
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#pragma alloc_text(PAGE,Ke386CyrixId)
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#pragma alloc_text(PAGELK,Ke386ConfigureCyrixProcessor)
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#endif
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extern CHAR CmpCyrixID[];
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ULONG
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Ke386CyrixId (
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VOID
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)
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/*++
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Routine Description:
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Detects and returns the Cyrix ID of the processor.
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This function only detects Cyrix processors which have internal
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cache support.
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Arguments:
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Configure - If TRUE, causes this function to alter
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the Cyrix CCR registers for the optimal NT
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performance.
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If FALSE, the processors configuration is
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not altered.
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Return Value:
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Cyrix ID of the processor
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0 if not a Cyrix processor
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--*/
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{
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ULONG CyrixID;
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UCHAR r3, c;
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UCHAR flags;
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PKPRCB Prcb;
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CyrixID = 0;
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Prcb = KeGetCurrentPrcb();
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if (Prcb->CpuID && strcmp ((PCHAR)Prcb->VendorString, CmpCyrixID)) {
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//
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// Not a Cyrix processor
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//
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return 0;
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}
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//
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// Test Div instruction to see if the flags
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// do not get altered
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//
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_asm {
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xor eax, eax
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sahf ; flags = ah
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lahf ; ah = flags
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mov flags, ah ; save flags
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mov eax, 5
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mov ecx, 2
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div cl ; 5 / 2 = ?
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lahf
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sub flags, ah ; flags = orig_flags - new_flags
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}
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if (flags == 0) {
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//
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// See if the Cyrix CCR3 register bit 0x80 can be editted.
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//
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r3 = ReadCyrixRegister(CCR3); // Read CCR3
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c = r3 ^ 0x80; // flip bit 80
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WriteCyrixRegister(CCR3, c); // Write CCR3
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ReadCyrixRegister(CCR0); // select new register
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c = ReadCyrixRegister(CCR3); // Read new CCR3 value
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if (ReadCyrixRegister(CCR3) != r3) {
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//
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// Read the Cyrix ID type register
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//
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CyrixID = ReadCyrixRegister(DIR0) + 1;
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}
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WriteCyrixRegister(CCR3, r3); // restore original CCR3 value
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}
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if (CyrixID > 0x7f) {
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// invalid setting
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CyrixID = 0;
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}
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return CyrixID;
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}
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static
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UCHAR
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ReadCyrixRegister (
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IN UCHAR Register
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)
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/*++
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Routine Description:
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Reads an internal Cyrix ID register. Note the internal register
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space is accessed via I/O addresses which are hooked internally
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to the processor.
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The caller is responsible for only calling this function on
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a Cyrix processor.
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Arguments:
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Register - Which Cyrix register to read
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Return Value:
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The registers value
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--*/
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{
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UCHAR Value;
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_asm {
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mov al, Register
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cli
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out 22h, al
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in al, 23h
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sti
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mov Value, al
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}
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return Value;
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}
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static
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VOID
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WriteCyrixRegister (
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IN UCHAR Register,
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IN UCHAR Value
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)
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/*++
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Routine Description:
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Write an internal Cyrix ID register. Note the internal register
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space is accessed via I/O addresses which are hooked internally
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to the processor.
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The caller is responsible for only calling this function on
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a Cyrix processor.
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Arguments:
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Register - Which Cyrix register to written
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Value - Value to write into the register
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Return Value:
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The register's value
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--*/
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{
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_asm {
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mov al, Register
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mov cl, Value
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cli
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out 22h, al
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mov al, cl
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out 23h, al
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sti
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}
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}
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VOID
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Ke386ConfigureCyrixProcessor (
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VOID
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)
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{
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UCHAR r0, r1;
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ULONG id, rev;
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PAGED_CODE();
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id = Ke386CyrixId();
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if (id) {
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ASSERT(ExPageLockHandle);
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MmLockPagableSectionByHandle(ExPageLockHandle);
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id = id - 1;
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rev = ReadCyrixRegister(DIR1);
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if ((id >= 0x20 && id <= 0x27) ||
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((id & 0xF0) == M1 && rev < 0x17)) {
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//
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// These steppings have a write-back cache problem.
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// On these chips the L1 w/b cache can be disabled by
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// setting only the NW bit.
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//
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_asm {
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cli
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mov eax, cr0
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or eax, CR0_NW
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mov cr0, eax
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sti
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}
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}
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switch (id) {
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case Cx486_SRx:
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case Cx486_DRx:
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case Cx486_SRx2:
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case Cx486_DRx2:
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//
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// These processors have an internal cache feature
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// let's turn it on.
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//
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r0 = ReadCyrixRegister(CCR0);
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r0 |= CCR0_NC1 | CCR0_FLUSH;
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r0 &= ~CCR0_NC0;
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WriteCyrixRegister(CCR0, r0);
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// Clear Non-Cacheable Region 1
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WriteCyrixRegister(0xC4, 0);
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WriteCyrixRegister(0xC5, 0);
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WriteCyrixRegister(0xC6, 0);
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break;
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case Cx486DX:
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case Cx486DX2:
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//
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// Set NO_LOCK flag on these processors according to
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// the number of booted processors
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//
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r1 = ReadCyrixRegister(CCR1);
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r1 |= CCR1_NO_LOCK;
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if (KeNumberProcessors > 1) {
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r1 &= ~CCR1_NO_LOCK;
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}
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WriteCyrixRegister(CCR1, r1);
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break;
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}
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MmUnlockPagableImageSection (ExPageLockHandle);
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}
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}
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