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116 lines
4.4 KiB
116 lines
4.4 KiB
/*--------------------------------------------------------------------------
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*
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* Copyright (C) Cyclades Corporation, 1999-2001.
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* All rights reserved.
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*
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* Cyclom-Y Bus/Port Driver
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*
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* This file: cyyhw.h
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*
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* Description: This module contains the common hardware declarations
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* for the parent driver (cyclom-y) and child driver
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* (cyyport).
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*
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* Notes: This code supports Windows 2000 and x86 processor.
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*
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* Complies with Cyclades SW Coding Standard rev 1.3.
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*
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*--------------------------------------------------------------------------
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*/
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/*-------------------------------------------------------------------------
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*
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* Change History
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*
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*--------------------------------------------------------------------------
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*
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*
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*--------------------------------------------------------------------------
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*/
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#ifndef CYYHW_H
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#define CYYHW_H
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#define MAX_DEVICE_ID_LEN 200 // This definition was copied from NTDDK\inc\cfgmgr32.h
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// Always check if this value was changed.
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// This is the maximum length for the Hardware ID.
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#define CYYPORT_PNP_ID_WSTR L"Cyclom-Y\\Port"
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#define CYYPORT_PNP_ID_STR "Cyclom-Y\\Port"
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#define CYYPORT_DEV_ID_STR "Cyclom-Y\\Port"
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#define CYY_NUMBER_OF_RESOURCES 3 // Memory, PLX Memory, Interrupt
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// Cyclom-Y hardware
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#define CYY_RUNTIME_LENGTH 0x00000080
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#define CYY_MAX_CHIPS 8
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#define CYY_CHANNELS_PER_CHIP 4
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#define CYY_MAX_PORTS (CYY_CHANNELS_PER_CHIP*CYY_MAX_CHIPS)
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// Custom register offsets
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#define CYY_CLEAR_INTR 0x1800 //Isa; for PCI, multiply by 2
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#define CYY_RESET_16 0x1400 //Isa; for PCI, multiply by 2
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#define CYY_PCI_TYPE 0x3400 //PCI (no need to multiply by 2)
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// Values in CYY_PCI_TYPE register
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#define CYY_PLX9050 (0x0b)
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#define CYY_PLX9060 (0x0c)
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#define CYY_PLX9080 (0x0d)
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// Runtime registers (or Local Configuration registers)
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#define PLX9050_INT_OFFSET (0x4c)
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#define PLX9060_INT_OFFSET (0x68)
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#define PLX9050_INT_ENABLE (0x00000043UL)
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#define PLX9060_INT_ENABLE (0x00000900UL)
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// Write to Custom registers
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#define CYY_RESET_BOARD(BaseBoardAddress,IsPci) \
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do \
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{ \
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WRITE_REGISTER_UCHAR( \
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(BaseBoardAddress)+(CYY_RESET_16 << IsPci), \
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0x00 \
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); \
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} while (0);
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#define CYY_CLEAR_INTERRUPT(BaseBoardAddress,IsPci) \
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do \
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{ \
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WRITE_REGISTER_UCHAR( \
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(BaseBoardAddress)+(CYY_CLEAR_INTR << IsPci), \
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0x00 \
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); \
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} while (0);
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#define CYY_READ_PCI_TYPE(BaseBoardAddress) \
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(READ_REGISTER_UCHAR((BaseBoardAddress)+CYY_PCI_TYPE))
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#define PLX9050_READ_INTERRUPT_CONTROL(BaseBoardAddress) \
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(READ_REGISTER_ULONG((PULONG)((BaseBoardAddress)+PLX9050_INT_OFFSET)))
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#define PLX9050_WRITE_INTERRUPT_CONTROL(BaseBoardAddress,Value) \
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do { \
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WRITE_REGISTER_ULONG( \
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(PULONG)((BaseBoardAddress)+PLX9050_INT_OFFSET), \
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Value \
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); \
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} while (0);
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#define PLX9060_READ_INTERRUPT_CONTROL(BaseBoardAddress) \
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(READ_REGISTER_ULONG((PULONG)((BaseBoardAddress)+PLX9060_INT_OFFSET)))
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#define PLX9060_WRITE_INTERRUPT_CONTROL(BaseBoardAddress,Value) \
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do { \
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WRITE_REGISTER_ULONG( \
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(PULONG)((BaseBoardAddress)+PLX9060_INT_OFFSET), \
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Value \
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); \
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} while (0);
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#endif // ndef CYCOMMON_H
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