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289 lines
11 KiB
289 lines
11 KiB
/*----------------------------------------------------------------------*
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* zfwint.h: Cyclom-Z asynchronous interface definition. *
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* *
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* rev 2.0 12/13/95 Marcio Saito Cyclom-Z interface definition. *
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* rev 2.1 03/13/96 Marcio Saito minor changes. *
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* rev 2.2 05/29/96 Marcio Saito parity/frame error interrupts. *
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* Acknolowdge interrupt mode. *
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* Break on/off. Data structures *
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* converted to ulong to avoid *
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* alignment problems. *
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* rev 2.3 07/12/96 Marcio Saito HW flow control changes. Flush *
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* buffer command added. Loopback *
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* operation. *
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* rev 2.4 07/16/96 Marcio Saito Diag counters added to CH_CTRL. *
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* rev 2.5 03/21/97 Marcio Saito Added INTBACK2 *
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* rez 3.0 06/04/97 Ivan Passos Added OVR_ERROR and RXOVF *
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*----------------------------------------------------------------------*/
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/*
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* This file contains the definitions for interfacing with the
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* Cyclom-Z ZFIRM Firmware.
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*/
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/* General Constant definitions */
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#define MAX_CHAN 64 /* max number of channels per board */
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#define MAX_SEX 4
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#define ZO_NPORTS (MAX_CHAN / 8)
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/* firmware id structure (set after boot) */
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#define ID_ADDRESS 0x00000180L /* signature/pointer address */
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#define ZFIRM_ID 0x5557465AL /* ZFIRM/U signature */
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#define ZFIRM_HLT 0x59505B5CL /* Halt signal (due to power supply issue) */
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#define ZFIRM_RST 0x56040674L /* RST signal (due to FW reset) */
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#define ZF_TINACT_DEF 1000 /* default inactivity timeout (1000 ms) */
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struct FIRM_ID {
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uclong signature; /* ZFIRM/U signature */
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uclong zfwctrl_addr; /* pointer to ZFW_CTRL structure */
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};
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/* Op. System id */
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#define C_OS_SVR3 0x00000010 /* generic SVR3 */
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#define C_OS_XENIX 0x00000011 /* SCO UNIX SVR3.2 */
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#define C_OS_SCO 0x00000012 /* SCO UNIX SVR3.2 */
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#define C_OS_SVR4 0x00000020 /* generic SVR4 */
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#define C_OS_UXWARE 0x00000021 /* UnixWare */
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#define C_OS_LINUX 0x00000030 /* generic Linux system */
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#define C_OS_SOLARIS 0x00000040 /* generic Solaris system */
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#define C_OS_BSD 0x00000050 /* generic BSD system */
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#define C_OS_DOS 0x00000070 /* generic DOS system */
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#define C_OS_NT 0x00000080 /* generic NT system */
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#define C_OS_OS2 0x00000090 /* generic OS/2 system */
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#define C_OS_MAC_OS 0x000000a0 /* MAC/OS */
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#define C_OS_AIX 0x000000b0 /* IBM AIX */
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/* channel op_mode */
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#define C_CH_DISABLE 0x00000000 /* channel is disabled */
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#define C_CH_TXENABLE 0x00000001 /* channel Tx enabled */
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#define C_CH_RXENABLE 0x00000002 /* channel Rx enabled */
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#define C_CH_ENABLE 0x00000003 /* channel Tx/Rx enabled */
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#define C_CH_LOOPBACK 0x00000004 /* Loopback mode */
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/* comm_parity - parity */
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#define C_PR_NONE 0x00000000 /* None */
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#define C_PR_ODD 0x00000001 /* Odd */
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#define C_PR_EVEN 0x00000002 /* Even */
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#define C_PR_MARK 0x00000004 /* Mark */
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#define C_PR_SPACE 0x00000008 /* Space */
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#define C_PR_PARITY 0x000000ff
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#define C_PR_DISCARD 0x00000100 /* discard char with frame/par error */
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#define C_PR_IGNORE 0x00000200 /* ignore frame/par error */
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/* comm_data_l - data length and stop bits */
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#define C_DL_CS5 0x00000001
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#define C_DL_CS6 0x00000002
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#define C_DL_CS7 0x00000004
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#define C_DL_CS8 0x00000008
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#define C_DL_CS 0x0000000f
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#define C_DL_1STOP 0x00000010
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#define C_DL_15STOP 0x00000020
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#define C_DL_2STOP 0x00000040
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#define C_DL_STOP 0x000000f0
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/* comm_data_l - data length and stop bits */
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#define C_CF_NOFIFO 0x00000001
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/* interrupt enabling/status */
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#define C_IN_DISABLE 0x00000000 /* zero, disable interrupts */
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#define C_IN_TXBEMPTY 0x00000001 /* tx buffer empty */
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#define C_IN_TXLOWWM 0x00000002 /* tx buffer below LWM */
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#define C_IN_TXFEMPTY 0x00000004 /* tx buffer + FIFO + shift reg. empty */
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#define C_IN_RXHIWM 0x00000010 /* rx buffer above HWM */
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#define C_IN_RXNNDT 0x00000020 /* rx no new data timeout */
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#define C_IN_MDCD 0x00000100 /* modem DCD change */
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#define C_IN_MDSR 0x00000200 /* modem DSR change */
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#define C_IN_MRI 0x00000400 /* modem RI change */
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#define C_IN_MCTS 0x00000800 /* modem CTS change */
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#define C_IN_RXBRK 0x00001000 /* Break received */
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#define C_IN_PR_ERROR 0x00002000 /* parity error */
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#define C_IN_FR_ERROR 0x00004000 /* frame error */
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#define C_IN_OVR_ERROR 0x00008000 /* overrun error */
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#define C_IN_RXOFL 0x00010000 /* RX buffer overflow */
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#define C_IN_IOCTLW 0x00020000 /* I/O control w/ wait */
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#define C_IN_MRTS 0x00040000 /* modem RTS drop */
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#define C_IN_ICHAR 0x00080000 /* special intr. char received */
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/* flow control */
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#define C_FL_OXX 0x00000001 /* output Xon/Xoff flow control */
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#define C_FL_IXX 0x00000002 /* input Xon/Xoff flow control */
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#define C_FL_OIXANY 0x00000004 /* output Xon/Xoff (any xon) */
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#define C_FL_SWFLOW 0x0000000f
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/* flow status */
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#define C_FS_TXIDLE 0x00000000 /* no Tx data in the buffer or UART */
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#define C_FS_SENDING 0x00000001 /* UART is sending data */
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#define C_FS_SWFLOW 0x00000002 /* Tx is stopped by received Xoff */
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/* rs_control/rs_status RS-232 signals */
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#define C_RS_PARAM 0x80000000 /* Indicates presence of parameter in
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IOCTLM command */
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#define C_RS_RTS 0x00000001 /* RTS */
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#define C_RS_DTR 0x00000004 /* DTR */
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#define C_RS_DCD 0x00000100 /* CD */
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#define C_RS_DSR 0x00000200 /* DSR */
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#define C_RS_RI 0x00000400 /* RI */
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#define C_RS_CTS 0x00000800 /* CTS */
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/* commands Host <-> Board */
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#define C_CM_RESET 0x01 /* resets/flushes buffers */
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#define C_CM_IOCTL 0x02 /* re-reads CH_CTRL */
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#define C_CM_IOCTLW 0x03 /* re-reads CH_CTRL, intr when done */
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#define C_CM_IOCTLM 0x04 /* RS-232 outputs change */
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#define C_CM_SENDXOFF 0x10 /* sends Xoff */
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#define C_CM_SENDXON 0x11 /* sends Xon */
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#define C_CM_CLFLOW 0x12 /* Clears flow control (resume) */
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#define C_CM_SENDBRK 0x41 /* sends break */
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#define C_CM_INTBACK 0x42 /* Interrupt back */
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#define C_CM_SET_BREAK 0x43 /* Tx break on */
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#define C_CM_CLR_BREAK 0x44 /* Tx break off */
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#define C_CM_CMD_DONE 0x45 /* Previous command done */
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#define C_CM_INTBACK2 0x46 /* Alternate Interrupt back */
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#define C_CM_TINACT 0x51 /* sets inactivity detection */
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#define C_CM_IRQ_ENBL 0x52 /* enables generation of interrupts */
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#define C_CM_IRQ_DSBL 0x53 /* disables generation of interrupts */
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#define C_CM_ACK_ENBL 0x54 /* enables acknolowdged interrupt mode */
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#define C_CM_ACK_DSBL 0x55 /* disables acknolowdged intr mode */
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#define C_CM_FLUSH_RX 0x56 /* flushes Rx buffer */
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#define C_CM_FLUSH_TX 0x57 /* flushes Tx buffer */
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#define C_CM_Q_ENABLE 0x58 /* enables queue access from the driver */
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#define C_CM_Q_DISABLE 0x59 /* disables queue access from the driver */
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#define C_CM_TXBEMPTY 0x60 /* Tx buffer is empty */
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#define C_CM_TXLOWWM 0x61 /* Tx buffer low water mark */
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#define C_CM_RXHIWM 0x62 /* Rx buffer high water mark */
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#define C_CM_RXNNDT 0x63 /* rx no new data timeout */
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#define C_CM_TXFEMPTY 0x64 /* Tx buffer, FIFO and shift reg. are empty */
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#define C_CM_ICHAR 0x65 /* Special Interrupt Character received */
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#define C_CM_MDCD 0x70 /* modem DCD change */
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#define C_CM_MDSR 0x71 /* modem DSR change */
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#define C_CM_MRI 0x72 /* modem RI change */
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#define C_CM_MCTS 0x73 /* modem CTS change */
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#define C_CM_MRTS 0x74 /* modem RTS drop */
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#define C_CM_RXBRK 0x84 /* Break received */
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#define C_CM_PR_ERROR 0x85 /* Parity error */
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#define C_CM_FR_ERROR 0x86 /* Frame error */
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#define C_CM_OVR_ERROR 0x87 /* Overrun error */
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#define C_CM_RXOFL 0x88 /* RX buffer overflow */
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#define C_CM_CMDERROR 0x90 /* command error */
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#define C_CM_FATAL 0x91 /* fatal error */
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#define C_CM_HW_RESET 0x92 /* reset board */
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/*
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* CH_CTRL - This per port structure contains all parameters
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* that control an specific port. It can be seen as the
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* configuration registers of a "super-serial-controller".
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*/
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struct CH_CTRL {
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uclong op_mode; /* operation mode */
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uclong intr_enable; /* interrupt masking for the UART */
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uclong sw_flow; /* SW flow control */
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uclong flow_status; /* output flow status */
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uclong comm_baud; /* baud rate - numerically specified */
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uclong comm_parity; /* parity */
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uclong comm_data_l; /* data length/stop */
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uclong comm_flags; /* other flags */
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uclong hw_flow; /* HW flow control */
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uclong rs_control; /* RS-232 outputs */
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uclong rs_status; /* RS-232 inputs */
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uclong flow_xon; /* xon char */
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uclong flow_xoff; /* xoff char */
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uclong hw_overflow; /* hw overflow counter */
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uclong sw_overflow; /* sw overflow counter */
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uclong comm_error; /* frame/parity error counter */
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uclong ichar; /* special interrupt char */
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uclong filler[7]; /* filler to align structures */
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};
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/*
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* BUF_CTRL - This per channel structure contains
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* all Tx and Rx buffer control for a given channel.
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*/
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struct BUF_CTRL {
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uclong flag_dma; /* buffers are in Host memory */
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uclong tx_bufaddr; /* address of the tx buffer */
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uclong tx_bufsize; /* tx buffer size */
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uclong tx_threshold; /* tx low water mark */
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uclong tx_get; /* tail index tx buf */
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uclong tx_put; /* head index tx buf */
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uclong rx_bufaddr; /* address of the rx buffer */
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uclong rx_bufsize; /* rx buffer size */
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uclong rx_threshold; /* rx high water mark */
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uclong rx_get; /* tail index rx buf */
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uclong rx_put; /* head index rx buf */
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uclong filler[5]; /* filler to align structures */
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};
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/*
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* BOARD_CTRL - This per board structure contains all global
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* control fields related to the board.
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*/
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struct BOARD_CTRL {
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/* static info provided by the on-board CPU */
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uclong n_channel; /* number of channels */
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uclong fw_version; /* firmware version */
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/* static info provided by the driver */
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uclong op_system; /* op_system id */
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uclong dr_version; /* driver version */
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/* board control area */
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uclong inactivity; /* inactivity control */
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/* host to FW commands */
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uclong hcmd_channel; /* channel number */
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uclong hcmd_param; /* parameter */
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/* FW to Host commands */
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uclong fwcmd_channel; /* channel number */
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uclong fwcmd_param; /* parameter */
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uclong zf_int_queue_addr; /* offset for INT_QUEUE structure */
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/* filler so the structures are aligned */
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uclong filler[6];
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};
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/* Host Interrupt Queue */
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#define QUEUE_SIZE (10*MAX_CHAN)
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struct INT_QUEUE {
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unsigned char intr_code[QUEUE_SIZE];
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unsigned long channel[QUEUE_SIZE];
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unsigned long param[QUEUE_SIZE];
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unsigned long put;
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unsigned long get;
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};
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/*
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* ZFW_CTRL - This is the data structure that includes all other
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* data structures used by the Firmware.
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*/
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struct ZFW_CTRL {
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struct BOARD_CTRL board_ctrl;
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struct CH_CTRL ch_ctrl[MAX_CHAN];
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struct BUF_CTRL buf_ctrl[MAX_CHAN];
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};
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