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184 lines
6.5 KiB
184 lines
6.5 KiB
/*----------------------------------------------------------------------*
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* cyclomz.h: Cyclades-Z hardware-related definitions. *
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* *
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* revision 1.0 03/14/95 Marcio Saito *
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* revision 2.0 01/04/96 Marcio Saito Changes due to HW design *
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* alterations. *
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* revision 2.1 03/15/96 Marcio Saito Changes due to HW design *
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* alterations. *
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* revision 3.0 04/11/97 Ivan Passos Changes to support the *
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* new boards (8Zo and Ze). *
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*----------------------------------------------------------------------*/
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/*
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* The data types defined below are used in all ZFIRM interface
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* data structures. They accomodate differences between HW
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* architectures and compilers.
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*/
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typedef unsigned long uclong; /* 32 bits, unsigned */
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typedef unsigned short ucshort; /* 16 bits, unsigned */
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typedef unsigned char ucchar; /* 8 bits, unsigned */
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/*
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* Memory Window Sizes
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*/
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#define DP_WINDOW_SIZE (0x00080000) /* window size 512 Kb */
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#define ZE_DP_WINDOW_SIZE (0x00100000) /* window size 1 Mb (for the
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Ze V_1 and 8Zo V_2) */
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#define CTRL_WINDOW_SIZE (0x00000080) /* runtime regs 128 bytes */
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/*
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* CUSTOM_REG - Cyclades-8Zo/PCI Custom Registers Set. The driver
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* normally will access only interested on the fpga_id, fpga_version,
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* start_cpu and stop_cpu.
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*/
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struct CUSTOM_REG {
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uclong fpga_id; /* FPGA Identification Register */
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uclong fpga_version; /* FPGA Version Number Register */
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uclong cpu_start; /* CPU start Register (write) */
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uclong cpu_stop; /* CPU stop Register (write) */
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uclong misc_reg; /* Miscelaneous Register */
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uclong idt_mode; /* IDT mode Register */
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uclong uart_irq_status; /* UART IRQ status Register */
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uclong clear_timer0_irq; /* Clear timer interrupt Register */
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uclong clear_timer1_irq; /* Clear timer interrupt Register */
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uclong clear_timer2_irq; /* Clear timer interrupt Register */
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uclong test_register; /* Test Register */
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uclong test_count; /* Test Count Register */
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uclong timer_select; /* Timer select register */
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uclong pr_uart_irq_status; /* Prioritized UART IRQ stat Reg */
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uclong ram_wait_state; /* RAM wait-state Register */
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uclong uart_wait_state; /* UART wait-state Register */
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uclong timer_wait_state; /* timer wait-state Register */
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uclong ack_wait_state; /* ACK wait State Register */
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};
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/*
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* CUSTOM_REG_ZE - Cyclades-Ze/PCI Custom Registers Set. The driver
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* normally will access only interested on the fpga_id, fpga_version,
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* start_cpu and stop_cpu.
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*/
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struct CUSTOM_REG_ZE {
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uclong fpga_id; /* FPGA Identification Register */
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uclong fpga_version; /* FPGA Version Number Register */
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uclong cpu_start; /* CPU start Register (write) */
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uclong cpu_stop; /* CPU stop Register (write) */
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uclong cpu_ctrl;
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uclong zbus_wait; /* Z-Bus wait states */
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uclong timer_div; /* Timer divider */
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uclong timer_irq_ack; /* Write anything to ack/clear Timer
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Interrupt Register */
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};
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/*
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* RUNTIME_9060 - PLX PCI9060ES local configuration and shared runtime
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* registers. This structure can be used to access the 9060 registers
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* (memory mapped).
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*/
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struct RUNTIME_9060 {
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uclong loc_addr_range; /* 00h - Local Address Range */
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uclong loc_addr_base; /* 04h - Local Address Base */
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uclong loc_arbitr; /* 08h - Local Arbitration */
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uclong endian_descr; /* 0Ch - Big/Little Endian Descriptor */
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uclong loc_rom_range; /* 10h - Local ROM Range */
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uclong loc_rom_base; /* 14h - Local ROM Base */
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uclong loc_bus_descr; /* 18h - Local Bus descriptor */
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uclong loc_range_mst; /* 1Ch - Local Range for Master to PCI */
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uclong loc_base_mst; /* 20h - Local Base for Master PCI */
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uclong loc_range_io; /* 24h - Local Range for Master IO */
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uclong pci_base_mst; /* 28h - PCI Base for Master PCI */
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uclong pci_conf_io; /* 2Ch - PCI configuration for Master IO */
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uclong filler1; /* 30h */
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uclong filler2; /* 34h */
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uclong filler3; /* 38h */
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uclong filler4; /* 3Ch */
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uclong mail_box_0; /* 40h - Mail Box 0 */
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uclong mail_box_1; /* 44h - Mail Box 1 */
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uclong mail_box_2; /* 48h - Mail Box 2 */
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uclong mail_box_3; /* 4Ch - Mail Box 3 */
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uclong filler5; /* 50h */
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uclong filler6; /* 54h */
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uclong filler7; /* 58h */
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uclong filler8; /* 5Ch */
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uclong pci_doorbell; /* 60h - PCI to Local Doorbell */
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uclong loc_doorbell; /* 64h - Local to PCI Doorbell */
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uclong intr_ctrl_stat; /* 68h - Interrupt Control/Status */
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uclong init_ctrl; /* 6Ch - EEPROM control, Init Control, etc */
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};
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/* Values for the Local Base Address re-map register */
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#define WIN_RAM 0x00000001L /* set the sliding window to RAM */
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#define WIN_CREG 0x14000001L /* set the window to custom Registers */
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/* Values timer select registers */
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#define TIMER_BY_1M 0x00 /* clock divided by 1M */
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#define TIMER_BY_256K 0x01 /* clock divided by 256k */
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#define TIMER_BY_128K 0x02 /* clock divided by 128k */
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#define TIMER_BY_32K 0x03 /* clock divided by 32k */
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/*
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* Starting from here, the compilation is conditional to the definition
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* of FIRMWARE
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*/
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#ifdef FIRMWARE
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struct RUNTIME_9060_FW {
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uclong mail_box_0; /* 40h - Mail Box 0 */
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uclong mail_box_1; /* 44h - Mail Box 1 */
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uclong mail_box_2; /* 48h - Mail Box 2 */
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uclong mail_box_3; /* 4Ch - Mail Box 3 */
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uclong filler5; /* 50h */
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uclong filler6; /* 54h */
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uclong filler7; /* 58h */
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uclong filler8; /* 5Ch */
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uclong pci_doorbell; /* 60h - PCI to Local Doorbell */
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uclong loc_doorbell; /* 64h - Local to PCI Doorbell */
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uclong intr_ctrl_stat; /* 68h - Interrupt Control/Status */
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uclong init_ctrl; /* 6Ch - EEPROM control, Init Control, etc */
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};
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/* Hardware related constants */
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#define ZF_UART_PTR (0xb0000000UL)
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#define ZF_UART_SPACE 0x00000080UL
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#define ZF_UART_CLOCK 7372800
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#define ZO_V1_FPGA_ID 0x95
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#define ZO_V2_FPGA_ID 0x84
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#define ZE_V1_FPGA_ID 0x89
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#define ZF_TIMER_PTR (0xb2000000UL)
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#define ZF_9060_PTR (0xb6000000UL)
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#define ZF_9060_ZE_PTR (0xb8000000UL)
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#define ZF_CUSTOM_PTR (0xb4000000UL)
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#define ZF_NO_CACHE (0xa0000000UL)
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#define ZF_CACHE (0x80000000UL)
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#define ZF_I_TIMER (EXT_INT0)
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#define ZF_I_SERIAL (EXT_INT2)
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#define ZF_I_HOST (EXT_INT3)
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#define ZF_I_ALL (EXT_INT0|EXT_INT2|EXT_INT3)
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#define ZF_I_TOTAL (EXT_INT0|EXT_INT1|EXT_INT2|EXT_INT3|EXT_INT4|EXT_INT5)
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#define ZF_IRQ03 0xfffffffeUL
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#define ZF_IRQ05 0xfffffffdUL
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#define ZF_IRQ09 0xfffffffbUL
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#define ZF_IRQ10 0xfffffff7UL
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#define ZF_IRQ11 0xffffffefUL
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#define ZF_IRQ12 0xffffffdfUL
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#define ZF_IRQ15 0xffffffbfUL
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#endif /* FIRMWARE */
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