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330 lines
10 KiB
330 lines
10 KiB
/*++
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Copyright (c) 1990, 1991, 1992, 1993 - 1997 Microsoft Corporation
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Module Name :
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cyserial.h
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Abstract:
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Type definitions and data for the serial port driver
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Modified to contain only 8250 bit definitions. - Fanny
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Author:
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--*/
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//
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// Bitmask definitions for accessing the 8250 device registers.
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//
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//
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// These bits define the number of data bits trasmitted in
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// the Serial Data Unit (SDU - Start,data, parity, and stop bits)
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//
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#define SERIAL_DATA_LENGTH_5 0x00
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#define SERIAL_DATA_LENGTH_6 0x01
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#define SERIAL_DATA_LENGTH_7 0x02
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#define SERIAL_DATA_LENGTH_8 0x03
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//
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// These masks define the interrupts that can be enabled or disabled.
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//
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//
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// This interrupt is used to notify that there is new incomming
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// data available. The SERIAL_RDA interrupt is enabled by this bit.
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//
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#define SERIAL_IER_RDA 0x01
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//
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// This interrupt is used to notify that there is space available
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// in the transmitter for another character. The SERIAL_THR
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// interrupt is enabled by this bit.
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//
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#define SERIAL_IER_THR 0x02
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//
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// This interrupt is used to notify that some sort of error occured
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// with the incomming data. The SERIAL_RLS interrupt is enabled by
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// this bit.
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#define SERIAL_IER_RLS 0x04
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//
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// This interrupt is used to notify that some sort of change has
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// taken place in the modem control line. The SERIAL_MS interrupt is
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// enabled by this bit.
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//
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#define SERIAL_IER_MS 0x08
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//
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// These masks define the values of the interrupt identification
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// register. The low bit must be clear in the interrupt identification
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// register for any of these interrupts to be valid. The interrupts
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// are defined in priority order, with the highest value being most
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// important. See above for a description of what each interrupt
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// implies.
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//
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#define SERIAL_IIR_RLS 0x06
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#define SERIAL_IIR_RDA 0x04
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#define SERIAL_IIR_CTI 0x0c
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#define SERIAL_IIR_THR 0x02
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#define SERIAL_IIR_MS 0x00
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//
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// This bit mask get the value of the high two bits of the
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// interrupt id register. If this is a 16550 class chip
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// these bits will be a one if the fifo's are enbled, otherwise
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// they will always be zero.
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//
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#define SERIAL_IIR_FIFOS_ENABLED 0xc0
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//
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// If the low bit is logic one in the interrupt identification register
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// this implies that *NO* interrupts are pending on the device.
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//
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#define SERIAL_IIR_NO_INTERRUPT_PENDING 0x01
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//
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// These masks define access to the fifo control register.
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//
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//
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// Enabling this bit in the fifo control register will turn
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// on the fifos. If the fifos are enabled then the high two
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// bits of the interrupt id register will be set to one. Note
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// that this only occurs on a 16550 class chip. If the high
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// two bits in the interrupt id register are not one then
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// we know we have a lower model chip.
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//
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//
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#define SERIAL_FCR_ENABLE ((UCHAR)0x01)
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#define SERIAL_FCR_RCVR_RESET ((UCHAR)0x02)
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#define SERIAL_FCR_TXMT_RESET ((UCHAR)0x04)
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//
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// This set of values define the high water marks (when the
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// interrupts trip) for the receive fifo.
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//
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#define SERIAL_1_BYTE_HIGH_WATER ((UCHAR)0x00)
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#define SERIAL_4_BYTE_HIGH_WATER ((UCHAR)0x40)
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#define SERIAL_8_BYTE_HIGH_WATER ((UCHAR)0x80)
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#define SERIAL_14_BYTE_HIGH_WATER ((UCHAR)0xc0)
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//
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// These masks define access to the line control register.
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//
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//
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// This defines the bit used to control the definition of the "first"
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// two registers for the 8250. These registers are the input/output
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// register and the interrupt enable register. When the DLAB bit is
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// enabled these registers become the least significant and most
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// significant bytes of the divisor value.
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//
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#define SERIAL_LCR_DLAB 0x80
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//
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// This defines the bit used to control whether the device is sending
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// a break. When this bit is set the device is sending a space (logic 0).
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//
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// Most protocols will assume that this is a hangup.
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//
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#define SERIAL_LCR_BREAK 0x40
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//
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// These defines are used to set the line control register.
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//
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#define SERIAL_5_DATA ((UCHAR)0x00)
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#define SERIAL_6_DATA ((UCHAR)0x01)
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#define SERIAL_7_DATA ((UCHAR)0x02)
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#define SERIAL_8_DATA ((UCHAR)0x03)
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#define SERIAL_DATA_MASK ((UCHAR)0x03)
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#define SERIAL_1_STOP ((UCHAR)0x00)
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#define SERIAL_1_5_STOP ((UCHAR)0x04) // Only valid for 5 data bits
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#define SERIAL_2_STOP ((UCHAR)0x04) // Not valid for 5 data bits
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#define SERIAL_STOP_MASK ((UCHAR)0x04)
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#define SERIAL_NONE_PARITY ((UCHAR)0x00)
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#define SERIAL_ODD_PARITY ((UCHAR)0x08)
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#define SERIAL_EVEN_PARITY ((UCHAR)0x18)
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#define SERIAL_MARK_PARITY ((UCHAR)0x28)
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#define SERIAL_SPACE_PARITY ((UCHAR)0x38)
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#define SERIAL_PARITY_MASK ((UCHAR)0x38)
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//
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// These masks define access the modem control register.
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//
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//
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// This bit controls the data terminal ready (DTR) line. When
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// this bit is set the line goes to logic 0 (which is then inverted
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// by normal hardware). This is normally used to indicate that
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// the device is available to be used. Some odd hardware
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// protocols (like the kernel debugger) use this for handshaking
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// purposes.
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//
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#define SERIAL_MCR_DTR 0x01
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//
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// This bit controls the ready to send (RTS) line. When this bit
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// is set the line goes to logic 0 (which is then inverted by the normal
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// hardware). This is used for hardware handshaking. It indicates that
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// the hardware is ready to send data and it is waiting for the
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// receiving end to set clear to send (CTS).
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//
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#define SERIAL_MCR_RTS 0x02
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//
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// This bit is used for general purpose output.
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//
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#define SERIAL_MCR_OUT1 0x04
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//
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// This bit is used for general purpose output.
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//
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#define SERIAL_MCR_OUT2 0x08
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//
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// This bit controls the loopback testing mode of the device. Basically
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// the outputs are connected to the inputs (and vice versa).
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//
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#define SERIAL_MCR_LOOP 0x10
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//
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// These masks define access to the line status register. The line
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// status register contains information about the status of data
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// transfer. The first five bits deal with receive data and the
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// last two bits deal with transmission. An interrupt is generated
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// whenever bits 1 through 4 in this register are set.
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//
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//
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// This bit is the data ready indicator. It is set to indicate that
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// a complete character has been received. This bit is cleared whenever
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// the receive buffer register has been read.
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//
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#define SERIAL_LSR_DR 0x01
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//
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// This is the overrun indicator. It is set to indicate that the receive
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// buffer register was not read befor a new character was transferred
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// into the buffer. This bit is cleared when this register is read.
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//
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#define SERIAL_LSR_OE 0x02
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//
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// This is the parity error indicator. It is set whenever the hardware
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// detects that the incoming serial data unit does not have the correct
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// parity as defined by the parity select in the line control register.
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// This bit is cleared by reading this register.
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//
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#define SERIAL_LSR_PE 0x04
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//
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// This is the framing error indicator. It is set whenever the hardware
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// detects that the incoming serial data unit does not have a valid
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// stop bit. This bit is cleared by reading this register.
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//
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#define SERIAL_LSR_FE 0x08
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//
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// This is the break interrupt indicator. It is set whenever the data
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// line is held to logic 0 for more than the amount of time it takes
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// to send one serial data unit. This bit is cleared whenever the
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// this register is read.
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//
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#define SERIAL_LSR_BI 0x10
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//
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// This is the transmit holding register empty indicator. It is set
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// to indicate that the hardware is ready to accept another character
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// for transmission. This bit is cleared whenever a character is
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// written to the transmit holding register.
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//
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#define SERIAL_LSR_THRE 0x20
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//
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// This bit is the transmitter empty indicator. It is set whenever the
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// transmit holding buffer is empty and the transmit shift register
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// (a non-software accessable register that is used to actually put
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// the data out on the wire) is empty. Basically this means that all
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// data has been sent. It is cleared whenever the transmit holding or
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// the shift registers contain data.
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//
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#define SERIAL_LSR_TEMT 0x40
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//
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// This bit indicates that there is at least one error in the fifo.
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// The bit will not be turned off until there are no more errors
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// in the fifo.
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//
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#define SERIAL_LSR_FIFOERR 0x80
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//
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// These masks are used to access the modem status register.
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// Whenever one of the first four bits in the modem status
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// register changes state a modem status interrupt is generated.
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//
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//
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// This bit is the delta clear to send. It is used to indicate
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// that the clear to send bit (in this register) has *changed*
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// since this register was last read by the CPU.
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//
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#define SERIAL_MSR_DCTS 0x01
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//
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// This bit is the delta data set ready. It is used to indicate
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// that the data set ready bit (in this register) has *changed*
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// since this register was last read by the CPU.
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//
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#define SERIAL_MSR_DDSR 0x02
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//
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// This is the trailing edge ring indicator. It is used to indicate
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// that the ring indicator input has changed from a low to high state.
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//
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#define SERIAL_MSR_TERI 0x04
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//
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// This bit is the delta data carrier detect. It is used to indicate
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// that the data carrier bit (in this register) has *changed*
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// since this register was last read by the CPU.
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//
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#define SERIAL_MSR_DDCD 0x08
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//
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// This bit contains the (complemented) state of the clear to send
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// (CTS) line.
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//
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#define SERIAL_MSR_CTS 0x10
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//
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// This bit contains the (complemented) state of the data set ready
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// (DSR) line.
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//
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#define SERIAL_MSR_DSR 0x20
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//
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// This bit contains the (complemented) state of the ring indicator
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// (RI) line.
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//
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#define SERIAL_MSR_RI 0x40
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//
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// This bit contains the (complemented) state of the data carrier detect
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// (DCD) line.
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//
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#define SERIAL_MSR_DCD 0x80
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