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788 lines
29 KiB
788 lines
29 KiB
#if PAL_SUPPORT
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//
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// ATIConfig
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//
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#ifndef PALSUPP_INC_
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#define PALSUPP_INC_
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// #define BUG_800x600_8BPP //if this is defined, in 800x600 8bpp the memory allocation is
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// done in rectangles with the width 800 not 832 (the actual cxMemory in this mode)
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// #define ALLOC_RECT_ANYWHERE // if this is defined, then the allocation will be made anywhere in the heap, not starting
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// at a requested location
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// #define DYNAMIC_REZ_AND_COLOUR_CHANGE // palindrome support for on the fly rez and colour depth
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#define ACCESSDEVICEDATA_SUBFUNC_ALLOC (DWORD)0x00000001
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#define ACCESSDEVICEDATA_SUBFUNC_FREE (DWORD)0x00000002
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#define ACCESSDEVICEDATA_SUBFUNC_QUERY (DWORD)0x00000003
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#define ACCESSDEVICECODE_CONNECTOR (DWORD)0x00000001
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#define ACCESSDEVICECODE_OVERLAY (DWORD)0x00000002
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// structure used for the size of off-screen memory alloc
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typedef struct tag_OFFSCEREEN {
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LONG cx; //width
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LONG cy; //height
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} OFFSCREEN;
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//structure for retriving the info about where the allocated off_screen memory is allocated
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typedef struct tag_OVERLAY_LOCATION {
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LONG x; //x coordinate in pixels from the begining of the aperture
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LONG y; //y coordinate in pixels from the begining of the aperture
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ULONG app_offset;//pointer to the begining of the allocated memory in the liniar memory
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} OVERLAY_LOCATION;
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typedef struct tag_RW_REG_STRUCT{
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BYTE reg_block;
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WORD reg_offset;
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DWORD data;
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} RW_REG_STRUCT;
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typedef struct struct_ATIConfig
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{
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BYTE ATISig[10];
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BYTE Filler1[2];
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BYTE DriverName[9];
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BYTE Filler2[3];
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DWORD dwMajorVersion;
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DWORD dwMinorVersion;
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DWORD dwBuildNumber;
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DWORD dwDesktopWidth;
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DWORD dwDesktopHeight;
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DWORD dwEnginePitch;
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DWORD dwRealRamAvail;
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DWORD VGABoundary;
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DWORD dwBpp;
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DWORD dwBoardBpp;
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DWORD dwColorFormat;
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DWORD dwAlphaBitMask;
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DWORD dwConfigBits;
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DWORD dwAsicRevision;
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DWORD dwROMVersion;
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DWORD dwBoardType;
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DWORD dwApertureType;
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DWORD AperturePtr;
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DWORD DisplayOffset;
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DWORD MemRegPtr;
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DWORD dwExtDevice[8];
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DWORD MemReg1Ptr;
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}
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ATIConfig;
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#define ATIConfig_ColorFmt_4 0x0000 //4 bpp
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#define ATIConfig_ColorFmt_4_Packed 0x0001 //4 bpp
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#define ATIConfig_ColorFmt_8 0x0002 //8 bpp
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#define ATIConfig_ColorFmt_RGB332 0x0003 //8 bpp
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#define ATIConfig_ColorFmt_Crystal8 0x0004 //8 bpp
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#define ATIConfig_ColorFmt_RGB555 0x0005 //16 bpp
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#define ATIConfig_ColorFmt_RGB565 0x0006 //16 bpp
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#define ATIConfig_ColorFmt_RGB655 0x0007 //16 bpp
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#define ATIConfig_ColorFmt_RGB664 0x0008 //16 bpp
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#define ATIConfig_ColorFmt_RGB888 0x0009 //24 bpp
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#define ATIConfig_ColorFmt_BGR888 0x000A //24 bpp
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#define ATIConfig_ColorFmt_aRGB8888 0x000B //32 bpp
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#define ATIConfig_ColorFmt_RGBa8888 0x000C //32 bpp
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#define ATIConfig_ColorFmt_aBGR8888 0x000D //32 bpp
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#define ATIConfig_ColorFmt_BGRa8888 0x000E //32 bpp
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#define ATIConfig_ColorFmtBIT_4 0x00000001
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#define ATIConfig_ColorFmtBIT_4_Packed 0x00000002
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#define ATIConfig_ColorFmtBIT_8 0x00000004
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#define ATIConfig_ColorFmtBIT_RGB332 0x00000008
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#define ATIConfig_ColorFmtBIT_Crystal8 0x00000010
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#define ATIConfig_ColorFmtBIT_RGB555 0x00000020
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#define ATIConfig_ColorFmtBIT_RGB565 0x 00000040
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#define ATIConfig_ColorFmtBIT_RGB655 0x00000080
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#define ATIConfig_ColorFmtBIT_RGB664 0x00000100
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#define ATIConfig_ColorFmtBIT_RGB888 0x00000200
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#define ATIConfig_ColorFmtBIT_BGR888 0x00000400
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#define ATIConfig_ColorFmtBIT_aRGB8888 0x00000800
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#define ATIConfig_ColorFmtBIT_RGBa8888 0x00001000
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#define ATIConfig_ColorFmtBIT_aBGR8888 0x00002000
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#define ATIConfig_ColorFmtBIT_BGRa8888 0x00004000
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// these two struct def have been moved into driver.h
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/*
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typedef struct tag_alloc_history{
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ULONG x;
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ULONG y;
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OH* poh;
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} alloc_history;
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typedef struct tagACCESSDEVICEDATA
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{
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DWORD dwSize;
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DWORD dwSubFunc;
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DWORD dwAccessDeviceCode;
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DWORD lpAccessCallbackFuncPtr;
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}ACCESSDEVICEDATA, *pACCESSDEVICEDATA;
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*/
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typedef DWORD FOURCC; /* a four character code */
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typedef struct tagVIDEOCAPTUREDATA{
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DWORD dwSize;
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DWORD dwSubFunc;
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DWORD dwCaptureWidth;
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DWORD dwCaptureHeight;
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FOURCC fccFormat;
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DWORD dwBitMasks[3];
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DWORD dwCaptureMode;
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}VIDEOCAPTUREDATA, FAR *LPVIDEOCAPTUREDATA;
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/* Gone into atint.h
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typedef struct tag_VIDEO_CAPTURE{
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DWORD dwSubFunct; // On , Off or return the capture width
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DWORD dwCaptureWidth; // maximum width of the capture at the current resolution, color depth and refresh rate
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DWORD dwCaptureMode; // Continuous capture or single capture (host mode)
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} VIDEO_CAPTURE;
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*/
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#define VIDEOCAPTUREDATA_SUBFUNC_ENABLE 0x00000000
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#define VIDEOCAPTUREDATA_SUBFUNC_DISABLE 0x00000001
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#define VIDEOCAPTUREDATA_SUBFUNC_QUERY 0x00000002
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#define VIDEOCAPTUREDATA_CAPTURE_HOSTTRIGGED 0x00000000
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#define VIDEOCAPTUREDATA_CAPTURE_CONTINUOUS 0x00000001
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typedef struct
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{
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long ScreenWidth;
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long ScreenHeight;
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long ScreenColorFormat;
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long DesctopWidth;
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long DesctopHeight;
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long SystemColorFormat;
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}ModeInfo;
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#define Control_DisplaymodeIsSupported 0x73A0
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#define Control_DisplaymodeIsEnabled 0x73A1
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#define Control_GetDisplaymode 0x73A3
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#define Control_TimewarpIsSupported 0x7340
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#define Control_TimewarpIsEnabled 0x7341
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#define Control_TimewarpEnable 0x7342
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#define Control_TimewarpDisable 0x7343
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#define Control_DCIIsSupported 0x73E0
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#define Control_DCIIsEnabled 0x73E1
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#define Control_DCIAccessDevice 0x73EC
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#define Control_DCIEnable 0x73e2
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#define Control_DCIDisable 0x73e3
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#define Control_DCIVideoCapture 0x73ee
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#define Control_ConfigIsSupported 0x7300
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#define Control_ConfigIsEnabled 0x7301
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#define Control_GetConfiguration 0x7302
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typedef struct {
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WORD wCard;
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WORD wChipID;
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WORD wError;
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WORD wWriteCount;
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WORD wReadCount;
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BYTE lpWrData[10];
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BYTE lpRdData[10];
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} I2CSTRUCT_NEW, *LPI2CSTRUCT_NEW;
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//
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// VT Scaler and Overlay Registers
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//
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#define OVERLAY_Y_X (0x0000 )//* 4)
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#define OVERLAY_Y_X_END (0x0001 )//* 4)
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#define OVERLAY_VIDEO_KEY_CLR (0x0002 )//* 4)
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#define OVERLAY_VIDEO_KEY_MSK (0x0003 )//* 4)
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#define OVERLAY_GRAPHICS_KEY_CLR (0x0004 )//* 4)
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#define OVERLAY_GRAPHICS_KEY_MSK (0x0005 )//* 4)
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#define OVERLAY_KEY_CNTL (0x0006 )//* 4)
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#define OVERLAY_SCALE_INC (0x0008 )//* 4)
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#define OVERLAY_SCALE_CNTL (0x0009 )//* 4)
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#define SCALER_HEIGHT_WIDTH (0x000A )//* 4)
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#define OVERLAY_TEST (0x000B )//* 4)
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#define SCALER_THRESHOLD (0x000C )//* 4)
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#define CAPTURE_Y_X (0x0010 )//* 4)
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#define CAPTURE_HEIGHT_WIDTH (0x0011 )//* 4)
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#define VIDEO_FORMAT (0x0012 )//* 4)
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#define VIDEO_CONFIG (0x0013 )//* 4)
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#define CAPTURE_CONFIG (0x0014 )//* 4)
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#define TRIG_CNTL (0x0015 )//* 4)
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#define VMC_CONFIG (0x0018 )//* 4)
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#define BUF0_OFFSET (0x0020 )//* 4)
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#define BUF0_PITCH (0x0023 )//* 4)
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#define BUF1_OFFSET (0x0026 )//* 4)
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#define BUF1_PITCH (0x0029 )//* 4)
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//
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// Handle private interface between the 3D driver and the 2D GDI
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// driver
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//
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typedef struct {
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DWORD dwSize; // size of this struct
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DWORD dwVideoBaseAddr; // linear address to aperture
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DWORD dwRegisterBaseAddr; // linear address to registers
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DWORD dwOffScreenAddr; // linear address to offscreen memory
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DWORD dwOffScreenSize; // size of offscreen memory
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DWORD dwTotalRAM; // amount of RAM on the card
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DWORD dwFIFOSize; // size of FIFO, (tbfl)
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DWORD dwScreenWidth; // screen width
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DWORD dwScreenHeight; // screen height
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DWORD dwScreenPitch; // screen pitch
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DWORD dwBpp; // bits per pixel
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// 1
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// 4
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// 8
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// 15 = 1555 format
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// 16 = 565 format
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// 24
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// 32
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BOOL b3DAvail; // driver supports 3D operations
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DWORD dwChipID; // 3D chip id code
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DWORD dwChipRevision; // 3D chip revision
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DWORD dwAlphaBitMask; // Alpha bit mask
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DWORD dwRedBitMask; // Red Bit Mask
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DWORD dwGreenBitMask; // Green Bit Mask
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DWORD dwBlueBitMask; // Blue Bit Mask
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} PHX2DHWINFO, PPHX2DHWINFO;
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// defines and structures for Brooktree819
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#define LINE_STORE_ENABLE 0
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#define MAX_POSSIB_CARDS 4
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//void FAR WriteBT819Reg (WORD wCard, BYTE bReg, WORD wData );
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//WORD FAR ReadBT819Reg (WORD wCard, BYTE bReg );
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//Physical Registers' Description
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typedef struct tagMAPBT819INFO {
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BYTE bFunctionality; // multifunctional - 1, monofunctional - 0, 2 - read only
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BYTE bReserved; // reserved - 1, active - 0
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BYTE bData; // data (a byte)
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}MAPBT819INFO;
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typedef MAPBT819INFO *MAPBT819;
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//Logical Registers' Description
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typedef struct tagREGSBT819INFO
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{
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BYTE bSize; // size of the register in bits
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BYTE bAddrLSBs; // register's LSBs address (0 - 31)
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BYTE bOffsetLSBs; // register's LSB offset (0 - 7)
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BYTE bMaskLSBs; // mask for LSBs (0x0 - 0xFF)
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BYTE bAddrMSBs; // register's MSBs address - for the registers longer than 1 byte
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BYTE bOffsetMSBs; // register's MSB offset - for the registers longer than 1 byte
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BYTE bMaskMSBs; // mask for MSBs - for the registers longer than 1 byte
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BYTE RegStatus; // read only - 1, otherwise - 0
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}REGSBT819INFO;
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typedef WORD REGSBT819DEF;
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// BT819 MAP BOUNDARIES' FLAGS
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#define RESERVED (BYTE) 1
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#define ACTIVE (BYTE) 0
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#define MULTIFUNC (BYTE) 1
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#define MONOFUNC (BYTE) 0
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#define READONLY (BYTE) 2
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// INDEX OF BT819 PHYSICAL REGISTERS - 1K BOUNDRIES OF THE 32K BT819 REGISTER MAP:
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#define STATUS (BYTE) 0x0
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#define IFORM (BYTE) 0x1
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#define TDEC (BYTE) 0x2
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#define CROP (BYTE) 0x3
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#define VDELAY_LO (BYTE) 0x4
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#define VACTIVE_LO (BYTE) 0x5
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#define HDELAY_LO (BYTE) 0x6
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#define HACTIVE_LO (BYTE) 0x7
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#define HSCALE_HI (BYTE) 0x8
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#define HSCALE_LO (BYTE) 0x9
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#define BRIGHT (BYTE) 0xA
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#define CONTROL (BYTE) 0xB
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#define CONTRAST_LO (BYTE) 0xC
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#define SAT_U_LO (BYTE) 0xD
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#define SAT_V_LO (BYTE) 0xE
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#define HUE (BYTE) 0xF
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#define RESERV_1 (BYTE) 0x10 //reserved byte
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#define RESERV_2 (BYTE) 0x11 //reserved byte
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#define OFORM (BYTE) 0x12
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#define VSCALE_HI (BYTE) 0x13
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#define VSCALE_LO (BYTE) 0x14
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#define TEST (BYTE) 0x15
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#define VPOLE (BYTE) 0x16
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#define IDCODE (BYTE) 0x17
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#define ADELAY (BYTE) 0x18
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#define BDELAY (BYTE) 0x19
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#define ADC (BYTE) 0x1A
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#define RESERV_3 (BYTE) 0x1B //reserved byte
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#define RESERV_4 (BYTE) 0x1C //reserved byte
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#define RESERV_5 (BYTE) 0x1D //reserved byte
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#define RESERV_6 (BYTE) 0x1E //reserved byte
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#define SRESET (BYTE) 0x1F
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#define NUM_BT819_BNDS (BYTE) 32
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// END
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//LIST OF LOGICAL REGISTERS:
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enum tagBT819LOGREGS
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{
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reg819_PRES,
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reg819_HLOC,
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reg819_FIELD,
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reg819_NUML,
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reg819_CSEL,
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reg819_LOF,
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reg819_COF,
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reg819_HACTIVE_I,
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reg819_MUXSEL,
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reg819_XTSEL,
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reg819_FORMAT,
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reg819_DEC_FIELD,
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reg819_DEC_RAT,
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reg819_VDELAY,
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reg819_VACTIVE,
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reg819_HDELAY,
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reg819_HACTIVE,
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reg819_HSCALE,
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reg819_BRIGHT,
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reg819_LNOTCH,
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reg819_COMP,
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reg819_LDEC,
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reg819_CBSENSE,
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reg819_INTERP,
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reg819_CON,
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reg819_SAT_U,
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reg819_SAT_V,
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reg819_HUE,
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reg819_RANGE,
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reg819_RND,
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reg819_FIFO_BURST,
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reg819_CODE,
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reg819_LEN,
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reg819_SPI,
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reg819_FULL,
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reg819_LINE,
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reg819_COMB,
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reg819_INT,
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reg819_VSCALE,
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reg819_OUTEN,
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reg819_VALID_PIN,
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reg819_AFF_PIN,
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reg819_CBFLAG_PIN,
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reg819_FIELD_PIN,
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reg819_ACTIVE_PIN,
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reg819_HRESET_PIN,
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reg819_VRESET_PIN,
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reg819_PART_ID,
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reg819_PART_REV,
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reg819_ADELAY,
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reg819_BDELAY,
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reg819_CLAMP,
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reg819_SYNC_T,
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reg819_AGC_EN,
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reg819_CLK_SLEEP,
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reg819_Y_SLEEP,
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reg819_C_SLEEP,
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reg819_SRESET
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}BT819LOGREGS;
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#define NUM_BT819_REGS (BYTE) 58
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#define reg819_PRES_DEF (WORD) 0x0000
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#define reg819_HLOC_DEF (WORD) 0x0000
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#define reg819_FIELD_DEF (WORD) 0x0000
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#define reg819_NUML_DEF (WORD) 0x0000
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#define reg819_CSEL_DEF (WORD) 0x0000
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#define reg819_LOF_DEF (WORD) 0x0000
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#define reg819_COF_DEF (WORD) 0x0000
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#define reg819_HACTIVE_I_DEF_DEF (WORD) 0x0000
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#define reg819_MUXSEL_DEF (WORD) 0x0002
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#define reg819_XTSEL_DEF (WORD) 0x0003
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#define reg819_FORMAT_DEF (WORD) 0x0000
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#define reg819_DEC_FIELD_DEF (WORD) 0x0000
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#define reg819_DEC_RAT_DEF (WORD) 0x0000
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#define reg819_VDELAY_DEF (WORD) 0x0016
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#define reg819_VACTIVE_DEF (WORD) 0x01E0
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#define reg819_HDELAY_DEF (WORD) 0x0078
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#define reg819_HACTIVE_DEF (WORD) 0x0280
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#define reg819_HSCALE_DEF (WORD) 0x02AC
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#define reg819_BRIGHT_DEF (WORD) 0x0000
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#define reg819_LNOTCH_DEF (WORD) 0x0000
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#define reg819_COMP_DEF (WORD) 0x0000
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#define reg819_LDEC_DEF (WORD) 0x0001
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#define reg819_CBSENSE_DEF (WORD) 0x0000
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#define reg819_INTERP_DEF (WORD) 0x0000
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#define reg819_CON_DEF (WORD) 0x00D8
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#define reg819_SAT_U_DEF (WORD) 0x00FE
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#define reg819_SAT_V_DEF (WORD) 0x00B4
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#define reg819_HUE_DEF (WORD) 0x0000
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#define reg819_RANGE_DEF (WORD) 0x0000
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#define reg819_RND_DEF (WORD) 0x0000
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#define reg819_FIFO_BURST_DEF (WORD) 0x0000
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#define reg819_CODE_DEF_DEF (WORD) 0x0000
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#define reg819_LEN_DEF (WORD) 0x0001
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#define reg819_SPI_DEF (WORD) 0x0001
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#define reg819_FULL_DEF (WORD) 0x0000
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#define reg819_LINE_DEF (WORD) 0x0000
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#define reg819_COMB_DEF (WORD) 0x0001
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#define reg819_INT_DEF (WORD) 0x0001
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#define reg819_VSCALE_DEF (WORD) 0x0000
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#define reg819_OUTEN_DEF (WORD) 0x0000
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#define reg819_VALID_PIN_DEF (WORD) 0x0000
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#define reg819_AFF_PIN_DEF (WORD) 0x0000
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#define reg819_CBFLAG_PIN_DEF (WORD) 0x0000
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#define reg819_FIELD_PIN_DEF (WORD) 0x0000
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#define reg819_ACTIVE_PIN_DEF (WORD) 0x0000
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#define reg819_HRESET_PIN_DEF (WORD) 0x0000
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#define reg819_VRESET_PIN_DEF (WORD) 0x0000
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#define reg819_PART_ID_DEF (WORD) 0x0000 /*Unknown, read only register*/
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#define reg819_PART_REV_DEF (WORD) 0x0000 /*Unknown, read only register*/
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#define reg819_ADELAY_DEF (WORD) 0x0068
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#define reg819_BDELAY_DEF (WORD) 0x005D
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#define reg819_CLAMP_DEF (WORD) 0x0002
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#define reg819_SYNC_T_DEF (WORD) 0x0000
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#define reg819_AGC_EN_DEF (WORD) 0x0000
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#define reg819_CLK_SLEEP_DEF (WORD) 0x0000
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#define reg819_Y_SLEEP_DEF (WORD) 0x0000
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#define reg819_C_SLEEP_DEF (WORD) 0x0001
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#define reg819_SRESET_DEF (WORD) 0x0000
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/**************************************************************************************************************************************/
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static MAPBT819INFO MapBT819DEF[NUM_BT819_BNDS] = /*default value*/
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{
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{ MULTIFUNC, ACTIVE, 0x0 }, //STATUS
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{ MULTIFUNC, ACTIVE, 0x58}, //IFORM
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{ MULTIFUNC, ACTIVE, 0x0}, //TDEC
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{ MULTIFUNC, ACTIVE, 0x12}, //CROP
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{ MONOFUNC, ACTIVE, 0x16}, //VDELAY_LO
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{ MONOFUNC, ACTIVE, 0xE0}, //VACTIVE_LO
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{ MONOFUNC, ACTIVE, 0x78}, //HDELAY_LO
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{ MONOFUNC, ACTIVE, 0x80}, //HACTIVE_LO
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{ MONOFUNC, ACTIVE, 0x2}, //HSCALE_HI
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{ MONOFUNC, ACTIVE, 0xAC}, //HSCALE_LO
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{ MONOFUNC, ACTIVE, 0x0}, //BRIGHT
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{ MULTIFUNC, ACTIVE, 0x20}, //CONTROL
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{ MONOFUNC, ACTIVE, 0xD8}, //CONTRAST_LO
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{ MONOFUNC, ACTIVE, 0xFE}, //SAT_U_LO,
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{ MONOFUNC, ACTIVE, 0xB4}, //SAT_V_LO,
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{ MONOFUNC, ACTIVE, 0x0}, //HUE,
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{ MONOFUNC, RESERVED, 0x0}, //RESERV_1,
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{ MONOFUNC, RESERVED, 0x0}, //RESERV_2,
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{ MULTIFUNC, ACTIVE, 0x6}, //OFORM,
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{ MULTIFUNC, ACTIVE, 0x60}, //VSCALE_HI,
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{ MONOFUNC, ACTIVE, 0x0}, //VSCALE_LO,
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{ MONOFUNC, RESERVED, 0x1}, //TEST,
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{ MULTIFUNC, ACTIVE, 0x0}, //VPOLE,
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{ MULTIFUNC, READONLY, 0}, //IDCODE,
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{ MONOFUNC, ACTIVE, 0x68}, //ADELAY,
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{ MONOFUNC, ACTIVE, 0x5D}, //BDELAY,
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{ MULTIFUNC, ACTIVE, 0x82}, //ADC,
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{ MONOFUNC, RESERVED, 0x0}, //RESERV_3,
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{ MONOFUNC, RESERVED, 0x0}, //RESERV_4,
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{ MONOFUNC, RESERVED, 0x0}, //RESERV_5,
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{ MONOFUNC, RESERVED, 0x0}, //RESERV_6,
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{ MONOFUNC, ACTIVE, 0x0} //SRESET,
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};
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// this array is initialized in pal_supp.c
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#if 0
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REGSBT819INFO RegsBT819[NUM_BT819_REGS] = { /* Register's Name*/
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{ 1, STATUS, 0, 0x7F, 0, 0, 0, 0 }, // 0 - PRES
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{ 1, STATUS, 1, 0xBF, 0, 0, 0, 0 }, // 1 - HLOC
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{ 1, STATUS, 2, 0xDF, 0, 0, 0, 0 }, // 2 - FIELD
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{ 1, STATUS, 3, 0xEF, 0, 0, 0, 0 }, // 3 - NUML
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{ 1, STATUS, 4, 0xF7, 0, 0, 0, 0 }, // 4 - CSEL
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{ 1, STATUS, 6, 0xFD, 0, 0, 0, 0 }, // 5 - LOF
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{ 1, STATUS, 7, 0xFE, 0, 0, 0, 0 }, // 6 - COF
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{ 1, IFORM, 0, 0x7F, 0, 0, 0, 0 }, // 7 - HACTIVE_I
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{ 2, IFORM, 1, 0x9F, 0, 0, 0, 0 }, // 8 - MUXEL
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{ 2, IFORM, 3, 0xE7, 0, 0, 0, 0 }, // 9 - XTSEL
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{ 2, IFORM, 6, 0xFC, 0, 0, 0, 0 }, // 10 - FORMAT
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{ 1, TDEC, 0, 0x7F, 0, 0, 0, 0 }, // 11 - DEC_FIELD
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{ 7, TDEC, 1, 0x80, 0, 0, 0, 0 }, // 12 - DEC_RAT
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{ 10, VDELAY_LO, 0, 0x00, CROP, 0, 0x3F, 0 }, // 13 - VDELAY
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{ 10, VACTIVE_LO, 0, 0x00, CROP, 2, 0xCF, 0 }, // 14 - VACTIVE
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{ 10, HDELAY_LO, 0, 0x00, CROP, 4, 0xF3, 0 }, // 15 - HDELAY
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{ 10, HACTIVE_LO, 0, 0x00, CROP, 6, 0xFC, 0 }, // 16 - HACTIVE
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{ 16, HSCALE_LO, 0, 0x00, HSCALE_HI, 0, 0x00, 0 }, // 17 - HSCALE
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{ 8, BRIGHT, 0, 0x00, 0, 0, 0, 0 }, // 18 - BRIGHT
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{ 1, CONTROL, 0, 0x7F, 0, 0, 0, 0 }, // 19 - LNOTCH
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{ 1, CONTROL, 1, 0xBF, 0, 0, 0, 0 }, // 20 - COMP
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{ 1, CONTROL, 2, 0xDF, 0, 0, 0, 0 }, // 21 - LDEC
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{ 1, CONTROL, 3, 0xEF, 0, 0, 0, 0 }, // 22 - CBSENSE
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{ 1, CONTROL, 4, 0xF7, 0, 0, 0, 0 }, // 23 - INTERP
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{ 9, CONTRAST_LO, 0, 0x00, CONTROL, 5, 0xFB, 0 }, // 24 - CON
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{ 9, SAT_U_LO, 0, 0x00, CONTROL, 6, 0xFD, 0 }, // 25 - SAT_U
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{ 9, SAT_V_LO, 0, 0x00, CONTROL, 7, 0xFE, 0 }, // 26 - SAT_V
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{ 8, HUE, 0, 0x00, 0, 0, 0, 0 }, // 27 - HUE
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{ 1, OFORM, 0, 0x7F, 0, 0, 0, 0 }, // 28 - RANGE
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{ 2, OFORM, 1, 0x9F, 0, 0, 0, 0 }, // 29 - RND
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{ 1, OFORM, 3, 0xEF, 0, 0, 0, 0 }, // 30 - FIFO_BURST
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{ 1, OFORM, 4, 0xF7, 0, 0, 0, 0 }, // 31 - CODE
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{ 1, OFORM, 5, 0xFB, 0, 0, 0, 0 }, // 32 - LEN
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{ 1, OFORM, 6, 0xFD, 0, 0, 0, 0 }, // 33 - SPI
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{ 1, OFORM, 7, 0xFE, 0, 0, 0, 0 }, // 34 - FULL
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{ 1, VSCALE_HI, 0, 0x7F, 0, 0, 0, 0 }, // 35 - LINE
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{ 1, VSCALE_HI, 1, 0xBF, 0, 0, 0, 0 }, // 36 - COMB
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{ 1, VSCALE_HI, 2, 0xDF, 0, 0, 0, 0 }, // 37 - INT
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{ 13,VSCALE_LO, 0, 0x00, VSCALE_HI, 3, 0xE0, 0 }, // 38 - VSCALE
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{ 1, VPOLE, 0, 0x7F, 0, 0, 0, 0 }, // 39 - OUTEN
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{ 1, VPOLE, 1, 0xBF, 0, 0, 0, 0 }, // 40 - VALID_PIN
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{ 1, VPOLE, 2, 0xDF, 0, 0, 0, 0 }, // 41 - AFF_PIN
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{ 1, VPOLE, 3, 0xEF, 0, 0, 0, 0 }, // 42 - CBFLAG_PIN
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{ 1, VPOLE, 4, 0xF7, 0, 0, 0, 0 }, // 43 - FIELD_PIN
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{ 1, VPOLE, 5, 0xFB, 0, 0, 0, 0 }, // 44 - ACTIVE_PIN
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{ 1, VPOLE, 6, 0xFD, 0, 0, 0, 0 }, // 45 - HRESET_PIN
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{ 1, VPOLE, 7, 0xFE, 0, 0, 0, 0 }, // 46 - VRESET_PIN
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{ 4, IDCODE, 0, 0, 0, 0, 0, READONLY }, // 47 - PART_ID
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{ 4, IDCODE, 4, 0, 0, 0, 0, READONLY }, // 48 - PART_REV
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{ 8, ADELAY, 0, 0x00, 0, 0, 0, 0 }, // 49 - ADELAY
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{ 8, BDELAY, 0, 0x00, 0, 0, 0, 0 }, // 50 - BDELAY
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{ 2, ADC, 0, 0x3F, 0, 0, 0, 0 }, // 51 - CLAMP
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{ 1, ADC, 2, 0xDF, 0, 0, 0, 0 }, // 52 - SYNC_T
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{ 1, ADC, 3, 0xEF, 0, 0, 0, 0 }, // 53 - AGC_EN
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{ 1, ADC, 4, 0xF7, 0, 0, 0, 0 }, // 54 - CLK_SLEEP
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{ 1, ADC, 5, 0xFB, 0, 0, 0, 0 }, // 55 - Y_SLEEP
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{ 1, ADC, 6, 0xFD, 0, 0, 0, 0 }, // 56 - C_SLEEP
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{ 8, SRESET, 0, 0x00, 0, 0, 0, 0 }, // 57 - SRESET
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};
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#endif
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// The following array contains default values for BT819 logical registers
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static REGSBT819DEF RegsBT819Def[NUM_BT819_REGS] = {
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reg819_PRES_DEF,
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reg819_HLOC_DEF,
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reg819_FIELD_DEF,
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reg819_NUML_DEF,
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reg819_CSEL_DEF,
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reg819_LOF_DEF,
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reg819_COF_DEF,
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reg819_HACTIVE_I_DEF_DEF,
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reg819_MUXSEL_DEF,
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reg819_XTSEL_DEF,
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reg819_FORMAT_DEF,
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reg819_DEC_FIELD_DEF,
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reg819_DEC_RAT_DEF,
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reg819_VDELAY_DEF,
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reg819_VACTIVE_DEF,
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reg819_HDELAY_DEF,
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reg819_HACTIVE_DEF,
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reg819_HSCALE_DEF,
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reg819_BRIGHT_DEF,
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reg819_LNOTCH_DEF,
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reg819_COMP_DEF,
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reg819_LDEC_DEF,
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reg819_CBSENSE_DEF,
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reg819_INTERP_DEF,
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reg819_CON_DEF,
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reg819_SAT_U_DEF,
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reg819_SAT_V_DEF,
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reg819_HUE_DEF,
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reg819_RANGE_DEF,
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reg819_RND_DEF,
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reg819_FIFO_BURST_DEF,
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reg819_CODE_DEF_DEF,
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reg819_LEN_DEF,
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reg819_SPI_DEF,
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reg819_FULL_DEF,
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reg819_LINE_DEF,
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reg819_COMB_DEF,
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reg819_INT_DEF,
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reg819_VSCALE_DEF,
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reg819_OUTEN_DEF,
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reg819_VALID_PIN_DEF,
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reg819_AFF_PIN_DEF,
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reg819_CBFLAG_PIN_DEF,
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reg819_FIELD_PIN_DEF,
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reg819_ACTIVE_PIN_DEF,
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reg819_HRESET_PIN_DEF,
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reg819_VRESET_PIN_DEF,
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reg819_PART_ID_DEF,
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reg819_PART_REV_DEF,
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reg819_ADELAY_DEF,
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reg819_BDELAY_DEF,
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reg819_CLAMP_DEF,
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reg819_SYNC_T_DEF,
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reg819_AGC_EN_DEF,
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reg819_CLK_SLEEP_DEF,
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reg819_Y_SLEEP_DEF,
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reg819_C_SLEEP_DEF,
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reg819_SRESET_DEF
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};
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// end defines and structures for Brooktree819
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// defines for I2C support
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//#define ATIAPI
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#define I2C_ACK_WR_ERROR 0x01
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#define I2C_ACK_RD_ERROR 0x02
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#define I2C_COLIDE 0x04
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/*
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I2C Bus constants
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*/
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#define I2C_HIGH (BYTE) 1
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#define I2C_LOW (BYTE) 0
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#define I2C_TIME_DELAY (BYTE) 5
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#define I2C_WRITE (BOOL)TRUE
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#define I2C_READ ( BOOL) FALSE
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// end for I2C support
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/*
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void Init3D_Info(PDEV*,PVOID);
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ULONG GetDisplayMode(PDEV* ,PVOID ) ;
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ULONG AccessDevice(PDEV* , PVOID, PVOID ) ;
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ULONG GetConfiguration(PDEV* ,PVOID ) ;
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ULONG WriteRegFnct(PDEV* ,PVOID ) ;
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ULONG ReadRegFnct(PDEV* ,PVOID , PVOID) ;
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void I2CAccess_New(PDEV* ,LPI2CSTRUCT_NEW ,LPI2CSTRUCT_NEW ) ;
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BYTE ReverseByte(BYTE ) ;
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WORD Ack(PDEV*, WORD , BOOL ) ;
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void Start(PDEV*, WORD ) ;
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void Stop(PDEV*, WORD ) ;
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void I2CDelay(PDEV*, WORD) ;
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void WriteByteI2C(PDEV*, WORD , BYTE ) ;
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BYTE ReadByteI2C(PDEV*,WORD ) ;
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BOOL DisableOvl(PDEV* ) ;
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ULONG AllocOffscreenMem(PDEV* , PVOID , PVOID) ;
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ULONG DeallocOffscreenMem(PDEV* ) ;
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ULONG AllocOffscreenMem(PDEV* , PVOID , PVOID ) ;
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void WriteVT264Reg(PDEV* , WORD , BYTE , DWORD );
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DWORD ReadVT264Reg(PDEV* , WORD , BYTE ) ;
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void WriteI2CData(PDEV* , WORD , BYTE );
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*/
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/*
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* VT registers that matter for the I2C bus
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*/
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#define vtf_GEN_GIO2_DATA_OUT 1
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#define vtf_GEN_GIO2_WRITE 2
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#define vtf_DAC_GIO_STATE_1 3
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#define vtf_GEN_GIO2_DATA_IN 4
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#define vtf_CFG_CHIP_FND_ID 5
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#define vtf_GEN_GIO3_DATA_OUT 6
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#define vtf_GEN_GIO2_EN 7
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#define vtf_DAC_FEA_CON_EN 8
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#define vtf_DAC_GIO_DIR_1 9
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// for VTB, GTB support
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#define vtf_GP_IO_4 10
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#define vtf_GP_IO_DIR_4 11
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#define vtf_GP_IO_B 12
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#define vtf_GP_IO_7 13
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#define vtf_GP_IO_DIR_B 14
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#define vtf_CFG_CHIP_MAJOR 15
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#endif
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#if 0 // the structure was moved in driver.h
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// this structure is used (as a static and global structure) instead of the ppdev structure for keeping the values for
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// pal support in NT4.0 since returning from DOS full screen with Alt+Enter will reinitialize the pdev and will lose
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// all the info
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typedef struct _ppdev_pal_type
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{
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ULONG no_lines_allocated; // number of lines already allocated by "alloc mem" in offscreen mem
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//flags for palindrome
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BOOL dos_flag;
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BOOL Palindrome_flag;
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BOOL Realloc_mem_flag;
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BOOL Mode_Switch_flag;
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BOOL No_mem_allocated_flag;
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DWORD* preg;
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//storage for buffers values (needed after a mode switch; ATIPlayer doesn't know that the mode was changed)
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DWORD Buf0_Offset;
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//DWORD Buf_Scaler1; //for the moment this is the same as the previous
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//globals for CWDDE
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ACCESSDEVICEDATA* lpOwnerAccessStructConnector;
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ACCESSDEVICEDATA* lpOwnerAccessStructOverlay;
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BOOL Flag_DCIIsEnabled;
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ULONG Counter_DCIIsEnabled;
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BOOL Flag_Control_ConfigIsEnabled;
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// for offscreen allocation history for palindrome
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int alloc_cnt;
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alloc_history alloc_hist[8];
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// global value for the pointer to the permanent node (off-screen memory allocation)
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OH* poh;
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// for DCIEnable CWDDE call
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PVOID pData;
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PVOID CallBackFnct;
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} PPDEV_PAL_NT;
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#endif
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// structure used in mode switch by DCIEnable
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typedef struct tagDCICB
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{
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DWORD dwDCICB_FuncCode;
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LPVOID lpDCICB_FuncData;
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} DCICB;
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#endif
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