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796 lines
19 KiB
796 lines
19 KiB
/************************************************************************/
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/* */
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/* EEVGA.C */
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/* */
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/* Copyright (c) 1992 ATI Technologies Inc. */
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/************************************************************************/
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/* */
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/********************** PolyTron RCS Utilities
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$Revision: 1.3 $
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$Date: 23 Jan 1996 11:46:08 $
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$Author: RWolff $
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$Log: S:/source/wnt/ms11/miniport/archive/eevga.c_v $
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*
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* Rev 1.3 23 Jan 1996 11:46:08 RWolff
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* Eliminated level 3 warnings.
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*
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* Rev 1.2 23 Dec 1994 10:47:10 ASHANMUG
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* ALPHA/Chrontel-DAC
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*
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* Rev 1.1 07 Feb 1994 14:07:44 RWOLFF
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* Added alloc_text() pragmas to allow miniport to be swapped out when
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* not needed.
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*
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* Rev 1.0 31 Jan 1994 11:08:26 RWOLFF
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* Initial revision.
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Rev 1.2 08 Oct 1993 15:17:28 RWOLFF
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No longer includes VIDFIND.H.
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Rev 1.1 03 Sep 1993 14:23:18 RWOLFF
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Partway through CX isolation.
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Rev 1.0 16 Aug 1993 13:26:32 Robert_Wolff
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Initial revision.
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Rev 1.11 24 Jun 1993 14:32:48 RWOLFF
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Microsoft-originated change: now uses VideoPortSynchronizeExecution()
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instead of _disable()/_enable() pairs.
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Rev 1.10 10 May 1993 10:54:08 RWOLFF
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Fixed uninitialized variable in Read_ee().
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Rev 1.9 27 Apr 1993 20:19:40 BRADES
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change extern ati_reg toa long, is a virtual IO address now.
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Rev 1.8 21 Apr 1993 17:31:10 RWOLFF
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Now uses AMACH.H instead of 68800.H/68801.H.
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Rev 1.7 08 Mar 1993 19:28:36 BRADES
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submit to MS NT
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Rev 1.5 06 Jan 1993 11:05:22 Robert_Wolff
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Cleaned up compile warnings.
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Rev 1.4 27 Nov 1992 15:19:30 STEPHEN
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No change.
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Rev 1.3 13 Nov 1992 16:32:32 Robert_Wolff
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Now includes 68801.H, which consists of the now-obsolete MACH8.H
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and elements moved from VIDFIND.H.
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Rev 1.2 12 Nov 1992 16:56:56 Robert_Wolff
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Same source file can now be used for both Windows NT driver and
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VIDEO.EXE test program.
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Rev 1.1 06 Nov 1992 19:02:34 Robert_Wolff
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Moved I/O port defines to VIDFIND.H.
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Rev 1.0 05 Nov 1992 14:01:06 Robert_Wolff
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Initial revision.
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Rev 1.1 01 Oct 1992 15:29:08 Robert_Wolff
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Can now handle both Mach32 and Mach8 cards.
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Rev 1.0 14 Sep 1992 09:44:30 Robert_Wolff
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Initial revision.
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End of PolyTron RCS section *****************/
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#if defined(DOC)
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EEVGA.C - EEPROM read and write routines
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DESCRIPTION:
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VGA EEPROM read and write routines
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September 4 1992 - R. Wolff
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Translated from assembler into C.
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August 28 1992 - C. Brady.
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This has been adapted from the VGA$EEC.ASM software by Steve Stefanidis
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The original code used externs to long_delay() and short_delay(), these
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where changed to use local function delay.
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The original used compile time options to work with various VGA revisions,
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it is required to be run time determinate since we need to access
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eeprom VGA style (how archaic) for the Graphics Ultra (38800) and the
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68800 family of graphics controllers.
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OLD_EEPROM_MAP equ 1 ; enables the Old EEPROM Handling routines
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REMOVED, the DETECT.C routine assigns the eeprom address size used
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in EE_addr(). I do not know of a Graphics Ultra using 7 bit address
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since they ONLY had a 1k eeprom == 64 words.
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#endif
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#include <conio.h>
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#include <dos.h>
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#include "miniport.h"
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#include "ntddvdeo.h"
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#include "video.h"
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#include "stdtyp.h"
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#include "amach.h"
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#include "amach1.h"
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#include "atimp.h"
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#include "cvtvga.h" /* For SplitWord data type */
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#include "eeprom.h"
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#include "services.h"
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#define OFF 0
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#define ON 1
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#define IND_OFFSET 0x00B0
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#define SYNC_I 0x008 ^ IND_OFFSET
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#define L_ALL 0x004
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#define MISC3_I 0x010 ^ IND_OFFSET
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#define EEPROM 0x020 /* EEPROM Enable bit */
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#define EE_WREG 0x003 ^ IND_OFFSET
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#define EE_CS 0x008 /* Chip Select bit */
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#define EE_ENABLE 0x004
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#define EE_CLK 0x002
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#define EE_DI 0x001
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#define EE_RREG 0x007 ^ IND_OFFSET
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#define EE_DO 0x008
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/*
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* Definitions for reading and writing the VGA sequencer registers.
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*/
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#define SD_CLOCK 0x0001 /* Index for clock mode register */
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/*
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* Bit to set in clock mode register to blank the screen and disable
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* video-generation logic access to video memory.
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*/
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#define SD_CLK_OFF 0x020
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ULONG ati_reg; // Base register for ATI extended VGA registers
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char vga_chip; // VGA chip revision as ascii
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/*
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* Storage for register where EEPROM read/write happens.
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*/
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static union SplitWord zEepromIOPort;
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/*
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* Storage for original status which is determined in Sel_EE() and
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* which must be restored in DeSel_EE().
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*/
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static union SplitWord zOrigStat;
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/*
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* EEPROM word to be read/written/erased/etc.
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*/
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static unsigned char ucEepromWord;
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static void setscrn(int iSetting);
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static unsigned short Read_ee(void);
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static void ee_sel_vga(void);
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static void ee_clock_vga(void);
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static void EE_control(unsigned char ucEepromStatus);
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static void ee_deselect_vga(void);
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static void Write_ee(unsigned short uiData);
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static void Enabl_ee(void);
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static void Disab_ee(void);
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static void Erase_ee(void);
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extern void ee_wait(void);
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/*
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* Allow miniport to be swapped out when not needed.
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*
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* The following routines are called through function pointers
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* rather than an explicit call to the routine, and may run into
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* trouble if paged out. If problems develop, make them un-pageable:
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* ee_read_vga()
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* ee_cmd_vga()
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*/
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#if defined (ALLOC_PRAGMA)
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#pragma alloc_text(PAGE_M, ee_read_vga)
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#pragma alloc_text(PAGE_M, ee_write_vga)
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#pragma alloc_text(PAGE_M, ee_erase_vga)
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#pragma alloc_text(PAGE_M, ee_enab_vga)
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#pragma alloc_text(PAGE_M, ee_disab_vga)
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#pragma alloc_text(PAGE_M, setscrn)
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#pragma alloc_text(PAGE_M, Read_ee)
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#pragma alloc_text(PAGE_M, ee_sel_vga)
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#pragma alloc_text(PAGE_M, ee_cmd_vga)
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#pragma alloc_text(PAGE_M, ee_sel_eeprom)
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#pragma alloc_text(PAGE_M, ee_clock_vga)
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#pragma alloc_text(PAGE_M, EE_control)
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#pragma alloc_text(PAGE_M, ee_deselect_vga)
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#pragma alloc_text(PAGE_M, Write_ee)
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#pragma alloc_text(PAGE_M, Enabl_ee)
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#pragma alloc_text(PAGE_M, Disab_ee)
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#pragma alloc_text(PAGE_M, Erase_ee)
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#endif
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/*
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* WORD ee_read_vga(iIndex);
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*
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* short iIndex; Which word of EEPROM should be read
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*
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* Read the specified word from the EEPROM.
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*/
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WORD ee_read_vga(short iIndex)
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{
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unsigned short uiRetVal; /* Value returned by Read_ee() */
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setscrn(OFF); /* Disable the video card */
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/*
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* Set up the word index within the EEPROM and the chip identifier.
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*/
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ucEepromWord = iIndex & 0x00ff;
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uiRetVal = Read_ee(); /* Get the word */
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setscrn(ON); /* Re-enable the video card */
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return uiRetVal;
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}
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/*
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* void ee_write_vga(uiIndex, uiData);
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*
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* unsigned short uiIndex;
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* unsigned short uiData;
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*
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* Routine to write a word to the EEPROM.
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*/
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void ee_write_vga(unsigned short uiIndex, unsigned short uiData)
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{
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setscrn(OFF);
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ucEepromWord = uiIndex & 0x00ff;
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Write_ee(uiData);
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ee_wait();
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setscrn(ON);
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return;
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}
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/*
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* void ee_erase_vga(uiIndex);
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*
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* unsigned short uiIndex;
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*
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* Routine to erase a word in the EEPROM.
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*/
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void ee_erase_vga(unsigned short uiIndex)
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{
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setscrn(OFF);
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ucEepromWord = uiIndex & 0x00ff;
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Erase_ee();
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setscrn(ON);
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ee_wait();
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return;
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}
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/*
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* void ee_enab_vga(void);
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*
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* Routine to enable the EEPROM.
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*/
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void ee_enab_vga()
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{
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setscrn(OFF);
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Enabl_ee();
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setscrn(ON);
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return;
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}
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/*
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* void ee_disab_vga(void);
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*
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* Routine to disable the EEPROM.
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*/
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void ee_disab_vga(void)
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{
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setscrn(OFF);
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Disab_ee();
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setscrn(ON);
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ee_wait();
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return;
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}
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/*
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* static void setscrn(iSetting);
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*
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* int iSetting; Should the video card be enabled (ON) or disabled (OFF)
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*
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* Enable or disable the video card, as selected by the caller.
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*/
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static void setscrn(int iSetting)
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{
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static unsigned char ucSavedMode; /* Saved value of clock mode register */
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if (iSetting)
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{
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/*
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* Caller wants to unblank the screen.
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*
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* Point the sequencer index register to the clock mode register.
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*/
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OUTP(SEQ_IND, SD_CLOCK);
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/*
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* Set the clock mode register to the value it had before we
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* blanked the screen.
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*/
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OUTP(SEQ_DATA, ucSavedMode);
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}
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else{
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/*
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* Caller wants to blank the screen.
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*
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* Point the sequencer index register to the clock mode register.
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*/
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OUTP(SEQ_IND, SD_CLOCK);
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/*
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* Read and save the current contents of the clock mode register.
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*/
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ucSavedMode = INP(SEQ_DATA);
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/*
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* Blank the screen without changing the other contents
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* of the clock mode register.
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*/
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OUTP(SEQ_DATA, (BYTE)(ucSavedMode | SD_CLK_OFF));
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}
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return;
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}
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/*
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* static unsigned short Read_ee(void);
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*
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* A lower-level way of getting a word out of the EEPROM.
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*/
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static unsigned short Read_ee(void)
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{
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int iCount; /* Loop counter */
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unsigned short uiValueRead = 0; /* Value read from the EEPROM */
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union SplitWord zStateSet; /* Used in setting the video state */
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ee_sel_vga();
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if (vga_chip >= '4') /* ASIC revision level */
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{
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/*
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* Set read/write bit of ATI register 26 to read.
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*/
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zStateSet.byte.low = 0x0a6;
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OUTP(ati_reg, zStateSet.byte.low);
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zStateSet.byte.high = INP(ati_reg+1);
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OUTPW(ati_reg, (WORD)((zStateSet.word & 0x0FBFF)));
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}
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ee_cmd_vga((unsigned short) (EE_READ | ucEepromWord));
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zEepromIOPort.byte.high &= (~EE_DI);
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OUTPW(ati_reg, zEepromIOPort.word);
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ee_clock_vga();
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/*
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* Read in the word, one bit at a time.
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*/
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for (iCount = 0; iCount < 16; iCount++)
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{
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uiValueRead = uiValueRead << 1;
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OUTP(ati_reg, EE_RREG);
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if (INP(ati_reg+1) & EE_DO)
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uiValueRead |= 1;
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ee_clock_vga();
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}
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ee_deselect_vga();
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/*
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* Undo the state setting which was done on entry.
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*/
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if (vga_chip >= '4')
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OUTPW(ati_reg, zStateSet.word);
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return uiValueRead;
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}
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/*
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* static void ee_sel_vga(void);
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*
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* This routine selects the EEPROM.
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*/
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static void ee_sel_vga(void)
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{
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if (vga_chip <= '2')
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{
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/*
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* Get the video card's status.
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*/
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VideoPortSynchronizeExecution(phwDeviceExtension,
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VpHighPriority,
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(PMINIPORT_SYNCHRONIZE_ROUTINE)
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ee_sel_eeprom,
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phwDeviceExtension);
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OUTPW(HI_SEQ_ADDR, 0x0100);
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}
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else{
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EE_control(EEPROM);
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}
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return;
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}
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/*
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* void ee_cmd_vga(uiInstruct);
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*
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* unsigned short uiInstruct; Opcode and address to send
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*
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* Sends EEPROM opcode and address to the EEPROM. The uiInstruct
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* parameter holds the 5 bit opcode and 6 bit index in the
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* format xxxx xOOO OOII IIII, where:
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* x is an unused bit
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* O is an opcode bit
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* I is an index bit
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*/
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void ee_cmd_vga(unsigned short uiInstruct)
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{
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struct st_eeprom_data *ee = phwDeviceExtension->ee;
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int iCount; /* Loop counter */
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/*
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* Mask showing which bit to test when sending the opcode or the address.
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*/
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unsigned short uiBitTest;
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/*
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* Get the initial value for the I/O register which
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* will have its bits forced to specific values.
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*/
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VideoPortSynchronizeExecution(phwDeviceExtension,
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VpHighPriority,
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(PMINIPORT_SYNCHRONIZE_ROUTINE) ee_init_io,
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phwDeviceExtension);
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ee_clock_vga();
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zEepromIOPort.byte.high &= (~EE_DI);
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zEepromIOPort.byte.high |= (EE_ENABLE | EE_CS); /* Enable the EEPROM and select the chip */
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OUTPW(ati_reg, zEepromIOPort.word);
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ee_clock_vga();
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/*
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* Send the opcode.
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*/
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uiBitTest = 0x400;
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for (iCount = 0; iCount < 3; iCount++)
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{
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if (uiInstruct & uiBitTest)
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zEepromIOPort.byte.high |= EE_DI;
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else
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zEepromIOPort.byte.high &= (~EE_DI);
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OUTPW(ati_reg, zEepromIOPort.word);
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ee_clock_vga();
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uiBitTest >>= 1;
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}
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/*
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* We have finished with the opcode, now send the address.
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* Assume the EEPROM address is no longer than 8 bits
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* (256 word capacity). The Graphics Ultra series use
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* a 6 bit address (64 words), while the G.U. Plus and
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* Pro use 8 bits (but the EEPROM is only 128 words long).
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* Assume a 6 bit EEPROM address (64 word capacity).
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*/
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uiBitTest = 0x01 << (ee->addr_size - 1);
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for (iCount = 0; iCount < ee->addr_size; iCount++)
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{
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if (uiBitTest & uiInstruct)
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zEepromIOPort.byte.high |= EE_DI;
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else
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zEepromIOPort.byte.high &= (~EE_DI);
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OUTPW(ati_reg, zEepromIOPort.word);
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ee_clock_vga();
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uiBitTest >>= 1;
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}
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return;
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}
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BOOLEAN
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ee_sel_eeprom (
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PVOID Context
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)
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/*++
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Routine Description:
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Selects the eeprom within the context of interrupts being disabled.
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This function must be called via a call to VideoPortSynchronizeRoutine.
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Arguments:
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Context - Context parameter passed to the synchronized routine.
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Must be a pointer to the miniport driver's device extension.
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Return Value:
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TRUE.
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--*/
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{
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union SplitWord zStatus; /* Status of the video card. */
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UNREFERENCED_PARAMETER(Context);
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OUTP(ati_reg, SYNC_I);
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zStatus.byte.high = INP(ati_reg + 1);
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zStatus.byte.low = SYNC_I;
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/*
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|
* Preserve the status so ee_deselect_vga() can restore it.
|
|
*/
|
|
zOrigStat.word = zStatus.word;
|
|
|
|
/*
|
|
* Unlock the EEPROM to allow reading/writing.
|
|
*/
|
|
zStatus.byte.high &= ~L_ALL;
|
|
OUTPW(ati_reg, zStatus.word);
|
|
return TRUE;
|
|
}
|
|
|
|
BOOLEAN
|
|
ee_init_io (
|
|
PVOID Context
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
|
|
Gets the initial value for the I/O register which
|
|
will have its bits forced to specific values.
|
|
|
|
This function must be called via a call to VideoPortSynchronizeRoutine.
|
|
|
|
Arguments:
|
|
|
|
Context - Context parameter passed to the synchronized routine.
|
|
Must be a pointer to the miniport driver's device extension.
|
|
|
|
Return Value:
|
|
|
|
TRUE.
|
|
|
|
--*/
|
|
|
|
{
|
|
UNREFERENCED_PARAMETER(Context);
|
|
|
|
zEepromIOPort.byte.low = EE_WREG;
|
|
OUTP(ati_reg, zEepromIOPort.byte.low);
|
|
zEepromIOPort.byte.high = INP(ati_reg + 1);
|
|
return TRUE;
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
* static void ee_clock_vga(void);
|
|
*
|
|
* Toggle the EEPROM CLK line high then low.
|
|
*/
|
|
static void ee_clock_vga(void)
|
|
{
|
|
ee_wait();
|
|
|
|
zEepromIOPort.byte.high |= EE_CLK;
|
|
OUTPW(ati_reg, zEepromIOPort.word);
|
|
|
|
ee_wait();
|
|
|
|
zEepromIOPort.byte.high &= ~EE_CLK;
|
|
OUTPW(ati_reg, zEepromIOPort.word);
|
|
|
|
return;
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
* static void EE_control(ucEepromStatus);
|
|
*
|
|
* unsigned char ucEepromStatus; Sets whether or not we should access the EEPROM
|
|
*
|
|
* Sets/resets the EEPROM bit of the data register at index MISC3_I.
|
|
* This enables/disables EEPROM access.
|
|
*/
|
|
static void EE_control(unsigned char ucEepromStatus)
|
|
{
|
|
union SplitWord zCtrlData; /* Data read/written at specified control port */
|
|
|
|
|
|
/*
|
|
* Set up to write to the MISC3_I index register, and initialize
|
|
* the data field to the EEPROM status we want.
|
|
*/
|
|
zCtrlData.byte.high = ucEepromStatus;
|
|
zCtrlData.byte.low = MISC3_I;
|
|
OUTP(ati_reg, zCtrlData.byte.low);
|
|
|
|
/*
|
|
* Read in the data which is stored at the index MISC3_I, and combine
|
|
* its contents (other than the EEPROM enable/disable bit)
|
|
* with the desired EEPROM status we received as a parameter.
|
|
*/
|
|
zCtrlData.byte.high |= (INP(ati_reg + 1) & ~EEPROM);
|
|
|
|
/*
|
|
* Write the result back. All bits other than the EEPROM enable/disable
|
|
* bit will be unmodified.
|
|
*/
|
|
OUTPW(ati_reg, zCtrlData.word);
|
|
|
|
return;
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
* static void ee_deselect_vga(void);
|
|
*
|
|
* Purpose: Disable EEPROM read/write
|
|
*/
|
|
static void ee_deselect_vga(void)
|
|
{
|
|
zEepromIOPort.byte.high &= (~EE_CS);
|
|
OUTPW(ati_reg, zEepromIOPort.word);
|
|
ee_clock_vga();
|
|
zEepromIOPort.byte.high &= (~EE_ENABLE);
|
|
OUTPW(ati_reg, zEepromIOPort.word);
|
|
|
|
if (vga_chip <= '2')
|
|
{
|
|
OUTPW(HI_SEQ_ADDR, 0x0300);
|
|
OUTPW(ati_reg, zOrigStat.word);
|
|
}
|
|
else{
|
|
EE_control(0);
|
|
}
|
|
|
|
ee_wait();
|
|
return;
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
* static void Write_ee(uiData);
|
|
*
|
|
* unsigned short uiData; Value to write to the EEPROM.
|
|
*
|
|
* Lower-level routine to write a word to the EEPROM.
|
|
*/
|
|
static void Write_ee(unsigned short uiData)
|
|
{
|
|
int iCount; /* Loop counter */
|
|
|
|
ee_sel_vga();
|
|
|
|
ee_cmd_vga((unsigned short) (EE_WRITE | ucEepromWord));
|
|
|
|
/*
|
|
* Write out the word, one bit at a time.
|
|
*/
|
|
for (iCount = 0; iCount < 16; iCount++)
|
|
{
|
|
if (uiData & 0x8000)
|
|
zEepromIOPort.byte.high |= EE_DI;
|
|
else
|
|
zEepromIOPort.byte.high &= (~EE_DI);
|
|
OUTPW(ati_reg, zEepromIOPort.word);
|
|
|
|
ee_clock_vga();
|
|
uiData = uiData << 1;
|
|
}
|
|
|
|
ee_deselect_vga();
|
|
|
|
return;
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
* Static void Enabl_ee(void);
|
|
*
|
|
* This is a lower-level routine to enable the EEPROM.
|
|
*/
|
|
static void Enabl_ee()
|
|
{
|
|
|
|
ee_sel_vga();
|
|
|
|
ee_cmd_vga((EE_ENAB | 0x3f));
|
|
|
|
ee_deselect_vga();
|
|
|
|
return;
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
* Static void Disab_ee(void);
|
|
*
|
|
* This is a lower-level routine to disable the EEPROM.
|
|
*/
|
|
static void Disab_ee(void)
|
|
{
|
|
|
|
ee_sel_vga();
|
|
|
|
ee_cmd_vga((EE_DISAB | 0x00));
|
|
|
|
ee_deselect_vga();
|
|
|
|
return;
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
* Static void Erase_ee(void);
|
|
*
|
|
* This is a lower-level routine to erase the EEPROM.
|
|
*/
|
|
static void Erase_ee(void)
|
|
{
|
|
|
|
ee_sel_vga();
|
|
|
|
ee_cmd_vga((unsigned short) (EE_ERASE | ucEepromWord));
|
|
|
|
ee_deselect_vga();
|
|
|
|
return;
|
|
}
|