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163 lines
7.0 KiB
163 lines
7.0 KiB
/* *************************************************************************
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** INTEL Corporation Proprietary Information
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**
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** This listing is supplied under the terms of a license
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** agreement with INTEL Corporation and may not be copied
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** nor disclosed except in accordance with the terms of
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** that agreement.
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**
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** Copyright (c) 1995 Intel Corporation.
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** All Rights Reserved.
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**
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** *************************************************************************
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*/
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// $Author: KLILLEVO $
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// $Date: 30 Aug 1996 08:39:58 $
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// $Archive: S:\h26x\src\dec\dxblkadd.cpv $
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// $Header: S:\h26x\src\dec\dxblkadd.cpv 1.7 30 Aug 1996 08:39:58 KLILLEVO $
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// $Log: S:\h26x\src\dec\dxblkadd.cpv $
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//
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// Rev 1.7 30 Aug 1996 08:39:58 KLILLEVO
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// added C version of block edge filter, and changed the bias in
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// ClampTbl[] from 128 to CLAMP_BIAS (defined to 128)
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// The C version of the block edge filter takes up way too much CPU time
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// relative to the rest of the decode time (4 ms for QCIF and 16 ms
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// for CIF on a P120, so this needs to coded in assembly)
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//
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// Rev 1.6 17 Jul 1996 15:33:56 AGUPTA2
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// Increased the size of clamping table ClampTbl to 128+256+128.
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//
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// Rev 1.5 08 Mar 1996 16:46:32 AGUPTA2
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// Moved the ClampTbl to be common between this module and IDCT. Reduced
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// the size of the ClampTbl from 256+256+256 to 64+256+64. IDCT INTER coeffs
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// are biased by 1024 and is taken care of when accessing ClampTbl. Added
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// pragma code_seg to place the rtn in Pass 2 code segment.
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//
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//
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// Rev 1.4 22 Dec 1995 13:52:16 KMILLS
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//
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// added new copyright notice
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//
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// Rev 1.3 25 Sep 1995 09:03:36 CZHU
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// Added comments on cycle counts
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//
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// Rev 1.2 13 Sep 1995 08:46:44 AKASAI
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// Set loopcounter back to 8. Intermediate is 8x8 of DWORDS so TEMPPITCH4
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// should be 32 not 64.
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//
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// Rev 1.1 12 Sep 1995 18:19:20 CZHU
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//
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// Changed loop from 8 to 7 to start with.
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//
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// Rev 1.0 11 Sep 1995 16:52:20 CZHU
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// Initial revision.
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// -------------------------------------------------------------------------
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// T is routine performs a block(8 8) addition.
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// output = clamp[reference + current]
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//
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// Input I32 *current (output of FMIDCT)
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// U8 *reference (Motion Compensated address of reference)
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// U8 *output (Output buffer)
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//
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// Assumption: reference and output use PITCH
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// current as some other pitch
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// -------------------------------------------------------------------------
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#include "precomp.h"
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#define TEMPPITCH4 32
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#pragma data_seg("IADATA2")
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#define FRAMEPOINTER esp
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#define L_LOOPCOUNTER FRAMEPOINTER + 0 // 4 byte
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#define LOCALSIZE 4 // keep aligned
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#pragma code_seg("IACODE2")
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__declspec(naked)
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void BlockAdd (U32 uResidual, U32 uRefBlock,U32 uDstBlock)
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{
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__asm {
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push ebp // save callers frame pointer
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mov ebp,esp // make parameters accessible
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push esi // assumed preserved
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push edi
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push ebx
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sub esp,LOCALSIZE // reserve local storage
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mov edi, uDstBlock ;// edi gets Base addr of OutputBuffer
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mov ecx, 8
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mov esi, uRefBlock; ;// esi gets Base addr of Current
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mov ebp, uResidual ;// ebp gets Base addr of Reference
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mov ebx, [edi] ;// pre-fetch output
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xor eax, eax
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// Cylces counts: 26 x 8=208 without cache miss
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// czhu, 9/25/95
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loop_for_i:
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mov [L_LOOPCOUNTER], ecx ; save loop counter in temporary
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mov ebx, [ebp+8] ; 1) fetch current[i+2]
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mov al, BYTE PTR[esi+2] ; 1) fetch ref[i+2]
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xor ecx, ecx ; 2)
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mov cl, BYTE PTR[esi+3] ; 2) fetch ref[i+3]
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mov edx, [ebp+12] ; 2) fetch current[i+3]
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add eax, ebx ; 1) result2 = ref[i+2] + current[i+2]
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xor ebx, ebx ; 3)
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add ecx, edx ; 2) result3= ref[i+3] + current[i+3]
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mov bl, BYTE PTR[esi+0] ; 3) fetch ref[i]
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mov dl, ClampTbl[CLAMP_BIAS+eax-1024] ; 1) fetch clamp[result2]
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mov eax, [ebp+0] ; 3) fetch current[i]
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add ebx, eax ; 3) result0 = ref[i] + current[i]
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xor eax, eax ; 4)
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mov dh, ClampTbl[CLAMP_BIAS+ecx-1024] ; 2) fetch clamp[result3]
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mov al, [esi+1] ; 4) fetch ref[i+1]
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shl edx, 16 ; move 1st 2 results to high word
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mov ecx, [ebp+4] ; 4) fetch current[i+1]
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mov dl, ClampTbl[CLAMP_BIAS+ebx-1024] ; 3) fetch clamp[result0]
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add eax, ecx ; 4) result1 = ref[i+1] + current[i+1]
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xor ecx, ecx ; 4+1)
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mov ebx, [ebp+24] ; 4+1) fetch current[i+6]
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mov dh, ClampTbl[CLAMP_BIAS+eax-1024] ; 4) fetch clamp[result1]
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mov cl, BYTE PTR[esi+6] ; 4+1) fetch ref[i+6]
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mov [edi], edx ; store 4 output pixels
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xor eax, eax ; 4+2)
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mov al, BYTE PTR[esi+7] ; 4+2) fetch ref[i+7]
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mov edx, [ebp+28] ; 4+2) fetch current[i+7]
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add ecx, ebx ; 4+1) result6 = ref[i+6] + current[i+6]
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xor ebx, ebx ; 4+3)
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add eax, edx ; 4+2) result7= ref[i+7] + current[i+7]
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mov bl, BYTE PTR[esi+4] ; 4+3) fetch ref[i+4]
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mov dl, ClampTbl[CLAMP_BIAS+ecx-1024] ; 4+1) fetch clamp[result6]
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mov ecx, [ebp+16] ; 4+3) fetch current[i+4]
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add ebx, ecx ; 4+3) result4 = ref[i+4] + current[i+4]
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xor ecx, ecx ; 4+4)
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mov dh, ClampTbl[CLAMP_BIAS+eax-1024] ; 4+2) fetch clamp[result7]
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mov cl, [esi+5] ; 4+4) fetch ref[i+5]
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shl edx, 16 ; move 3rd 2 results to high word
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mov eax, [ebp+20] ; 4+4) fetch current[i+5]
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add ecx, eax ; 4+4) result5 = ref[i+5] + current[i+5]
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add esi, PITCH ; Update address of next line
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mov dl, ClampTbl[CLAMP_BIAS+ebx-1024] ; 4+3) fetch clamp[result4]
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add ebp, TEMPPITCH4 ; Update address of current to next line
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mov dh, ClampTbl[CLAMP_BIAS+ecx-1024] ; 4+4) fetch clamp[result5]
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mov ecx, [L_LOOPCOUNTER] ; get loop counter
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mov [edi+4], edx ; store 4 output pixels
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add edi, PITCH ; Update address of output to next line
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xor eax, eax ; 1)
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dec ecx
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mov ebx, [edi] ; pre-fetch output
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jnz loop_for_i
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add esp,LOCALSIZE // free locals
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pop ebx
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pop edi
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pop esi
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pop ebp
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ret
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} //end of asm
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}
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#pragma code_seg()
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