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546 lines
8.3 KiB
546 lines
8.3 KiB
// TITLE ("Memory Fences, Load Acquires and Store Acquires")
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/*++
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Copyright (c) 1995 Intel Corporation
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Module Name:
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i64ioasm.s assembly routines for read and write I/O
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Abstract:
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This module implements the I/O port access routines.
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Author:
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Bernard Lint, M. Jayakumar 17 Sep '97
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Environment:
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Kernel mode
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Revision History:
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--*/
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#include "ksia64.h"
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#define HAL_RR_PS_VE 0x69
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.file "i64ioasm.s"
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/*++
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VOID
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HalpInsertTranslationRegister (
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IN UINT_PTR IFA,
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IN ULONG SlotNumber,
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IN ULONGLONG Attribute,
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IN ULONGLONG ITIR
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)
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Routine Description:
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This function fills a fixed entry in TR
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N.B. It is assumed that the entry is not in the TB and therefore the TB
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is not probed.
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Arguements:
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(a0) - Supplies the virtual page number to be loaded into IFA.
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(a1) - Supplies the slot number to be used for Translation Register.
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(a2) - Supplies the attribute and portion of the physical address.
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(a3) - Supplies the value to be loaded into ITIR.
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Return Value:
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None.
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--*/
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LEAF_ENTRY(HalpInsertTranslationRegister)
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// Register aliases
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//
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rT1 = t3
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rT2 = t4
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rPKR = t13
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rRR = t15
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//
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// rsm to reset PSR.i bit
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//
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rsm 1 << PSR_I // reset PSR.i bit
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;;
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rsm 1 << PSR_IC // reset PSR.ic bit
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;;
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srlz.d // serialize
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//
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// set RR[0],Region ID (HAL_ RID) = 0x7FFFFF,Page Size (PS) = 8K,
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// VHPT enabled (VE) = 1
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//
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// dep.z rRR= RR_IO_PORT, RR_INDEX, RR_INDEX_LEN
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dep.z rRR = 5, RR_INDEX, RR_INDEX_LEN
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movl rT2 = (0x7FFFFF << RR_RID) | HAL_RR_PS_VE
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;;
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mov rr[rRR] = rT2 // Initialize rr[RR_IOPort]
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// Protection Key Registers
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mov rPKR = PKRNUM // Total number of key registers
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;;
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sub rPKR = rPKR, zero,1 // Choose the last one
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movl rT2 = (0x7FFFFF << RR_RID) | PKR_VALID
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;;
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mov pkr[rPKR] = rT2
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;;
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srlz.i
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mov cr.ifa = a0
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mov cr.itir = a3
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;;
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itr.d dtr[a1] = a2
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ssm 1 << PSR_IC // set PSR.ic bit again
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;;
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srlz.d // serialize
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ssm 1 << PSR_I // set PSR.i bit again
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LEAF_RETURN
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LEAF_EXIT(HalpInsertTranslationRegister)
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/*++
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VOID
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HalpLoadBufferUCHAR (
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PUCHAR VirtualAddress,
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PUCHAR Buffer,
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UCHAR Count
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);
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Routine Description:
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Arguements:
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Return Value:
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--*/
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LEAF_ENTRY(HalpLoadBufferUCHAR)
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.prologue
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.save ar.lc, t22
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mov t22 = ar.lc
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sub a2 = a2,zero,1
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;;
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PROLOGUE_END
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mov ar.lc = a2
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mf
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LoadChar:
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ld1.acq t1 = [a0]
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;;
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st1 [a1] = t1, 1
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br.cloop.dptk.few LoadChar
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;;
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mf.a
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mov ar.lc = t22
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LEAF_RETURN
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LEAF_EXIT (HalpLoadBufferUCHAR)
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/*++
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VOID
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HalpLoadBufferUSHORT (
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PUSHORT VirtualAddress,
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PUSHORT Buffer,
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ULONG Count
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);
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Routine Description:
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Arguements:
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Return Value:
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--*/
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LEAF_ENTRY(HalpLoadBufferUSHORT)
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.prologue
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.save ar.lc, t22
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mov t22 = ar.lc
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sub a2 = a2,zero,1
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;;
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PROLOGUE_END
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mov ar.lc = a2
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mf
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LoadShort:
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ld2.acq t1 = [a0]
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;;
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st2 [a1] = t1, 2
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br.cloop.dptk.few LoadShort
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;;
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mf.a
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mov ar.lc = t22
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LEAF_RETURN
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LEAF_EXIT (HalpLoadBufferUSHORT)
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/*++
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VOID
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HalpLoadBufferULONG (
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PULONG VirtualAddress,
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PULONG Buffer,
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ULONG Count
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);
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Routine Description:
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Arguements:
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Return Value:
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--*/
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LEAF_ENTRY(HalpLoadBufferULONG)
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.prologue
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.save ar.lc, t22
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mov t22 = ar.lc
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sub a2 = a2,zero,1
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;;
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PROLOGUE_END
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mov ar.lc = a2
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mf
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LoadLong:
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ld4.acq t1 = [a0]
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;;
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st4 [a1] = t1, 4
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br.cloop.dptk.few LoadLong
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;;
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mf.a
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mov ar.lc = t22
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LEAF_RETURN
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LEAF_EXIT (HalpLoadBufferULONG)
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/*++
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VOID
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HalpLoadBufferULONGLONG (
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PULONGLONG VirtualAddress,
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PULONGLONG Buffer,
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ULONG Count
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);
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Routine Description:
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Arguements:
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Return Value:
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--*/
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LEAF_ENTRY(HalpLoadBufferULONGLONG)
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.prologue
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.save ar.lc, t22
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mov t22 = ar.lc
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sub a2 = a2,zero,1
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;;
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PROLOGUE_END
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mov ar.lc = a2
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mf
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LoadLongLong:
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ld8.acq t1 = [a0]
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;;
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st8 [a1] = t1, 8
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br.cloop.dptk.few LoadLongLong
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;;
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mf.a
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mov ar.lc = t22
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LEAF_RETURN
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LEAF_EXIT (HalpLoadBufferULONGLONG)
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/*++
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VOID
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HalpStoreBufferUCHAR (
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PUCHAR VirtualAddress,
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PUCHAR Buffer,
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ULONG Count
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);
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Routine Description:
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Arguements:
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Return Value:
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--*/
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LEAF_ENTRY(HalpStoreBufferUCHAR)
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.prologue
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.save ar.lc, t22
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mov t22 = ar.lc
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sub a2 = a2,zero,1
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;;
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PROLOGUE_END
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mov ar.lc = a2
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StoreChar:
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ld1 t1 = [a1], 1
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;;
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st1.rel [a0] = t1
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br.cloop.dptk.few StoreChar
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;;
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mf
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mf.a
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mov ar.lc = t22
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LEAF_RETURN
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LEAF_EXIT (HalpStoreBufferUCHAR)
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/*++
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VOID
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HalpStoreBufferUSHORT (
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PUSHORT VirtualAddress,
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PUSHORT Buffer,
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ULONG Count
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);
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Routine Description:
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Arguements:
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Return Value:
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--*/
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LEAF_ENTRY(HalpStoreBufferUSHORT)
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.prologue
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.save ar.lc, t22
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mov t22 = ar.lc
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sub a2 = a2,zero,1
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;;
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PROLOGUE_END
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mov ar.lc = a2
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StoreShort:
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ld2 t1 = [a1], 2
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;;
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st2.rel [a0] = t1
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br.cloop.dptk.few StoreShort
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;;
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mf
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mf.a
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mov ar.lc = t22
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LEAF_RETURN
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LEAF_EXIT (HalpStoreBufferUSHORT)
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/*++
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VOID
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HalpStoreBufferULONG (
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PULONG VirtualAddress,
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PULONG Buffer,
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ULONG Count
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);
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Routine Description:
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Arguements:
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Return Value:
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--*/
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LEAF_ENTRY(HalpStoreBufferULONG)
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.prologue
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.save ar.lc, t22
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mov t22 = ar.lc
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sub a2 = a2,zero,1
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;;
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PROLOGUE_END
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mov ar.lc = a2
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StoreLong:
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ld4.s t1 = [a1],t0
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;;
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st4.rel [a0] = t1,4
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br.cloop.dptk.few StoreLong
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;;
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mf
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mf.a
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mov ar.lc = t22
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LEAF_RETURN
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LEAF_EXIT (HalpStoreBufferULONG)
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/*++
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VOID
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HalpStoreBufferULONGLONG (
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PULONGLONG VirtualAddress,
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PULONGLONG Buffer,
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ULONG Count
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);
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Routine Description:
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Arguements:
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Return Value:
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--*/
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LEAF_ENTRY(HalpStoreBufferULONGLONG)
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.prologue
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.save ar.lc, t22
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mov t22 = ar.lc
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sub a2 = a2,zero,1
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;;
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PROLOGUE_END
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mov ar.lc = a2
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StoreLongLong:
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ld8.s t1 = [a1],t0
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;;
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st8.rel [a0] = t1, 8
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br.cloop.dptk.few StoreLongLong
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;;
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mf
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mf.a
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mov ar.lc = t22
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LEAF_RETURN
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LEAF_EXIT (HalpStoreBufferULONGLONG)
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//++
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//
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// VOID
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// ReadCpuLid(VOID);
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//
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// Routine Description:
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//
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// This function returns that value of cr.lid for this cpu
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//
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// Arguements:
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//
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// Return Value:
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//
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// LID register contents
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//
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//--
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LEAF_ENTRY(ReadCpuLid)
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mov v0 = cr.lid
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LEAF_RETURN
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LEAF_EXIT(ReadCpuLid)
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