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903 lines
21 KiB
903 lines
21 KiB
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/*++
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Copyright (c) 1996-2000 Microsoft Corporation
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Module Name:
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config.c
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Abstract:
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Two kinds of config space access are allowed. One for the config space
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associated with a specific PDO and one for a device specified in terms of
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a (RootFdo, BusNumber, Slot) tuple.
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Author:
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Andrew Thornton (andrewth) 27-Aug-1998
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Revision History:
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--*/
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#include "pcip.h"
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#define INT_LINE_OFFSET ((ULONG)FIELD_OFFSET(PCI_COMMON_CONFIG,u.type0.InterruptLine))
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//
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// None of these functions are pageable as they are called to power manage
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// devices at high IRQL
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//
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VOID
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PciReadWriteConfigSpace(
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IN PPCI_FDO_EXTENSION ParentFdo,
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IN PCI_SLOT_NUMBER Slot,
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IN PVOID Buffer,
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IN ULONG Offset,
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IN ULONG Length,
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IN BOOLEAN Read
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)
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/*++
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Routine Description:
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This is the base routine through which all config space access from the
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pci driver go.
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Arguments:
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ParentFdo - The FDO of the bus who's config space we want
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Slot - The Device/Function of the device on that bus we are interested in
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Buffer - A buffer where the data will be read or written
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Offset - The byte offset in config space where we should start to read/write
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Length - The number of bytes to read/write
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Read - TRUE to read from config space, FALSE to write
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Return Value:
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None
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Notes:
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If the underlying HAL or ACPI access mechanism failes we bugcheck with a
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PCI_CONFIG_SPACE_ACCESS_FAILURE
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--*/
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{
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PciReadWriteConfig busHandlerReadWrite;
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PCI_READ_WRITE_CONFIG interfaceReadWrite;
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ULONG count;
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PPCI_BUS_INTERFACE_STANDARD busInterface;
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PCI_ASSERT(PCI_IS_ROOT_FDO(ParentFdo->BusRootFdoExtension));
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busInterface = ParentFdo->BusRootFdoExtension->PciBusInterface;
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if (busInterface) {
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//
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// If we have a PCI_BUS_INTERFACE use it to access config space
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//
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if (Read) {
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interfaceReadWrite = busInterface->ReadConfig;
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} else {
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interfaceReadWrite = busInterface->WriteConfig;
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}
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//
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// The interface access to config space is at the root of each PCI
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// domain
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//
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count = interfaceReadWrite(
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busInterface->Context,
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ParentFdo->BaseBus,
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Slot.u.AsULONG,
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Buffer,
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Offset,
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Length
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);
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if (count != Length) {
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KeBugCheckEx(
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PCI_CONFIG_SPACE_ACCESS_FAILURE,
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(ULONG_PTR) ParentFdo->BaseBus, // Bus
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(ULONG_PTR) Slot.u.AsULONG, // Slot
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(ULONG_PTR) Offset, // Offset
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(ULONG_PTR) Read // Read/Write
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);
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}
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} else {
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//
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// The BusHandler interface is at the parent level.
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//
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// NOTE: This means that if hot-plug of bridges (aka Docking) is to be
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// supported then the HAL must provide a PCI_BUS_INTERFACE_STANDARD
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// because it will not have a bus handler for the new bridge so we
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// won't be able to use this code path.
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//
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PCI_ASSERT(ParentFdo->BusHandler);
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//
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// We had better not think we can do hot plug
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//
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PCI_ASSERT(!PciAssignBusNumbers);
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if (Read) {
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busHandlerReadWrite =
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((PPCIBUSDATA)ParentFdo->BusHandler->BusData)->ReadConfig;
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} else {
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busHandlerReadWrite =
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((PPCIBUSDATA)ParentFdo->BusHandler->BusData)->WriteConfig;
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}
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busHandlerReadWrite(ParentFdo->BusHandler,
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Slot,
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Buffer,
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Offset,
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Length
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);
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}
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}
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VOID
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PciReadDeviceConfig(
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IN PPCI_PDO_EXTENSION Pdo,
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IN PVOID Buffer,
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IN ULONG Offset,
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IN ULONG Length
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)
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/*++
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Routine Description:
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Read the config space for a specific device
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Arguments:
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Pdo - The PDO representing the device who's config space we want
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Buffer - A buffer where the data will be read or written
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Offset - The byte offset in config space where we should start to read/write
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Length - The number of bytes to read/write
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Return Value:
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None
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--*/
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{
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PciReadWriteConfigSpace(PCI_PARENT_FDOX(Pdo),
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Pdo->Slot,
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Buffer,
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Offset,
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Length,
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TRUE // read
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);
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}
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VOID
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PciWriteDeviceConfig(
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IN PPCI_PDO_EXTENSION Pdo,
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IN PVOID Buffer,
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IN ULONG Offset,
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IN ULONG Length
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)
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/*++
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Routine Description:
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Write the config space for a specific device
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Arguments:
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Pdo - The PDO representing the device who's config space we want
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Buffer - A buffer where the data will be read or written
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Offset - The byte offset in config space where we should start to read/write
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Length - The number of bytes to read/write
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Return Value:
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None
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--*/
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{
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#if 0
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//
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// Make sure we never change the interrupt line register
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//
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if ((Offset <= INT_LINE_OFFSET)
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&& (Offset + Length > INT_LINE_OFFSET)) {
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PUCHAR interruptLine = (PUCHAR)Buffer + INT_LINE_OFFSET - Offset;
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PCI_ASSERT(*interruptLine == Pdo->RawInterruptLine);
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}
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#endif
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PciReadWriteConfigSpace(PCI_PARENT_FDOX(Pdo),
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Pdo->Slot,
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Buffer,
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Offset,
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Length,
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FALSE // write
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);
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}
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VOID
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PciReadSlotConfig(
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IN PPCI_FDO_EXTENSION ParentFdo,
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IN PCI_SLOT_NUMBER Slot,
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IN PVOID Buffer,
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IN ULONG Offset,
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IN ULONG Length
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)
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/*++
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Routine Description:
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Read config space for a specific bus/slot
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Arguments:
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ParentFdo - The FDO of the bus who's config space we want
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Slot - The Device/Function of the device on that bus we are interested in
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Buffer - A buffer where the data will be read or written
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Offset - The byte offset in config space where we should start to read/write
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Length - The number of bytes to read/write
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Return Value:
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None
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--*/
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{
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PciReadWriteConfigSpace(ParentFdo,
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Slot,
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Buffer,
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Offset,
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Length,
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TRUE // read
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);
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}
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VOID
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PciWriteSlotConfig(
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IN PPCI_FDO_EXTENSION ParentFdo,
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IN PCI_SLOT_NUMBER Slot,
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IN PVOID Buffer,
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IN ULONG Offset,
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IN ULONG Length
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)
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/*++
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Routine Description:
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Read config space for a specific bus/slot
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Arguments:
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ParentFdo - The FDO of the bus who's config space we want
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Slot - The Device/Function of the device on that bus we are interested in
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Buffer - A buffer where the data will be read or written
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Offset - The byte offset in config space where we should start to read/write
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Length - The number of bytes to read/write
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Return Value:
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None
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--*/
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{
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PciReadWriteConfigSpace(ParentFdo,
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Slot,
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Buffer,
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Offset,
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Length,
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FALSE // write
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);
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}
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UCHAR
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PciGetAdjustedInterruptLine(
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IN PPCI_PDO_EXTENSION Pdo
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)
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/*++
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Routine Description:
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This updates the interrupt line the HAL would like the world to see - this
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may or may not be different than the raw pin.
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Arguments:
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Pdo - The PDO representing the device who's config space we want
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Buffer - A buffer where the data will be read or written
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Offset - The byte offset in config space where we should start to read/write
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Length - The number of bytes to read/write
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Return Value:
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None
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--*/
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{
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UCHAR adjustedInterruptLine = 0;
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ULONG lengthRead;
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//
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// Just in case anyone messes up the structures
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//
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PCI_ASSERT(INT_LINE_OFFSET
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== (ULONG)FIELD_OFFSET(PCI_COMMON_CONFIG, u.type1.InterruptLine));
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PCI_ASSERT(INT_LINE_OFFSET
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== (ULONG)FIELD_OFFSET(PCI_COMMON_CONFIG, u.type2.InterruptLine));
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if (Pdo->InterruptPin != 0) {
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//
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// Get the adjusted line the HAL wants us to see
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//
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lengthRead = HalGetBusDataByOffset(
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PCIConfiguration,
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PCI_PARENT_FDOX(Pdo)->BaseBus,
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Pdo->Slot.u.AsULONG,
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&adjustedInterruptLine,
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INT_LINE_OFFSET,
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sizeof(adjustedInterruptLine));
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if (lengthRead != sizeof(adjustedInterruptLine)) {
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adjustedInterruptLine = Pdo->RawInterruptLine;
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}
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}
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return adjustedInterruptLine;
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}
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NTSTATUS
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PciQueryForPciBusInterface(
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IN PPCI_FDO_EXTENSION FdoExtension
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)
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/*++
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Routine Description:
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This routine sends an IRP to the parent PDO requesting
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handlers for PCI configuration reads and writes.
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Arguments:
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FdoExtension - this PCI bus's FDO extension
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Return Value:
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STATUS_SUCCESS, if the PDO provided handlers
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Notes:
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--*/
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{
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NTSTATUS status;
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PPCI_BUS_INTERFACE_STANDARD interface;
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PDEVICE_OBJECT targetDevice = NULL;
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KEVENT irpCompleted;
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IO_STATUS_BLOCK statusBlock;
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PIRP irp = NULL;
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PIO_STACK_LOCATION irpStack;
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PAGED_CODE();
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//
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// We only do this for root busses
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//
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PCI_ASSERT(PCI_IS_ROOT_FDO(FdoExtension));
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interface = ExAllocatePool(NonPagedPool, sizeof(PCI_BUS_INTERFACE_STANDARD));
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if (!interface) {
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return STATUS_INSUFFICIENT_RESOURCES;
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}
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//
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// Find out where we are sending the irp
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//
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targetDevice = IoGetAttachedDeviceReference(FdoExtension->PhysicalDeviceObject);
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//
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// Get an IRP
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//
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KeInitializeEvent(&irpCompleted, SynchronizationEvent, FALSE);
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irp = IoBuildSynchronousFsdRequest(IRP_MJ_PNP,
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targetDevice,
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NULL, // Buffer
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0, // Length
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0, // StartingOffset
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&irpCompleted,
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&statusBlock
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);
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if (!irp) {
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status = STATUS_INSUFFICIENT_RESOURCES;
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goto cleanup;
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}
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irp->IoStatus.Status = STATUS_NOT_SUPPORTED;
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irp->IoStatus.Information = 0;
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//
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// Initialize the stack location
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//
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irpStack = IoGetNextIrpStackLocation(irp);
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PCI_ASSERT(irpStack->MajorFunction == IRP_MJ_PNP);
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irpStack->MinorFunction = IRP_MN_QUERY_INTERFACE;
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irpStack->Parameters.QueryInterface.InterfaceType = (PGUID) &GUID_PCI_BUS_INTERFACE_STANDARD;
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irpStack->Parameters.QueryInterface.Version = PCI_BUS_INTERFACE_STANDARD_VERSION;
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irpStack->Parameters.QueryInterface.Size = sizeof (PCI_BUS_INTERFACE_STANDARD);
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irpStack->Parameters.QueryInterface.Interface = (PINTERFACE) interface;
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irpStack->Parameters.QueryInterface.InterfaceSpecificData = NULL;
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//
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// Call the driver and wait for completion
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//
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status = IoCallDriver(targetDevice, irp);
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if (status == STATUS_PENDING) {
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KeWaitForSingleObject(&irpCompleted, Executive, KernelMode, FALSE, NULL);
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status = statusBlock.Status;
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}
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if (NT_SUCCESS(status)) {
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FdoExtension->PciBusInterface = interface;
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//
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// The interface is already referenced when we get it so we don't need
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// to reference it again.
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//
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} else {
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//
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// We don't have an interface
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//
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FdoExtension->PciBusInterface = NULL;
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ExFreePool(interface);
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}
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//
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// Ok we're done with this stack
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//
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ObDereferenceObject(targetDevice);
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return status;
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cleanup:
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if (targetDevice) {
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ObDereferenceObject(targetDevice);
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}
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if (interface) {
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ExFreePool(interface);
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}
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return status;
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}
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NTSTATUS
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PciGetConfigHandlers(
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IN PPCI_FDO_EXTENSION FdoExtension
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)
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/*++
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Routine Description:
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This routine attempts to get pnp style config handlers from the PCI busses
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enumerator and if they are not provided falls back on using the HAL bus
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handler method.
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Arguments:
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FdoExtension - this PCI bus's FDO extension
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Return Value:
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STATUS_SUCCESS, if the PDO provided handlers
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Notes:
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--*/
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{
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NTSTATUS status;
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PCI_ASSERT(FdoExtension->BusHandler == NULL);
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//
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// Check if this is a root bus
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//
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if (PCI_IS_ROOT_FDO(FdoExtension)) {
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PCI_ASSERT(FdoExtension->PciBusInterface == NULL);
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//
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// Check to see if our parent is offering
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// functions for reading and writing config space.
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//
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status = PciQueryForPciBusInterface(FdoExtension);
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if (NT_SUCCESS(status)) {
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//
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// If we have an interface we support numbering of busses
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//
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PciAssignBusNumbers = TRUE;
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} else {
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//
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// We better not think we can number busses - we should only ever
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// get here if one root provides an interface and the other does not
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//
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PCI_ASSERT(!PciAssignBusNumbers);
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}
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} else {
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//
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// Check if our root has a PciBusInterface - which it got from above
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//
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if (FdoExtension->BusRootFdoExtension->PciBusInterface) {
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return STATUS_SUCCESS;
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} else {
|
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//
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// Set status so we get a bus handler for this bus
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//
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status = STATUS_NOT_SUPPORTED;
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}
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}
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if (!NT_SUCCESS(status)) {
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PCI_ASSERT(status == STATUS_NOT_SUPPORTED);
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|
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//
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// Make sure we arn't trying to get a bus handler for a hot plug
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// capable machine
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//
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PCI_ASSERT(!PciAssignBusNumbers);
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|
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//
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// We couldn't find config handlers the PnP way,
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// build them from the HAL bus handlers.
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//
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FdoExtension->BusHandler =
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HalReferenceHandlerForBus(PCIBus, FdoExtension->BaseBus);
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if (!FdoExtension->BusHandler) {
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//
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// This must be a bus that arrived hot. We only support hot anything
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// on ACPI machines and they should have provided a PCI_BUS interface
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// at the root. Fail the add for this new bus.
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//
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return STATUS_INVALID_DEVICE_REQUEST; // better code?
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}
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}
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return STATUS_SUCCESS;
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}
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|
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|
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NTSTATUS
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PciExternalReadDeviceConfig(
|
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IN PPCI_PDO_EXTENSION Pdo,
|
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IN PVOID Buffer,
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IN ULONG Offset,
|
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IN ULONG Length
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)
|
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/*++
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|
Routine Description:
|
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Called when agents outside the PCI driver want to access config space
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(either from a READ_CONFIG IRP or through BUS_INTERFACE_STANDARD).
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This function performs extra sanity checks and sanitization on the
|
|
arguments and also double buffers the data as Buffer might be
|
|
pageable and we access config space at high IRQL.
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Arguments:
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Pdo - The PDO representing the device who's config space we want
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Buffer - A buffer where the data will be read or written
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Offset - The byte offset in config space where we should start to read/write
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Length - The number of bytes to read/write
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Return Value:
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None
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--*/
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{
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UCHAR doubleBuffer[sizeof(PCI_COMMON_CONFIG)];
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//
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// Validate the request
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//
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if ((Length + Offset) > sizeof(PCI_COMMON_CONFIG)) {
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return STATUS_INVALID_DEVICE_REQUEST;
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}
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//
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// Read the data into a buffer allocated on the stack with
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// is guaranteed to not be paged as we access config space
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// at > DISPATCH_LEVEL and the DDK says that the buffer
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// *should* be in paged pool.
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//
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PciReadDeviceConfig(Pdo, &doubleBuffer[Offset], Offset, Length);
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|
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//
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// If we are reading the interrupt line register then adjust it.
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//
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if ((Pdo->InterruptPin != 0) &&
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(Offset <= INT_LINE_OFFSET) &&
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(Offset + Length > INT_LINE_OFFSET)) {
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doubleBuffer[INT_LINE_OFFSET] = Pdo->AdjustedInterruptLine;
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}
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RtlCopyMemory(Buffer, &doubleBuffer[Offset], Length);
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return STATUS_SUCCESS;
|
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}
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|
|
|
|
|
NTSTATUS
|
|
PciExternalWriteDeviceConfig(
|
|
IN PPCI_PDO_EXTENSION Pdo,
|
|
IN PVOID Buffer,
|
|
IN ULONG Offset,
|
|
IN ULONG Length
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
Called when agents outside the PCI driver want to access config space
|
|
(either from a WRITE_CONFIG IRP or through BUS_INTERFACE_STANDARD).
|
|
|
|
This function performs extra sanity checks and sanitization on the
|
|
arguments and also double buffers the data as Buffer might be
|
|
pageable and we access config space at high IRQL.
|
|
|
|
Arguments:
|
|
|
|
Pdo - The PDO representing the device who's config space we want
|
|
|
|
Buffer - A buffer where the data will be read or written
|
|
|
|
Offset - The byte offset in config space where we should start to read/write
|
|
|
|
Length - The number of bytes to read/write
|
|
|
|
Return Value:
|
|
|
|
None
|
|
|
|
--*/
|
|
|
|
{
|
|
PUCHAR interruptLine;
|
|
UCHAR doubleBuffer[255];
|
|
BOOLEAN illegalAccess = FALSE;
|
|
PVERIFIER_DATA verifierData;
|
|
|
|
//
|
|
// Validate the request
|
|
//
|
|
|
|
if ((Length + Offset) > sizeof(PCI_COMMON_CONFIG)) {
|
|
return STATUS_INVALID_DEVICE_REQUEST;
|
|
}
|
|
|
|
//
|
|
// Make sure they are not touching registers they should not be. For
|
|
// backward compatiblity we will just complain and let the request through.
|
|
//
|
|
|
|
switch (Pdo->HeaderType) {
|
|
case PCI_DEVICE_TYPE:
|
|
|
|
//
|
|
// They should not be writing to their BARS including the ROM BAR
|
|
//
|
|
if (INTERSECT_CONFIG_FIELD(Offset, Length, u.type0.BaseAddresses)
|
|
|| INTERSECT_CONFIG_FIELD(Offset, Length, u.type0.ROMBaseAddress)) {
|
|
illegalAccess = TRUE;
|
|
}
|
|
break;
|
|
|
|
case PCI_BRIDGE_TYPE:
|
|
//
|
|
// For bridges they should not touch the bars, the base and limit registers,
|
|
// the bus numbers or bridge control
|
|
//
|
|
if (INTERSECT_CONFIG_FIELD_RANGE(Offset, Length, u.type1.BaseAddresses, u.type1.SubordinateBus)
|
|
|| INTERSECT_CONFIG_FIELD_RANGE(Offset, Length, u.type1.IOBase, u.type1.IOLimit)
|
|
|| INTERSECT_CONFIG_FIELD_RANGE(Offset, Length, u.type1.MemoryBase, u.type1.IOLimitUpper16)
|
|
|| INTERSECT_CONFIG_FIELD(Offset, Length, u.type1.ROMBaseAddress)) {
|
|
illegalAccess = TRUE;
|
|
}
|
|
break;
|
|
|
|
case PCI_CARDBUS_BRIDGE_TYPE:
|
|
|
|
//
|
|
// For bridges they should not touch the bars, the base and limit registers
|
|
// or the bus numbers. Bridge control is modified by PCICIA to control cardbus
|
|
// IRQ routing so must be ok.
|
|
//
|
|
if (INTERSECT_CONFIG_FIELD(Offset, Length, u.type2.SocketRegistersBaseAddress)
|
|
|| INTERSECT_CONFIG_FIELD_RANGE(Offset, Length, u.type2.PrimaryBus, u.type2.SubordinateBus)
|
|
|| INTERSECT_CONFIG_FIELD(Offset, Length, u.type2.Range)) {
|
|
illegalAccess = TRUE;
|
|
}
|
|
break;
|
|
}
|
|
|
|
if (illegalAccess) {
|
|
|
|
verifierData = PciVerifierRetrieveFailureData(
|
|
PCI_VERIFIER_PROTECTED_CONFIGSPACE_ACCESS
|
|
);
|
|
|
|
PCI_ASSERT(verifierData);
|
|
|
|
//
|
|
// We fail the devnode instead of the driver because we don't actually
|
|
// have an address to pass to the driver verifier.
|
|
//
|
|
VfFailDeviceNode(
|
|
Pdo->PhysicalDeviceObject,
|
|
PCI_VERIFIER_DETECTED_VIOLATION,
|
|
PCI_VERIFIER_PROTECTED_CONFIGSPACE_ACCESS,
|
|
verifierData->FailureClass,
|
|
&verifierData->Flags,
|
|
verifierData->FailureText,
|
|
"%DevObj%Ulong%Ulong",
|
|
Pdo->PhysicalDeviceObject,
|
|
Offset,
|
|
Length
|
|
);
|
|
}
|
|
|
|
|
|
//
|
|
// Copy the data into a buffer allocated on the stack with
|
|
// is guaranteed to not be paged as we access config space
|
|
// at > DISPATCH_LEVEL and the DDK says that the buffer
|
|
// *should* be in paged pool.
|
|
//
|
|
|
|
RtlCopyMemory(doubleBuffer, Buffer, Length);
|
|
|
|
//
|
|
// If we are writing the interrupt line register then adjust it so we write
|
|
// the raw value back again
|
|
//
|
|
|
|
if ((Pdo->InterruptPin != 0) &&
|
|
(Offset <= INT_LINE_OFFSET) &&
|
|
(Offset + Length > INT_LINE_OFFSET)) {
|
|
|
|
interruptLine = (PUCHAR)doubleBuffer + INT_LINE_OFFSET - Offset;
|
|
|
|
//
|
|
// Adjust the interrupt line with what the HAL wants us to see
|
|
//
|
|
|
|
*interruptLine = Pdo->RawInterruptLine;
|
|
|
|
}
|
|
|
|
PciWriteDeviceConfig(Pdo, doubleBuffer, Offset, Length);
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
|