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951 lines
26 KiB
951 lines
26 KiB
/*++
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Copyright (c) 1989 Microsoft Corporation
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Module Name:
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ixpciint.c
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Abstract:
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All PCI bus interrupt mapping is in this module, so that a real
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system which doesn't have all the limitations which PC PCI
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systems have can replaced this code easly.
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(bus memory & i/o address mappings can also be fix here)
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Author:
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Ken Reneris
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Environment:
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Kernel mode
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Revision History:
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--*/
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#include "halp.h"
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#include "pci.h"
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#include "pcip.h"
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#include "pcmp_nt.inc"
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volatile ULONG PCIType2Stall;
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extern struct HalpMpInfo HalpMpInfoTable;
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extern BOOLEAN HalpHackNoPciMotion;
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extern BOOLEAN HalpDoingCrashDump;
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VOID
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HalpPCIPin2MPSLine (
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PCI_SLOT_NUMBER SlotNumber,
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IN PPCI_COMMON_CONFIG PciData
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);
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VOID
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HalpPCIBridgedPin2Line (
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PCI_SLOT_NUMBER SlotNumber,
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IN PPCI_COMMON_CONFIG PciData
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);
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VOID
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HalpPCIMPSLine2Pin (
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PCI_SLOT_NUMBER SlotNumber,
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IN PPCI_COMMON_CONFIG PciNewData,
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IN PPCI_COMMON_CONFIG PciOldData
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);
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NTSTATUS
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HalpGetFixedPCIMPSLine (
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PCI_SLOT_NUMBER PciSlot,
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OUT PSUPPORTED_RANGE *Interrupt
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);
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BOOLEAN
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HalpMPSBusId2NtBusId (
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IN UCHAR ApicBusId,
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OUT PPCMPBUSTRANS *ppBusType,
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OUT PULONG BusNo
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);
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ULONG
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HalpGetPCIBridgedInterruptVector (
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN ULONG InterruptLevel,
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IN ULONG InterruptVector,
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OUT PKIRQL Irql,
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OUT PKAFFINITY Affinity
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);
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#ifdef ALLOC_PRAGMA
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#pragma alloc_text(INIT, HalpSubclassPCISupport)
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#pragma alloc_text(INIT, HalpMPSPCIChildren)
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#pragma alloc_text(PAGE, HalpGetFixedPCIMPSLine)
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#pragma alloc_text(PAGE, HalpGetPCIBridgedInterruptVector)
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#pragma alloc_text(PAGE, HalpIrqTranslateRequirementsPci)
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#pragma alloc_text(PAGE, HalpIrqTranslateResourcesPci)
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#endif
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//
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// Turn PCI pin to inti via the MPS spec
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// (note: pin must be non-zero)
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//
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#define PCIPin2Int(Slot,Pin) \
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((((Slot.u.bits.DeviceNumber << 2) | (Pin-1)) != 0) ? \
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(Slot.u.bits.DeviceNumber << 2) | (Pin-1) : 0x80);
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#define PCIInt2Pin(interrupt) \
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((interrupt & 0x3) + 1)
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#define PCIInt2Slot(interrupt) \
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((interrupt & 0x7f) >> 2)
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VOID
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HalpSubclassPCISupport (
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PBUS_HANDLER Handler,
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ULONG HwType
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)
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{
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ULONG d, pin, i, MaxDeviceFound;
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PPCIPBUSDATA BusData;
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PCI_SLOT_NUMBER SlotNumber;
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BOOLEAN DeviceFound;
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BusData = (PPCIPBUSDATA) Handler->BusData;
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SlotNumber.u.bits.Reserved = 0;
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MaxDeviceFound = 0;
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DeviceFound = FALSE;
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#ifdef P6_WORKAROUNDS
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BusData->MaxDevice = 0x10;
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#endif
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//
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// Find any PCI bus which has MPS inti information, and provide
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// MPS handlers for dealing with it.
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//
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// Note: we assume that any PCI bus with any MPS information
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// is totally defined. (Ie, it's not possible to connect some PCI
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// interrupts on a given PCI bus via the MPS table without connecting
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// them all).
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//
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// Note2: we assume that PCI buses are listed in the MPS table in
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// the same order the BUS declares them. (Ie, the first listed
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// PCI bus in the MPS table is assumed to match physical PCI bus 0, etc).
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//
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//
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for (d=0; d < PCI_MAX_DEVICES; d++) {
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SlotNumber.u.bits.DeviceNumber = d;
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SlotNumber.u.bits.FunctionNumber = 0;
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for (pin=1; pin <= 4; pin++) {
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i = PCIPin2Int (SlotNumber, pin);
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if (HalpGetApicInterruptDesc(PCIBus, Handler->BusNumber, i, (PUSHORT)&i)) {
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MaxDeviceFound = d;
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DeviceFound = TRUE;
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}
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}
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}
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if (DeviceFound) {
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//
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// There are Inti mapping for interrupts on this PCI bus
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// Change handlers for this bus to MPS versions
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//
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Handler->GetInterruptVector = HalpGetSystemInterruptVector;
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BusData->CommonData.Pin2Line = (PciPin2Line) HalpPCIPin2MPSLine;
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BusData->CommonData.Line2Pin = (PciLine2Pin) HalpPCIMPSLine2Pin;
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BusData->GetIrqRange = HalpGetFixedPCIMPSLine;
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if (BusData->MaxDevice < MaxDeviceFound) {
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BusData->MaxDevice = MaxDeviceFound;
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}
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} else {
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//
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// Not all PCI machines are eisa machine, since the PCI interrupts
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// aren't coming into IoApics go check the Eisa ELCR for broken
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// behaviour.
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//
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HalpCheckELCR ();
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}
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}
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VOID
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HalpMPSPCIChildren (
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VOID
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)
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/*++
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Any PCI buses which don't have declared interrupt mappings and
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are children of parent buses that have MPS interrupt mappings
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need to inherit interrupts from parents via PCI barbar pole
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algorithm
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--*/
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{
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PBUS_HANDLER Handler, Parent;
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PPCIPBUSDATA BusData, ParentData;
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ULONG b, cnt, i, id;
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PCI_SLOT_NUMBER SlotNumber;
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struct {
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union {
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UCHAR map[4];
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ULONG all;
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} u;
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} Interrupt, Hold;
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//
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// Lookup each PCI bus in the system
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//
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for (b=0; Handler = HaliHandlerForBus(PCIBus, b); b++) {
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BusData = (PPCIPBUSDATA) Handler->BusData;
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if (BusData->CommonData.Pin2Line == (PciPin2Line) HalpPCIPin2MPSLine) {
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//
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// This bus already has mappings
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//
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continue;
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}
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//
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// Check if any parent has PCI MPS interrupt mappings
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//
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Interrupt.u.map[0] = 1;
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Interrupt.u.map[1] = 2;
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Interrupt.u.map[2] = 3;
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Interrupt.u.map[3] = 4;
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Parent = Handler;
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SlotNumber = BusData->CommonData.ParentSlot;
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while (Parent = Parent->ParentHandler) {
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if (Parent->InterfaceType != PCIBus) {
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break;
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}
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//
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// Check if parent has MPS interrupt mappings
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//
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ParentData = (PPCIPBUSDATA) Parent->BusData;
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if (ParentData->CommonData.Pin2Line == (PciPin2Line) HalpPCIPin2MPSLine) {
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//
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// This parent has MPS interrupt mappings. Set the device
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// to get its InterruptLine values from the buses SwizzleIn table
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//
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Handler->GetInterruptVector = HalpGetPCIBridgedInterruptVector;
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BusData->CommonData.Pin2Line = (PciPin2Line) HalpPCIBridgedPin2Line;
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BusData->CommonData.Line2Pin = (PciLine2Pin) HalpPCIMPSLine2Pin;
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for (i=0; i < 4; i++) {
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id = PCIPin2Int (SlotNumber, Interrupt.u.map[i]);
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BusData->SwizzleIn[i] = (UCHAR) id;
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}
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break;
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}
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//
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// Apply interrupt mapping
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//
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i = SlotNumber.u.bits.DeviceNumber;
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Hold.u.map[0] = Interrupt.u.map[(i + 0) & 3];
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Hold.u.map[1] = Interrupt.u.map[(i + 1) & 3];
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Hold.u.map[2] = Interrupt.u.map[(i + 2) & 3];
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Hold.u.map[3] = Interrupt.u.map[(i + 3) & 3];
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Interrupt.u.all = Hold.u.all;
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SlotNumber = ParentData->CommonData.ParentSlot;
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}
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}
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}
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VOID
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HalpPCIPin2MPSLine (
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PCI_SLOT_NUMBER SlotNumber,
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IN PPCI_COMMON_CONFIG PciData
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)
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/*++
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--*/
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{
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if (!PciData->u.type0.InterruptPin) {
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return ;
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}
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PciData->u.type0.InterruptLine = (UCHAR)
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PCIPin2Int (SlotNumber, PciData->u.type0.InterruptPin);
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}
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VOID
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HalpPCIBridgedPin2Line (
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PCI_SLOT_NUMBER SlotNumber,
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IN PPCI_COMMON_CONFIG PciData
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)
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/*++
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This function maps the device's InterruptPin to an InterruptLine
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value.
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test function particular to dec pci-pci bridge card
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--*/
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{
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PPCIPBUSDATA BusData;
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ULONG i;
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if (!PciData->u.type0.InterruptPin) {
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return ;
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}
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//
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// Convert slot Pin into Bus INTA-D.
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//
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BusData = (PPCIPBUSDATA) BusHandler->BusData;
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i = (PciData->u.type0.InterruptPin +
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SlotNumber.u.bits.DeviceNumber - 1) & 3;
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PciData->u.type0.InterruptLine = BusData->SwizzleIn[i];
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}
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VOID
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HalpPCIMPSLine2Pin (
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PCI_SLOT_NUMBER SlotNumber,
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IN PPCI_COMMON_CONFIG PciNewData,
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IN PPCI_COMMON_CONFIG PciOldData
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)
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/*++
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--*/
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{
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//
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// PCI interrupts described in the MPS table are directly
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// connected to APIC Inti pins.
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// Do nothing...
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//
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}
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ULONG
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HalpGetPCIBridgedInterruptVector (
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN ULONG InterruptLevel,
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IN ULONG InterruptVector,
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OUT PKIRQL Irql,
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OUT PKAFFINITY Affinity
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)
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{
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//
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// Get parent's translation
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//
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return BusHandler->ParentHandler->GetInterruptVector (
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BusHandler->ParentHandler,
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BusHandler->ParentHandler,
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InterruptLevel,
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InterruptVector,
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Irql,
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Affinity
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);
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}
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NTSTATUS
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HalpGetFixedPCIMPSLine (
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PCI_SLOT_NUMBER PciSlot,
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OUT PSUPPORTED_RANGE *Interrupt
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)
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{
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UCHAR buffer[PCI_COMMON_HDR_LENGTH];
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PPCI_COMMON_CONFIG PciData;
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PciData = (PPCI_COMMON_CONFIG) buffer;
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HalGetBusData (
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PCIConfiguration,
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BusHandler->BusNumber,
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PciSlot.u.AsULONG,
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PciData,
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PCI_COMMON_HDR_LENGTH
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);
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if (PciData->VendorID == PCI_INVALID_VENDORID) {
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return STATUS_UNSUCCESSFUL;
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}
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*Interrupt = ExAllocatePoolWithTag(PagedPool,
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sizeof(SUPPORTED_RANGE),
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HAL_POOL_TAG);
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if (!*Interrupt) {
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return STATUS_INSUFFICIENT_RESOURCES;
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}
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RtlZeroMemory (*Interrupt, sizeof (SUPPORTED_RANGE));
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(*Interrupt)->Base = 1; // base = 1, limit = 0
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if (!PciData->u.type0.InterruptPin) {
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return STATUS_SUCCESS;
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}
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(*Interrupt)->Base = PciData->u.type0.InterruptLine;
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(*Interrupt)->Limit = PciData->u.type0.InterruptLine;
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return STATUS_SUCCESS;
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}
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VOID
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HalpPCIType2TruelyBogus (
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ULONG Context
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)
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/*++
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This is a piece of work.
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Type 2 of the PCI configuration space is bad. Bad as in to
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access it one needs to block out 4K of I/O space.
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Video cards are bad. The only decode the bits in an I/O address
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they feel like. Which means one can't block out a 4K range
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or these video cards don't work.
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Combinding all these bad things onto an MP machine is even
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more (sic) bad. The I/O ports can't be mapped out unless
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all processors stop accessing I/O space.
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Allowing access to device specific PCI control space during
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an interrupt isn't bad, (although accessing it on every interrupt
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is ineficent) but this cause the added grief that all processors
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need to obtained at above all device interrupts.
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And... naturally we have an MP machine with a wired down
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bad video controller, stuck in the bad Type 2 configuration
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space (when we told everyone about type 1!). So the "fix"
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is to HALT ALL processors for the duration of reading/writing
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ANY part of PCI configuration space such that we can be sure
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no processor is touching the 4k I/O ports which get mapped out
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of existance when type2 accesses occur.
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----
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While I'm flaming. Hooking PCI interrupts ontop of ISA interrupts
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in a machine which has the potential to have 240+ interrupts
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sources (read APIC) is bad.
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--*/
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{
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// oh - let's just wait here and not pay attention to that other processor
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// guy whom is punching holes into the I/O space
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while (PCIType2Stall == Context) {
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HalpPollForBroadcast ();
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}
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}
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VOID
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HalpPCIAcquireType2Lock (
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PKSPIN_LOCK SpinLock,
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PKIRQL OldIrql
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)
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{
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if (!HalpDoingCrashDump) {
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*OldIrql = KfRaiseIrql (CLOCK2_LEVEL-1);
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KiAcquireSpinLock (SpinLock);
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//
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// Interrupt all other processors and have them wait until the
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// barrier is cleared. (HalpGenericCall waits until the target
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// processors have been interrupted before returning)
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//
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HalpGenericCall (
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HalpPCIType2TruelyBogus,
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PCIType2Stall,
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HalpActiveProcessors & ~KeGetCurrentPrcb()->SetMember
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);
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} else {
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*OldIrql = HIGH_LEVEL;
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}
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}
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VOID
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HalpPCIReleaseType2Lock (
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PKSPIN_LOCK SpinLock,
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KIRQL Irql
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)
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{
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if (!HalpDoingCrashDump) {
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PCIType2Stall++; // clear barrier
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KiReleaseSpinLock (SpinLock);
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KfLowerIrql (Irql);
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}
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}
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NTSTATUS
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HalpIrqTranslateRequirementsPci(
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IN PVOID Context,
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IN PIO_RESOURCE_DESCRIPTOR Source,
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IN PDEVICE_OBJECT PhysicalDeviceObject,
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OUT PULONG TargetCount,
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OUT PIO_RESOURCE_DESCRIPTOR *Target
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)
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/*++
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Routine Description:
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This function translates IRQ resource requirements from
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a PCI bus that is described in the MPS table to the
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root.
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Arguments:
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Context - must hold the MPS bus number of this PCI bus
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Return Value:
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STATUS_SUCCESS, so long as we can allocate the necessary
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memory
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--*/
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#define USE_INT_LINE_REGISTER_TOKEN 0xffffffff
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{
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PIO_RESOURCE_DESCRIPTOR target;
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PPCMPBUSTRANS busType;
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PBUS_HANDLER busHandler;
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NTSTATUS status;
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UCHAR mpsBusNumber;
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ULONG devPciBus, bridgePciBus;
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PCI_SLOT_NUMBER pciSlot;
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UCHAR interruptLine, interruptPin;
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UCHAR dummy;
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PDEVICE_OBJECT parentPdo;
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ROUTING_TOKEN routingToken;
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KIRQL irql;
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KAFFINITY affinity;
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ULONG busVector;
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ULONG vector;
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BOOLEAN success;
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PAGED_CODE();
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ASSERT(Source->Type == CmResourceTypeInterrupt);
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ASSERT(PciIrqRoutingInterface.GetInterruptRouting);
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devPciBus = (ULONG)-1;
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pciSlot.u.AsULONG = (ULONG)-1;
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status = PciIrqRoutingInterface.GetInterruptRouting(
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PhysicalDeviceObject,
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&devPciBus,
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&pciSlot.u.AsULONG,
|
|
&interruptLine,
|
|
&interruptPin,
|
|
&dummy,
|
|
&dummy,
|
|
&parentPdo,
|
|
&routingToken,
|
|
&dummy
|
|
);
|
|
|
|
if (!NT_SUCCESS(status)) {
|
|
|
|
//
|
|
// We should never get here. If we do, we have a bug.
|
|
// It means that we're trying to arbitrate PCI IRQs for
|
|
// a non-PCI device.
|
|
//
|
|
|
|
#if DBG
|
|
DbgPrint("HAL: The PnP manager passed a non-PCI PDO to the PCI IRQ translator (%x)\n",
|
|
PhysicalDeviceObject);
|
|
#endif
|
|
*TargetCount = 0;
|
|
return STATUS_INVALID_PARAMETER_3;
|
|
}
|
|
|
|
target = ExAllocatePoolWithTag(PagedPool,
|
|
sizeof(IO_RESOURCE_DESCRIPTOR),
|
|
HAL_POOL_TAG);
|
|
|
|
if (!target) {
|
|
return STATUS_INSUFFICIENT_RESOURCES;
|
|
}
|
|
|
|
//
|
|
// Copy the source to fill in all the relevant fields.
|
|
//
|
|
|
|
*target = *Source;
|
|
|
|
if (Context == (PVOID)USE_INT_LINE_REGISTER_TOKEN) {
|
|
|
|
//
|
|
// This bus's vectors aren't described in
|
|
// the MPS table. So just use the Int Line
|
|
// register.
|
|
//
|
|
|
|
busVector = interruptLine;
|
|
|
|
busHandler = HaliHandlerForBus(Isa, 0);
|
|
|
|
} else {
|
|
|
|
mpsBusNumber = (UCHAR)Context;
|
|
success = HalpMPSBusId2NtBusId(mpsBusNumber,
|
|
&busType,
|
|
&bridgePciBus);
|
|
|
|
if (!success) {
|
|
ExFreePool(target);
|
|
return STATUS_UNSUCCESSFUL;
|
|
}
|
|
|
|
//
|
|
// Start with the assumption that the incoming
|
|
// resources will contain the proper MPS-style
|
|
// interrupt vector. This will be guaranteed
|
|
// to be true if some previous translation has
|
|
// been done on these resources. And it might
|
|
// be true otherwise.
|
|
//
|
|
|
|
busVector = Source->u.Interrupt.MinimumVector;
|
|
|
|
if (bridgePciBus == devPciBus) {
|
|
|
|
//
|
|
// If this device sits on the bus for which
|
|
// this translator has been ejected, we can
|
|
// do better than to assume the incoming
|
|
// resources are clever.
|
|
//
|
|
|
|
busVector = PCIPin2Int(pciSlot, interruptPin);
|
|
}
|
|
|
|
//
|
|
// Find the PCI bus that corresponds to this MPS bus.
|
|
//
|
|
|
|
ASSERT(busType->NtType == PCIBus);
|
|
|
|
//
|
|
// TEMPTEMP Use bus handlers for now.
|
|
//
|
|
|
|
busHandler = HaliHandlerForBus(PCIBus, devPciBus);
|
|
|
|
}
|
|
|
|
|
|
vector = busHandler->GetInterruptVector(busHandler,
|
|
busHandler,
|
|
busVector,
|
|
busVector,
|
|
&irql,
|
|
&affinity);
|
|
|
|
if (vector == 0) {
|
|
|
|
#if DBG
|
|
DbgPrint("\nHAL: PCI Device 0x%02x, Func. 0x%x on bus 0x%x is not in the MPS table.\n *** Note to WHQL: Fail this machine. ***\n\n",
|
|
pciSlot.u.bits.DeviceNumber,
|
|
pciSlot.u.bits.FunctionNumber,
|
|
devPciBus);
|
|
#endif
|
|
ExFreePool(target);
|
|
*TargetCount = 0;
|
|
|
|
return STATUS_PNP_BAD_MPS_TABLE;
|
|
|
|
} else {
|
|
|
|
target->u.Interrupt.MinimumVector = vector;
|
|
target->u.Interrupt.MaximumVector = vector;
|
|
|
|
*TargetCount = 1;
|
|
*Target = target;
|
|
}
|
|
|
|
return STATUS_TRANSLATION_COMPLETE;
|
|
}
|
|
|
|
NTSTATUS
|
|
HalpIrqTranslateResourcesPci(
|
|
IN PVOID Context,
|
|
IN PCM_PARTIAL_RESOURCE_DESCRIPTOR Source,
|
|
IN RESOURCE_TRANSLATION_DIRECTION Direction,
|
|
IN ULONG AlternativesCount, OPTIONAL
|
|
IN IO_RESOURCE_DESCRIPTOR Alternatives[], OPTIONAL
|
|
IN PDEVICE_OBJECT PhysicalDeviceObject,
|
|
OUT PCM_PARTIAL_RESOURCE_DESCRIPTOR Target
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function translates IRQ resources between the
|
|
IDT and PCI busses that are described in the MPS
|
|
tables. The translation can go in either direction.
|
|
|
|
Arguments:
|
|
|
|
Context - Must hold the slot number of the bridge in
|
|
the lower sixteen bits. Must hold the
|
|
the bridge's primary bus number in the
|
|
upper sixteen bits.
|
|
|
|
Return Value:
|
|
|
|
status
|
|
|
|
--*/
|
|
{
|
|
PPCMPBUSTRANS busType;
|
|
PBUS_HANDLER busHandler;
|
|
UCHAR mpsBusNumber = (UCHAR)Context;
|
|
ULONG devPciBus, bridgePciBus;
|
|
KIRQL irql;
|
|
KAFFINITY affinity;
|
|
ULONG vector;
|
|
ULONG busVector;
|
|
NTSTATUS status;
|
|
PCI_SLOT_NUMBER pciSlot;
|
|
UCHAR interruptLine;
|
|
UCHAR interruptPin;
|
|
UCHAR dummy;
|
|
PDEVICE_OBJECT parentPdo;
|
|
ROUTING_TOKEN routingToken;
|
|
BOOLEAN useAlternatives = FALSE;
|
|
BOOLEAN foundBus = FALSE;
|
|
|
|
ASSERT(Source->Type = CmResourceTypeInterrupt);
|
|
ASSERT(PciIrqRoutingInterface.GetInterruptRouting);
|
|
|
|
*Target = *Source;
|
|
|
|
devPciBus = (ULONG)-1;
|
|
pciSlot.u.AsULONG = (ULONG)-1;
|
|
status = PciIrqRoutingInterface.GetInterruptRouting(
|
|
PhysicalDeviceObject,
|
|
&devPciBus,
|
|
&pciSlot.u.AsULONG,
|
|
&interruptLine,
|
|
&interruptPin,
|
|
&dummy,
|
|
&dummy,
|
|
&parentPdo,
|
|
&routingToken,
|
|
&dummy
|
|
);
|
|
|
|
ASSERT(NT_SUCCESS(status));
|
|
|
|
switch (Direction) {
|
|
case TranslateChildToParent:
|
|
|
|
if (Context == (PVOID)USE_INT_LINE_REGISTER_TOKEN) {
|
|
|
|
//
|
|
// This bus's vectors aren't described in
|
|
// the MPS table. So just use the Int Line
|
|
// register.
|
|
//
|
|
|
|
interruptLine = (UCHAR)Source->u.Interrupt.Vector;
|
|
|
|
busVector = interruptLine;
|
|
|
|
busHandler = HaliHandlerForBus(Isa, 0);
|
|
|
|
} else {
|
|
|
|
//
|
|
// Find the PCI bus that corresponds to this MPS bus.
|
|
//
|
|
|
|
mpsBusNumber = (UCHAR)Context;
|
|
foundBus = HalpMPSBusId2NtBusId(mpsBusNumber,
|
|
&busType,
|
|
&bridgePciBus);
|
|
|
|
if (!foundBus) {
|
|
return STATUS_INVALID_PARAMETER_1;
|
|
}
|
|
|
|
ASSERT(busType->NtType == PCIBus);
|
|
|
|
//
|
|
// Start with the assumption that the incoming
|
|
// resources will contain the proper MPS-style
|
|
// interrupt vector. This will be guaranteed
|
|
// to be true if some previous translation has
|
|
// been done on these resources. And it might
|
|
// be true otherwise.
|
|
//
|
|
|
|
busVector = Source->u.Interrupt.Vector;
|
|
|
|
if (devPciBus == bridgePciBus) {
|
|
|
|
//
|
|
// If this device sits on the bus for which
|
|
// this translator has been ejected, we can
|
|
// do better than to assume the incoming
|
|
// resources are clever.
|
|
//
|
|
|
|
busVector = PCIPin2Int(pciSlot, interruptPin);
|
|
}
|
|
|
|
//
|
|
// TEMPTEMP Use bus handlers for now.
|
|
//
|
|
|
|
busHandler = HaliHandlerForBus(PCIBus, devPciBus);
|
|
|
|
}
|
|
|
|
vector = busHandler->GetInterruptVector(busHandler,
|
|
busHandler,
|
|
busVector,
|
|
busVector,
|
|
&irql,
|
|
&affinity);
|
|
|
|
ASSERT(vector != 0);
|
|
|
|
Target->u.Interrupt.Vector = vector;
|
|
Target->u.Interrupt.Level = irql;
|
|
Target->u.Interrupt.Affinity = affinity;
|
|
|
|
return STATUS_TRANSLATION_COMPLETE;
|
|
|
|
case TranslateParentToChild:
|
|
|
|
//
|
|
// There is a problem here. We are translating from the
|
|
// context of the IDT down to the context of a specific
|
|
// PCI bus. (One decribed in the MPS tables.) This may
|
|
// not, however, be the bus that PhysicalDeviceObject's
|
|
// hardware lives on. There may be plug-in PCI to PCI
|
|
// bridges between this bus and the device.
|
|
//
|
|
// But we are not being asked the question "What is the
|
|
// bus-relative interrupt with respect to the bus that
|
|
// the device lives on?" We are being asked "What is the
|
|
// bus-relative interrupt once that interrupt passes through
|
|
// all those briges and makes it up to this bus?" This
|
|
// turns out to be a much harder question.
|
|
//
|
|
// There are really two cases:
|
|
//
|
|
// 1) There are no bridges between this bus and the device.
|
|
//
|
|
// This is easy. We answer the first question above and
|
|
// we're done. (This information will actually get used.
|
|
// it will appear in the start device IRP and the device
|
|
// manager.)
|
|
//
|
|
// 2) There are bridges.
|
|
//
|
|
// This is the hard case. And the information, were we
|
|
// actually going to bother to dig it up, would get thrown
|
|
// away. Nobody actually cares what the answer is. The
|
|
// only place it is going is the "Source" argument to
|
|
// the next translator. And the translator for PCI to PCI
|
|
// bridges won't end up using it.
|
|
//
|
|
// So we punt here and just answer the first question.
|
|
//
|
|
|
|
if (Context == (PVOID)USE_INT_LINE_REGISTER_TOKEN) {
|
|
|
|
Target->u.Interrupt.Vector = interruptLine;
|
|
|
|
} else {
|
|
|
|
mpsBusNumber = (UCHAR)Context;
|
|
if (HalpMPSBusId2NtBusId(mpsBusNumber,
|
|
&busType,
|
|
&bridgePciBus)) {
|
|
|
|
if (devPciBus == bridgePciBus) {
|
|
|
|
Target->u.Interrupt.Vector = PCIPin2Int(pciSlot, interruptPin);
|
|
|
|
} else {
|
|
|
|
useAlternatives = TRUE;
|
|
}
|
|
|
|
} else {
|
|
|
|
useAlternatives = TRUE;
|
|
}
|
|
}
|
|
|
|
if (useAlternatives) {
|
|
|
|
//
|
|
// Setup the default case. We assume that the I/O
|
|
// res list had the right answer.
|
|
//
|
|
|
|
ASSERT(AlternativesCount == 1);
|
|
ASSERT(Alternatives[0].Type == CmResourceTypeInterrupt);
|
|
|
|
Target->u.Interrupt.Vector = Alternatives[0].u.Interrupt.MinimumVector;
|
|
}
|
|
|
|
Target->u.Interrupt.Level = Target->u.Interrupt.Vector;
|
|
Target->u.Interrupt.Affinity = 0xffffffff;
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
return STATUS_INVALID_PARAMETER_3;
|
|
}
|
|
|