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962 lines
24 KiB
962 lines
24 KiB
/*++
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Copyright (c) 1991 Microsoft Corporation
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Copyright (c) 1992 Intel Corporation
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All rights reserved
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INTEL CORPORATION PROPRIETARY INFORMATION
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This software is supplied to Microsoft under the terms
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of a license agreement with Intel Corporation and may not be
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copied nor disclosed except in accordance with the terms
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of that agreement.
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Module Name:
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mpsproc.c
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Abstract:
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PC+MP Start Next Processor c code.
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This module implements the initialization of the system dependent
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functions that define the Hardware Architecture Layer (HAL) for a
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PC+MP System
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Author:
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Ken Reneris (kenr) 22-Jan-1991
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Environment:
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Kernel mode only.
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Revision History:
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Ron Mosgrove (Intel) - Modified to support the PC+MP
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Jake Oshins (jakeo) - Modified for ACPI MP machines 22-Dec-1997
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--*/
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#if !defined(_HALPAE_)
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#define _HALPAE_
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#endif
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#include "halp.h"
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#include "apic.inc"
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#include "pcmp_nt.inc"
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#include "stdio.h"
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#ifdef ACPI_HAL
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#include "acpitabl.h"
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#endif
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#ifdef DEBUGGING
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void
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HalpDisplayString(
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IN PVOID String
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);
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#endif // DEBUGGING
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#if defined(ACPI_HAL)
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const ULONG HalDisableFirmwareMapper = 1;
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#if !defined(NT_UP)
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const UCHAR HalName[] = "ACPI 1.0 - APIC platform MP";
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#define HalName L"ACPI 1.0 - APIC platform MP"
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WCHAR HalHardwareIdString[] = L"acpiapic_mp\0";
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#else
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const UCHAR HalName[] = "ACPI 1.0 - APIC platform UP";
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#define HalName L"ACPI 1.0 - APIC platform UP"
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WCHAR MpHalHardwareIdString[] = L"acpiapic_mp\0";
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WCHAR HalHardwareIdString[] = L"acpiapic_up\0";
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#endif
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#else
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const ULONG HalDisableFirmwareMapper = 0;
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#if !defined(NT_UP)
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const UCHAR HalName[] = "MPS 1.4 - APIC platform";
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#define HalName L"MPS 1.4 - APIC platform"
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WCHAR HalHardwareIdString[] = L"mps_mp\0";
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#else
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const UCHAR HalName[] = "UP MPS 1.4 - APIC platform";
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#define HalName L"UP MPS 1.4 - APIC platform"
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WCHAR MpHalHardwareIdString[] = L"mps_mp\0";
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WCHAR HalHardwareIdString[] = L"mps_up\0";
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#endif
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#endif
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#if !defined(NT_UP)
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ULONG
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HalpStartProcessor (
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IN PVOID InitCodePhysAddr,
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IN ULONG ProcessorNumber
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);
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#endif
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VOID
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HalpInitMP (
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IN ULONG Phase,
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IN PLOADER_PARAMETER_BLOCK LoaderBlock
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);
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VOID
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HalpInitOtherBuses (
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VOID
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);
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VOID
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HalpInitializePciBus (
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VOID
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);
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VOID
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HalpInitializePciStubs (
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VOID
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);
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VOID
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HalpInheritBusAddressMapInfo (
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VOID
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);
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VOID
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HalpInitBusAddressMapInfo (
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VOID
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);
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VOID
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HalpResetThisProcessor (
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VOID
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);
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HAL_INTERRUPT_SERVICE_PROTOTYPE(HalpApicRebootService);
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#ifdef ACPI_HAL
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VOID
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HalpInitMpInfo (
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IN PMAPIC ApicTable,
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IN ULONG Phase
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);
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extern PMAPIC HalpApicTable;
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#endif
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extern VOID (*HalpRebootNow)(VOID);
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extern volatile ULONG HalpNMIInProgress;
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volatile ULONG HalpProcessorsNotHalted = 0;
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#define LOW_MEMORY 0x000100000
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//
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// From hal386.inc
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//
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#define IDT_NMI_VECTOR 2
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#define D_INT032 0x8E00
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#if !defined(KGDT_R0_CODE)
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#define KGDT_R0_CODE 0x8
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#endif
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//
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// Defines to let us diddle the CMOS clock and the keyboard
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//
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#define CMOS_CTRL (PUCHAR )0x70
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#define CMOS_DATA (PUCHAR )0x71
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#define RESET 0xfe
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#define KEYBPORT (PUCHAR )0x64
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extern USHORT HalpGlobal8259Mask;
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extern PKPCR HalpProcessorPCR[];
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extern struct HalpMpInfo HalpMpInfoTable;
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extern ULONG HalpIpiClock;
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extern PVOID HalpLowStubPhysicalAddress; // pointer to low memory bootup stub
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extern PUCHAR HalpLowStub; // pointer to low memory bootup stub
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PUCHAR Halp1stPhysicalPageVaddr; // pointer to physical memory 0:0
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PUSHORT MppProcessorAvail; // pointer to processavail flag
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ULONG HalpDontStartProcessors = 0;
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#ifdef ALLOC_PRAGMA
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#pragma alloc_text(INIT,HalpInitMP)
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#pragma alloc_text(INIT,HalAllProcessorsStarted)
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#pragma alloc_text(INIT,HalReportResourceUsage)
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#pragma alloc_text(INIT,HalpInitOtherBuses)
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#if !defined(NT_UP)
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#pragma alloc_text(PAGELK,HalpStartProcessor)
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#endif
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#endif
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VOID
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HalpInitMP (
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IN ULONG Phase,
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IN PLOADER_PARAMETER_BLOCK LoaderBlock
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)
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/*++
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Routine Description:
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Allows MP initialization from HalInitSystem.
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Arguments:
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Same as HalInitSystem
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Return Value:
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None.
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--*/
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{
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PKPCR pPCR;
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PHYSICAL_ADDRESS physicalAddress;
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pPCR = KeGetPcr();
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//
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// Increment a count of the number of processors
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// running NT, This could be different from the
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// number of enabled processors, if one or more
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// of the processor failed to start.
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//
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if (Phase == 1)
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HalpMpInfoTable.NtProcessors++;
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#ifdef DEBUGGING
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sprintf(Cbuf, "HalpInitMP: Number of Processors = 0x%x\n",
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HalpMpInfoTable.NtProcessors);
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HalpDisplayString(Cbuf);
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#endif
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if (Phase == 0) {
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#if defined(NT_UP)
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//
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// On UP build - done
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//
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return ;
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#endif
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//
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// Map the 1st Physical page of memory
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//
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physicalAddress.QuadPart = 0;
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Halp1stPhysicalPageVaddr = HalpMapPhysicalMemoryWriteThrough (physicalAddress, 1);
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//
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// Allocate some low memory for processor bootup stub
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//
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HalpLowStubPhysicalAddress =
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UlongToPtr(HalpAllocPhysicalMemory (LoaderBlock,
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LOW_MEMORY, 1, FALSE));
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if (!HalpLowStubPhysicalAddress) {
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//
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// Can't get memory
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//
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#if DBG
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DbgPrint("HAL: can't allocate memory to start processors\n");
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#endif
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return;
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}
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physicalAddress.QuadPart = (ULONGLONG)HalpLowStubPhysicalAddress;
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HalpLowStub = (PCHAR) HalpMapPhysicalMemory (physicalAddress, 1);
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} else {
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//
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// Phase 1 for another processor
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//
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if (CurrentPrcb(pPCR)->Number != 0) {
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HalpIpiClock = 0xff;
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}
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#ifdef ACPI_HAL
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HalpInitMpInfo(HalpApicTable, Phase);
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#endif
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}
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}
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BOOLEAN
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HalAllProcessorsStarted (
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VOID
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)
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{
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if (KeGetPcr()->Number == 0) {
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if (HalpFeatureBits & HAL_PERF_EVENTS) {
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//
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// Enable local perf events on each processor
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//
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HalpGenericCall (
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HalpEnablePerfInterupt,
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0,
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HalpActiveProcessors
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);
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}
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#if !defined(_AMD64_)
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if (HalpFeatureBits & HAL_NO_SPECULATION) {
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//
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// Processor doesn't perform speculative execeution,
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// remove fences in critical code paths
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//
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HalpRemoveFences ();
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}
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#endif
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}
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return TRUE;
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}
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VOID
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HalpInitOtherBuses (
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VOID
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)
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{
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//
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// Registry is now intialized, see if there are any PCI buses
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//
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}
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VOID
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HalReportResourceUsage (
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VOID
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)
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/*++
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Routine Description:
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The registery is now enabled - time to report resources which are
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used by the HAL.
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Arguments:
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Return Value:
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--*/
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{
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UNICODE_STRING UHalName;
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INTERFACE_TYPE interfacetype;
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//
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// Initialize phase 2
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//
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HalInitSystemPhase2 ();
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//
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// Turn on MCA support if present
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//
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HalpMcaInit();
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//
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// Registry is now intialized, see if there are any PCI buses
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//
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HalpInitializePciBus ();
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HalpInitializePciStubs ();
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#ifndef ACPI_HAL // ACPI HALs don't deal with address maps
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//
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// Update supported address info with MPS bus address map
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//
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HalpInitBusAddressMapInfo ();
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//
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// Inherit any bus address mappings from MPS hierarchy descriptors
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//
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HalpInheritBusAddressMapInfo ();
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#endif
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//
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// Set type
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//
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switch (HalpBusType) {
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case MACHINE_TYPE_ISA: interfacetype = Isa; break;
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case MACHINE_TYPE_EISA: interfacetype = Eisa; break;
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case MACHINE_TYPE_MCA: interfacetype = MicroChannel; break;
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default: interfacetype = PCIBus; break;
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}
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//
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// Report HALs resource usage
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//
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RtlInitUnicodeString (&UHalName, HalName);
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HalpReportResourceUsage (
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&UHalName, // descriptive name
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interfacetype
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);
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#ifndef ACPI_HAL // ACPI HALs don't deal with address maps
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//
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// Register hibernate support
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//
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HalpRegisterHibernate();
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#endif
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HalpRegisterPciDebuggingDeviceInfo();
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}
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VOID
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HalpResetAllProcessors (
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VOID
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)
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/*++
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Routine Description:
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This procedure is called by the HalpReboot routine. It is called in
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response to a system reset request.
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This routine generates a reboot request via the APIC's ICR.
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This routine will NOT return.
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--*/
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{
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ULONG_PTR j;
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PKGDTENTRY GdtPtr;
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ULONG TssAddr;
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PKPRCB Prcb;
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#if defined(_AMD64_)
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PKIDTENTRY64 idtEntry;
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KIDT_HANDLER_ADDRESS handler;
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handler.Address = (ULONG64)HalpApicRebootService;
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#endif
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if (HalpNMIInProgress) {
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//
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// If we are in an NMI then none of the code below is going to work so just reset the old fashion way
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//
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HalpWriteResetCommand();
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}
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#ifndef NT_UP
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HalpProcessorsNotHalted = HalpMpInfoTable.NtProcessors;
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#else
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//
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// Only this processor needs to be halted
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//
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HalpProcessorsNotHalted = 1;
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#endif
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//
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// Set all processors NMI handlers
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//
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for (j = 0; j < HalpMpInfoTable.NtProcessors; ++j) {
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#if defined(_AMD64_)
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idtEntry = &HalpProcessorPCR[j]->IdtBase[IDT_NMI_VECTOR];
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idtEntry->OffsetLow = handler.OffsetLow;
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idtEntry->OffsetMiddle = handler.OffsetMiddle;
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idtEntry->OffsetHigh = handler.OffsetHigh;
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#else
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GdtPtr = &HalpProcessorPCR[j]->
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GDT[HalpProcessorPCR[j]->IDT[IDT_NMI_VECTOR].Selector >> 3];
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TssAddr = (((GdtPtr->HighWord.Bits.BaseHi << 8) +
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GdtPtr->HighWord.Bits.BaseMid) << 16) + GdtPtr->BaseLow;
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((PKTSS)TssAddr)->Eip = (ULONG)HalpApicRebootService;
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#endif
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}
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if (HalpProcessorsNotHalted > 1) {
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//
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// Wait for the ICR to become free
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//
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if (HalpWaitForPending (0xFFFF, pLocalApic + LU_INT_CMD_LOW/4)) {
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//
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// For P54c or better processors, reboot by sending all processors
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// NMIs. For pentiums we send interrupts, since there are some
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// pentium MP machines where the NMIs method does not work.
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//
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// The NMI method is better.
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//
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Prcb = KeGetCurrentPrcb();
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j = Prcb->CpuType << 16 | (Prcb->CpuStep & 0xff00);
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if (j > 0x50100) {
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|
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//
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// Get other processors attention with an NMI
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//
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// BUGBUG if we're in cluster mode?
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//
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j = HalpActiveProcessors & ~Prcb->SetMember;
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j = j << DESTINATION_SHIFT;
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pLocalApic[LU_INT_CMD_HIGH/4] = (ULONG)j;
|
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pLocalApic[LU_INT_CMD_LOW/4] = (ICR_USE_DEST_FIELD | LOGICAL_DESTINATION | DELIVER_NMI);
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|
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//
|
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// Wait 5ms and see if any processors took the NMI. If not,
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// go do it the old way.
|
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//
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KeStallExecutionProcessor(5000);
|
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if (HalpProcessorsNotHalted != HalpMpInfoTable.NtProcessors) {
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|
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//
|
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// Reboot local
|
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//
|
|
|
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#if defined(_AMD64_)
|
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HalpApicRebootService(NULL,NULL);
|
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#else
|
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HalpApicRebootService();
|
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#endif
|
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}
|
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}
|
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|
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//
|
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// Signal other processors which also may be waiting to
|
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// reboot the machine, that it's time to go
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//
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|
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HalpRebootNow = HalpResetThisProcessor;
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|
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//
|
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// Send a reboot interrupt
|
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//
|
|
|
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pLocalApic[LU_INT_CMD_LOW/4] = (ICR_ALL_INCL_SELF | APIC_REBOOT_VECTOR);
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|
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//
|
|
// we're done - set TPR to zero so the reboot interrupt will happen
|
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//
|
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|
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pLocalApic[LU_TPR/4] = 0;
|
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HalpEnableInterrupts();
|
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for (; ;) ;
|
|
}
|
|
}
|
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|
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//
|
|
// Reset the old fashion way
|
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//
|
|
HalpWriteResetCommand();
|
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|
|
}
|
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|
|
VOID
|
|
HalpResetThisProcessor (
|
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VOID
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This procedure is called by the HalpReboot routine.
|
|
It is called in response to a system reset request.
|
|
|
|
This routine is called by the reboot ISR (linked to
|
|
APIC_REBOOT_VECTOR). The HalpResetAllProcessors
|
|
generates the reboot request via the APIC's ICR.
|
|
|
|
The function of this routine is to perform any processor
|
|
specific shutdown code needed and then reset the system
|
|
(on the BSP==P0 only).
|
|
|
|
This routine will NOT return.
|
|
|
|
--*/
|
|
{
|
|
PUSHORT Magic;
|
|
ULONG ThisProcessor = 0;
|
|
ULONG i, j, max, RedirEntry;
|
|
struct ApicIoUnit *IoUnitPtr;
|
|
PHYSICAL_ADDRESS physicalAddress;
|
|
|
|
ThisProcessor = CurrentPrcb(KeGetPcr())->Number;
|
|
|
|
//
|
|
// Do whatever is needed to this processor to restore
|
|
// system to a bootable state
|
|
//
|
|
|
|
pLocalApic[LU_TPR/4] = 0xff;
|
|
pLocalApic[LU_TIMER_VECTOR/4] =
|
|
(APIC_SPURIOUS_VECTOR |PERIODIC_TIMER | INTERRUPT_MASKED);
|
|
pLocalApic[LU_INT_VECTOR_0/4] =
|
|
(APIC_SPURIOUS_VECTOR | INTERRUPT_MASKED);
|
|
pLocalApic[LU_INT_VECTOR_1/4] =
|
|
( LEVEL_TRIGGERED | ACTIVE_HIGH | DELIVER_NMI |
|
|
INTERRUPT_MASKED | NMI_VECTOR);
|
|
if (HalpMpInfoTable.ApicVersion != APIC_82489DX) {
|
|
pLocalApic[LU_FAULT_VECTOR/4] =
|
|
APIC_FAULT_VECTOR | INTERRUPT_MASKED;
|
|
}
|
|
|
|
if (ThisProcessor == 0) {
|
|
|
|
InterlockedDecrement(&HalpProcessorsNotHalted);
|
|
|
|
//
|
|
// we are running on the BSP, wait for everyone to
|
|
// complete the re-initialization code above
|
|
//
|
|
|
|
while (InterlockedAnd(&HalpProcessorsNotHalted,0xffffffff) != 0) {
|
|
;
|
|
}
|
|
|
|
KeStallExecutionProcessor(100);
|
|
|
|
//
|
|
// Write the Shutdown reason code, so the BIOS knows
|
|
// this is a reboot
|
|
//
|
|
|
|
WRITE_PORT_UCHAR(CMOS_CTRL, 0x0f); // CMOS Addr 0f
|
|
|
|
WRITE_PORT_UCHAR(CMOS_DATA, 0x00); // Reason Code Reset
|
|
|
|
physicalAddress.QuadPart = 0;
|
|
Magic = HalpMapPhysicalMemoryWriteThrough(physicalAddress, 1);
|
|
Magic[0x472 / sizeof(USHORT)] = 0x1234; // warm boot
|
|
|
|
//
|
|
// If required, disable APIC mode
|
|
//
|
|
|
|
if (HalpMpInfoTable.IMCRPresent)
|
|
{
|
|
WRITE_PORT_UCHAR(UlongToPtr(ImcrRegPortAddr),ImcrPort);
|
|
KeStallExecutionProcessor(100);
|
|
WRITE_PORT_UCHAR(UlongToPtr(ImcrDataPortAddr),ImcrDisableApic);
|
|
}
|
|
|
|
KeStallExecutionProcessor(100);
|
|
|
|
for (j=0; j<HalpMpInfoTable.IOApicCount; j++) {
|
|
IoUnitPtr = (struct ApicIoUnit *) HalpMpInfoTable.IoApicBase[j];
|
|
|
|
//
|
|
// Disable all interrupts on IO Unit
|
|
//
|
|
|
|
IoUnitPtr->RegisterSelect = IO_VERS_REGISTER;
|
|
max = ((IoUnitPtr->RegisterWindow >> 16) & 0xff) * 2;
|
|
for (i=0; i <= max; i += 2) {
|
|
IoUnitPtr->RegisterSelect = IO_REDIR_00_LOW + i;
|
|
IoUnitPtr->RegisterWindow |= INT_VECTOR_MASK | INTERRUPT_MASKED;
|
|
|
|
//
|
|
// Clear any set Remote IRR bits by programming the entry to
|
|
// edge and then back to level. Otherwise there will be
|
|
// no further interrupts from this source.
|
|
//
|
|
|
|
IoUnitPtr->RegisterSelect = IO_REDIR_00_LOW + i;
|
|
RedirEntry = IoUnitPtr->RegisterWindow;
|
|
if ( (RedirEntry & LEVEL_TRIGGERED) && (RedirEntry & REMOTE_IRR)) {
|
|
RedirEntry &= ~LEVEL_TRIGGERED;
|
|
IoUnitPtr->RegisterWindow = RedirEntry;
|
|
RedirEntry = IoUnitPtr->RegisterWindow;
|
|
RedirEntry |= LEVEL_TRIGGERED;
|
|
IoUnitPtr->RegisterWindow = RedirEntry;
|
|
}
|
|
}
|
|
} // for all Io Apics
|
|
|
|
//
|
|
// Disable the Local Apic
|
|
//
|
|
pLocalApic[LU_SPURIOUS_VECTOR/4] =
|
|
(APIC_SPURIOUS_VECTOR | LU_UNIT_DISABLED);
|
|
|
|
|
|
KeStallExecutionProcessor(100);
|
|
|
|
HalpDisableInterrupts();
|
|
|
|
//
|
|
// Enable Pic interrupts
|
|
//
|
|
HalpGlobal8259Mask = 0;
|
|
HalpSet8259Mask ((USHORT) HalpGlobal8259Mask);
|
|
|
|
KeStallExecutionProcessor(1000);
|
|
|
|
//
|
|
// Finally, reset the system.
|
|
//
|
|
HalpWriteResetCommand();
|
|
|
|
|
|
} else {
|
|
//
|
|
// We're running on a processor other than the BSP
|
|
//
|
|
|
|
//
|
|
// Disable the Local Apic
|
|
//
|
|
|
|
pLocalApic[LU_SPURIOUS_VECTOR/4] =
|
|
(APIC_SPURIOUS_VECTOR | LU_UNIT_DISABLED);
|
|
|
|
KeStallExecutionProcessor(100);
|
|
|
|
//
|
|
// Now we are done, tell the BSP
|
|
//
|
|
|
|
InterlockedDecrement(&HalpProcessorsNotHalted);
|
|
|
|
} // Not BSP
|
|
|
|
|
|
//
|
|
// Everyone stops here until reset
|
|
//
|
|
|
|
HalpDisableInterrupts();
|
|
while (TRUE) {
|
|
HalpHalt();
|
|
}
|
|
}
|
|
|
|
#if !defined(NT_UP)
|
|
ULONG
|
|
HalpStartProcessor (
|
|
IN PVOID InitCodePhysAddr,
|
|
IN ULONG ProcessorNumber
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
Actually Start the Processor in question. This routine
|
|
assumes the init code is setup and ready to run. The real
|
|
mode init code must begin on a page boundry.
|
|
|
|
NOTE: This assumes the BSP is entry 0 in the MP table.
|
|
|
|
This routine cannot fail.
|
|
|
|
Arguments:
|
|
InitCodePhysAddr - execution address of init code
|
|
|
|
Return Value:
|
|
0 - Something prevented us from issuing the reset.
|
|
|
|
n - Processor's PCMP Local APICID + 1
|
|
--*/
|
|
{
|
|
NTSTATUS status;
|
|
UCHAR ApicID;
|
|
PVULONG LuDestAddress = (PVULONG) (LOCALAPIC + LU_INT_CMD_HIGH);
|
|
PVULONG LuICR = (PVULONG) (LOCALAPIC + LU_INT_CMD_LOW);
|
|
#define DEFAULT_DELAY 100
|
|
ULONG DelayCount = DEFAULT_DELAY;
|
|
ULONG ICRCommand,i;
|
|
|
|
ASSERT((((ULONG_PTR) InitCodePhysAddr) & 0xfff00fff) == 0);
|
|
|
|
if (ProcessorNumber >= HalpMpInfoTable.ProcessorCount) {
|
|
return(0);
|
|
}
|
|
|
|
//
|
|
// Get the APIC ID of the processor to start.
|
|
//
|
|
|
|
status = HalpGetNextProcessorApicId(ProcessorNumber,
|
|
&ApicID);
|
|
|
|
if (!NT_SUCCESS(status)) {
|
|
#ifdef DEBUGGING
|
|
HalpDisplayString("HAL: HalpStartProcessor: No Processor Available\n");
|
|
#endif
|
|
return(0);
|
|
}
|
|
|
|
if (HalpDontStartProcessors)
|
|
return ApicID+1;
|
|
|
|
//
|
|
// Make sure we can get to the Apic Bus
|
|
//
|
|
|
|
KeStallExecutionProcessor(200);
|
|
if (HalpWaitForPending (DEFAULT_DELAY, LuICR) == 0) {
|
|
//
|
|
// We couldn't find a processor to start
|
|
//
|
|
#ifdef DEBUGGING
|
|
HalpDisplayString("HAL: HalpStartProcessor: can't access APIC Bus\n");
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
// For a P54 C/CM system, it is possible that the BSP is the P54CM and the
|
|
// P54C is the Application processor. The P54C needs an INIT (reset)
|
|
// to restart, so we issue a reset regardless of whether we a 82489DX
|
|
// or an integrated APIC.
|
|
|
|
//
|
|
// This system is based on the original 82489DX's.
|
|
// These devices do not support the Startup IPI's.
|
|
// The mechanism used is the ASSERT/DEASSERT INIT
|
|
// feature of the local APIC. This resets the
|
|
// processor.
|
|
//
|
|
|
|
#ifdef DEBUGGING
|
|
sprintf(Cbuf, "HAL: HalpStartProcessor: Reset IPI to ApicId %d (0x%x)\n",
|
|
ApicID,((ULONG) ApicID) << DESTINATION_SHIFT );
|
|
HalpDisplayString(Cbuf);
|
|
#endif
|
|
|
|
//
|
|
// We use a Physical Destination
|
|
//
|
|
|
|
*LuDestAddress = ((ULONG) ApicID) << DESTINATION_SHIFT;
|
|
|
|
//
|
|
// Now Assert reset and drop it
|
|
//
|
|
|
|
*LuICR = LU_RESET_ASSERT;
|
|
KeStallExecutionProcessor(10);
|
|
*LuICR = LU_RESET_DEASSERT;
|
|
KeStallExecutionProcessor(200);
|
|
|
|
if (HalpMpInfoTable.ApicVersion == APIC_82489DX) {
|
|
return ApicID+1;
|
|
}
|
|
|
|
//
|
|
// Set the Startup Address as a vector and combine with the
|
|
// ICR bits
|
|
//
|
|
ICRCommand = (ULONG)((((ULONG_PTR) InitCodePhysAddr & 0x000ff000) >> 12)
|
|
| LU_STARTUP_IPI);
|
|
|
|
#ifdef DEBUGGING
|
|
sprintf(Cbuf, "HAL: HalpStartProcessor: Startup IPI (0x%x) to ApicId %d (0x%x)\n",
|
|
ICRCommand, ApicID, ((ULONG) ApicID) << DESTINATION_SHIFT );
|
|
HalpDisplayString(Cbuf);
|
|
#endif
|
|
|
|
//
|
|
// Set the Address of the APIC again, this may not be needed
|
|
// but it can't hurt.
|
|
//
|
|
*LuDestAddress = (ApicID << DESTINATION_SHIFT);
|
|
//
|
|
// Issue the request
|
|
//
|
|
*LuICR = ICRCommand;
|
|
KeStallExecutionProcessor(200);
|
|
|
|
//
|
|
// Repeat the Startup IPI. This is because the second processor may
|
|
// have been issued an INIT request. This is generated by some BIOSs.
|
|
//
|
|
// On older processors (286) BIOS's use a mechanism called triple
|
|
// fault reset to transition from protected mode to real mode.
|
|
// This mechanism causes the processor to generate a shutdown cycle.
|
|
// The shutdown is typically issued by the BIOS building an invalid
|
|
// IDT and then generating an interrupt. Newer processors have an
|
|
// INIT line that the chipset jerks when it sees a shutdown cycle
|
|
// issued by the processor. The Phoenix BIOS, for example, has
|
|
// integrated support for triple fault reset as part of their POST
|
|
// (Power On Self Test) code.
|
|
//
|
|
// When the P54CM powers on it is held in a tight microcode loop
|
|
// waiting for a Startup IPI to be issued and queuing other requests.
|
|
// When the POST code executes the triple fault reset test the INIT
|
|
// cycle is queued by the processor. Later, when a Startup IPI is
|
|
// issued to the CM, the CM starts and immediately gets a INIT cycle.
|
|
// The effect from a software standpoint is that the processor is
|
|
// never started.
|
|
//
|
|
// The work around implemented here is to issue two Startup IPI's.
|
|
// The first allows the INIT to be processed and the second performs
|
|
// the actual startup.
|
|
//
|
|
|
|
//
|
|
// Make sure we can get to the Apic Bus
|
|
//
|
|
|
|
|
|
if (HalpWaitForPending (DEFAULT_DELAY, LuICR) == 0) {
|
|
//
|
|
// We're toast, can't gain access to the APIC Bus
|
|
//
|
|
#ifdef DEBUGGING
|
|
HalpDisplayString("HAL: HalpStartProcessor: can't access APIC Bus\n");
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
//
|
|
// Allow Time for any Init request to be processed
|
|
//
|
|
KeStallExecutionProcessor(100);
|
|
|
|
//
|
|
// Set the Address of the APIC again, this may not be needed
|
|
// but it can't hurt.
|
|
//
|
|
*LuDestAddress = (ApicID << DESTINATION_SHIFT);
|
|
//
|
|
// Issue the request
|
|
//
|
|
*LuICR = ICRCommand;
|
|
|
|
KeStallExecutionProcessor(200);
|
|
return ApicID+1;
|
|
}
|
|
#endif // !NT_UP
|
|
|
|
|
|
ULONG
|
|
FASTCALL
|
|
HalSystemVectorDispatchEntry (
|
|
IN ULONG Vector,
|
|
OUT PKINTERRUPT_ROUTINE **FlatDispatch,
|
|
OUT PKINTERRUPT_ROUTINE *NoConnection
|
|
)
|
|
{
|
|
return FALSE;
|
|
}
|