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785 lines
18 KiB
785 lines
18 KiB
#include "ki.h"
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#define STATIC
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#define IDBG 0
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#if DBG
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#define DBGMSG(a) DbgPrint(a)
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#else
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#define DBGMSG(a)
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#endif
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//
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// Externals.
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//
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NTSTATUS
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KiLoadMTRR (
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PVOID Context
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);
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// --- AMD Structure definitions ---
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// K6 MTRR hardware register layout.
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// Single MTRR control register.
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typedef struct _AMDK6_MTRR {
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ULONG type:2;
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ULONG mask:15;
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ULONG base:15;
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} AMDK6_MTRR, *PAMDK6_MTRR;
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// MSR image, contains two control regs.
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typedef struct _AMDK6_MTRR_MSR_IMAGE {
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union {
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struct {
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AMDK6_MTRR mtrr0;
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AMDK6_MTRR mtrr1;
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} hw;
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ULONGLONG QuadPart;
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} u;
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} AMDK6_MTRR_MSR_IMAGE, *PAMDK6_MTRR_MSR_IMAGE;
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// MTRR reg type field values.
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#define AMDK6_MTRR_TYPE_DISABLED 0
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#define AMDK6_MTRR_TYPE_UC 1
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#define AMDK6_MTRR_TYPE_WC 2
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#define AMDK6_MTRR_TYPE_MASK 3
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// AMD K6 MTRR MSR Index number
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#define AMDK6_MTRR_MSR 0xC0000085
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//
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// Region table entry - used to track all write combined regions.
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//
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// Set BaseAddress to AMDK6_REGION_UNUSED for unused entries.
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//
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typedef struct _AMDK6_MTRR_REGION {
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ULONG BaseAddress;
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ULONG Size;
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MEMORY_CACHING_TYPE RegionType;
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ULONG RegionFlags;
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} AMDK6_MTRR_REGION, *PAMDK6_MTRR_REGION;
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#define MAX_K6_REGIONS 2 // Limit the write combined regions to 2 since that's how many MTRRs we have available.
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//
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// Value to set base address to for unused indication.
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//
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#define AMDK6_REGION_UNUSED 0xFFFFFFFF
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//
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// Flag to indicate that this region was set up by the BIOS.
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//
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#define AMDK6_REGION_FLAGS_BIOS 0x00000001
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//
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// Usage count for hardware MTRR registers.
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//
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#define AMDK6_MAX_MTRR 2
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//
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// AMD Function Prototypes.
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//
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VOID
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KiAmdK6InitializeMTRR (
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VOID
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);
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NTSTATUS
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KiAmdK6RestoreMTRR (
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);
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NTSTATUS
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KiAmdK6MtrrSetMemoryType (
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ULONG BaseAddress,
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ULONG Size,
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MEMORY_CACHING_TYPE Type
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);
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BOOLEAN
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KiAmdK6AddRegion (
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ULONG BaseAddress,
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ULONG Size,
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MEMORY_CACHING_TYPE Type,
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ULONG Flags
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);
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NTSTATUS
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KiAmdK6MtrrCommitChanges (
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VOID
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);
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NTSTATUS
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KiAmdK6HandleWcRegionRequest (
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ULONG BaseAddress,
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ULONG Size
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);
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VOID
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KiAmdK6MTRRAddRegionFromHW (
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AMDK6_MTRR RegImage
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);
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PAMDK6_MTRR_REGION
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KiAmdK6FindFreeRegion (
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MEMORY_CACHING_TYPE Type
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);
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#pragma alloc_text(INIT,KiAmdK6InitializeMTRR)
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#pragma alloc_text(PAGELK,KiAmdK6RestoreMTRR)
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#pragma alloc_text(PAGELK,KiAmdK6MtrrSetMemoryType)
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#pragma alloc_text(PAGELK,KiAmdK6AddRegion)
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#pragma alloc_text(PAGELK,KiAmdK6MtrrCommitChanges)
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#pragma alloc_text(PAGELK,KiAmdK6HandleWcRegionRequest)
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#pragma alloc_text(PAGELK,KiAmdK6MTRRAddRegionFromHW)
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#pragma alloc_text(PAGELK,KiAmdK6FindFreeRegion)
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// --- AMD Global Variables ---
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extern KSPIN_LOCK KiRangeLock;
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// AmdK6Regions - Table to track wc regions.
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AMDK6_MTRR_REGION AmdK6Regions[MAX_K6_REGIONS];
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ULONG AmdK6RegionCount;
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// Usage counter for hardware MTRRs.
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ULONG AmdMtrrHwUsageCount;
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// Global variable image of MTRR MSR.
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AMDK6_MTRR_MSR_IMAGE KiAmdK6Mtrr;
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// --- AMD Start of code ---
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VOID
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KiAmdK6InitializeMTRR (
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VOID
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)
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{
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ULONG i;
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KIRQL OldIrql;
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DBGMSG("KiAmdK6InitializeMTRR: Initializing K6 MTRR support\n");
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KiAmdK6Mtrr.u.hw.mtrr0.type = AMDK6_MTRR_TYPE_DISABLED;
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KiAmdK6Mtrr.u.hw.mtrr1.type = AMDK6_MTRR_TYPE_DISABLED;
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AmdK6RegionCount = MAX_K6_REGIONS;
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AmdMtrrHwUsageCount = 0;
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//
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// Set all regions to free.
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//
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for (i = 0; i < AmdK6RegionCount; i++) {
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AmdK6Regions[i].BaseAddress = AMDK6_REGION_UNUSED;
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AmdK6Regions[i].RegionFlags = 0;
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}
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//
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// Initialize the spin lock.
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//
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// N.B. Normally this is done by KiInitializeMTRR but that
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// routine is not called in the AMD K6 case.
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//
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KeInitializeSpinLock (&KiRangeLock);
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//
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// Read the MTRR registers to see if the BIOS has set them up.
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// If so, add entries to the region table and adjust the usage
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// count. Serialize the region table.
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//
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KeAcquireSpinLock (&KiRangeLock, &OldIrql);
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KiAmdK6Mtrr.u.QuadPart = RDMSR (AMDK6_MTRR_MSR);
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//
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// Check MTRR0 first.
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//
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KiAmdK6MTRRAddRegionFromHW(KiAmdK6Mtrr.u.hw.mtrr0);
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//
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// Now check MTRR1.
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//
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KiAmdK6MTRRAddRegionFromHW(KiAmdK6Mtrr.u.hw.mtrr1);
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//
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// Release the locks.
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//
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KeReleaseSpinLock (&KiRangeLock, OldIrql);
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}
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VOID
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KiAmdK6MTRRAddRegionFromHW (
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AMDK6_MTRR RegImage
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)
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{
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ULONG BaseAddress, Size, TempMask;
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//
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// Check to see if this MTRR is enabled.
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//
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if (RegImage.type != AMDK6_MTRR_TYPE_DISABLED) {
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//
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// If this is a write combined region then add an entry to
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// the region table.
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//
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if ((RegImage.type & AMDK6_MTRR_TYPE_UC) == 0) {
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//
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// Create a new resion table entry.
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//
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BaseAddress = RegImage.base << 17;
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//
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// Calculate the size base on the mask value.
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//
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TempMask = RegImage.mask;
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//
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// There should never be 4GB WC region!
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//
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ASSERT (TempMask != 0);
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//
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// Start with 128 size and search upward.
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//
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Size = 0x00020000;
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while ((TempMask & 0x00000001) == 0) {
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TempMask >>= 1;
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Size <<= 1;
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}
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//
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// Add the region to the table.
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//
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KiAmdK6AddRegion(BaseAddress,
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Size,
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MmWriteCombined,
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AMDK6_REGION_FLAGS_BIOS);
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AmdMtrrHwUsageCount++;
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}
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}
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}
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NTSTATUS
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KiAmdK6MtrrSetMemoryType (
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ULONG BaseAddress,
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ULONG Size,
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MEMORY_CACHING_TYPE Type
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)
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{
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NTSTATUS Status = STATUS_SUCCESS;
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KIRQL OldIrql;
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switch(Type) {
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case MmWriteCombined:
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//
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// H/W needs updating, lock down the code required to effect
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// the change.
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//
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if (KeGetCurrentIrql() >= DISPATCH_LEVEL) {
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//
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// Code can not be locked down. Supplying a new range type
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// requires that the caller calls at irql < dispatch_level.
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//
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DBGMSG ("KeAmdK6SetPhysicalCacheTypeRange failed due to calling IRQL == DISPATCH_LEVEL\n");
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return STATUS_UNSUCCESSFUL;
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}
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//
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// Lock the code.
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//
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MmLockPagableSectionByHandle(ExPageLockHandle);
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//
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// Serialize the region table.
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//
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KeAcquireSpinLock (&KiRangeLock, &OldIrql);
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Status = KiAmdK6HandleWcRegionRequest(BaseAddress, Size);
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//
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// Release the locks.
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//
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KeReleaseSpinLock (&KiRangeLock, OldIrql);
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MmUnlockPagableImageSection(ExPageLockHandle);
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break; // End of WriteCombined case.
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case MmNonCached:
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//
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// Add an entry to the region table.
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//
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// Don't need to add these to the region table. Non-cached regions are
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// accessed using a non-caching virtual pointer set up in the page tables.
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break;
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case MmCached:
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//
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// Redundant. These should be filtered out in
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// KeAmdK6SetPhysicalCacheTypeRange();
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//
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Status = STATUS_NOT_SUPPORTED;
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break;
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default:
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DBGMSG ("KeAmdK6SetPhysicalCacheTypeRange: no such cache type\n");
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Status = STATUS_INVALID_PARAMETER;
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break;
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}
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return Status;
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}
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NTSTATUS
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KiAmdK6HandleWcRegionRequest (
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ULONG BaseAddress,
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ULONG Size
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)
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{
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ULONG i;
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ULONG AdjustedSize, AdjustedEndAddress, AlignmentMask;
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ULONG CombinedBase, CombinedSize, CombinedAdjustedSize;
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PAMDK6_MTRR_REGION pRegion;
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BOOLEAN bCanCombine, bValidRange;
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//
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// Try and find a region that overlaps or is adjacent to the new one and
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// check to see if the combined region would be a legal mapping.
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//
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for (i = 0; i < AmdK6RegionCount; i++) {
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pRegion = &AmdK6Regions[i];
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if ((pRegion->BaseAddress != AMDK6_REGION_UNUSED) &&
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(pRegion->RegionType == MmWriteCombined)) {
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//
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// Does the new start address overlap or adjoin an
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// existing WC region?
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//
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if (((pRegion->BaseAddress >= BaseAddress) &&
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(pRegion->BaseAddress <= (BaseAddress + Size))) ||
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((BaseAddress <= (pRegion->BaseAddress + pRegion->Size)) &&
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(BaseAddress >= pRegion->BaseAddress))) {
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//
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// Combine the two regions into one.
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//
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AdjustedEndAddress = BaseAddress + Size;
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if (pRegion->BaseAddress < BaseAddress) {
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CombinedBase = pRegion->BaseAddress;
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} else {
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CombinedBase = BaseAddress;
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}
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if ((pRegion->BaseAddress + pRegion->Size) >
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AdjustedEndAddress) {
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CombinedSize = (pRegion->BaseAddress + pRegion->Size) -
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CombinedBase;
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} else {
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CombinedSize = AdjustedEndAddress - CombinedBase;
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}
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//
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// See if the new region would be a legal mapping.
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//
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//
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// Find the smallest legal size that is equal to the requested range. Scan
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// all ranges from 128k - 2G. (Start at 2G and work down).
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//
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CombinedAdjustedSize = 0x80000000;
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AlignmentMask = 0x7fffffff;
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bCanCombine = FALSE;
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while (CombinedAdjustedSize > 0x00010000) {
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//
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// Check the size to see if it matches the requested limit.
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//
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if (CombinedAdjustedSize == CombinedSize) {
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//
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// This one works.
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// Check to see if the base address conforms to the MTRR restrictions.
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//
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if ((CombinedBase & AlignmentMask) == 0) {
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bCanCombine = TRUE;
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}
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break;
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} else {
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//
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// Bump it down to the next range size and try again.
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//
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CombinedAdjustedSize >>= 1;
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AlignmentMask >>= 1;
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}
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}
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if (bCanCombine) {
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//
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// If the resized range is OK, record the change in the region
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// table and commit the changes to hardware.
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//
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pRegion->BaseAddress = CombinedBase;
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pRegion->Size = CombinedAdjustedSize;
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//
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// Reset the BIOS flag since we now "own" this region (if we didn't already).
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//
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pRegion->RegionFlags &= ~AMDK6_REGION_FLAGS_BIOS;
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return KiAmdK6MtrrCommitChanges();
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}
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}
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}
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}
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// A valid combination could not be found, so try to create a new range for this request.
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//
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// Find the smallest legal size that is less than or equal to the requested range. Scan
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// all ranges from 128k - 2G. (Start at 2G and work down).
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//
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AdjustedSize = 0x80000000;
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AlignmentMask = 0x7fffffff;
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bValidRange = FALSE;
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while (AdjustedSize > 0x00010000) {
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//
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// Check the size to see if it matches the requested limit.
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//
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if (AdjustedSize == Size) {
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//
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// This one works.
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//
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// Check to see if the base address conforms to the MTRR restrictions.
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//
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if ((BaseAddress & AlignmentMask) == 0) {
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bValidRange = TRUE;
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}
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//
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// Stop looking.
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//
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break;
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} else {
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//
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// Bump it down to the next range size and try again.
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//
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AdjustedSize >>= 1;
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AlignmentMask >>= 1;
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}
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}
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//
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// Couldn't find a legal region that fit.
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//
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if (!bValidRange) {
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return STATUS_NOT_SUPPORTED;
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}
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//
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// If we got this far then this is a new WC region.
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// Create a new region entry for this request.
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//
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if (!KiAmdK6AddRegion(BaseAddress, AdjustedSize, MmWriteCombined, 0)) {
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return STATUS_UNSUCCESSFUL;
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}
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//
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// Commit the changes to hardware.
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//
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return KiAmdK6MtrrCommitChanges();
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}
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BOOLEAN
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KiAmdK6AddRegion (
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ULONG BaseAddress,
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ULONG Size,
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MEMORY_CACHING_TYPE Type,
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ULONG Flags
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)
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{
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PAMDK6_MTRR_REGION pRegion;
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if ((pRegion = KiAmdK6FindFreeRegion(Type)) == NULL) {
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return FALSE;
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}
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pRegion->BaseAddress = BaseAddress;
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pRegion->Size = Size;
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pRegion->RegionType = Type;
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pRegion->RegionFlags = Flags;
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return TRUE;
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}
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PAMDK6_MTRR_REGION
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KiAmdK6FindFreeRegion (
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MEMORY_CACHING_TYPE Type
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)
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{
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ULONG i;
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|
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//
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// If this is a MmWriteCombined request, limit the number of
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// regions to match the actual hardware support.
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//
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if (Type == MmWriteCombined) {
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if (AmdMtrrHwUsageCount >= AMDK6_MAX_MTRR) {
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//
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// Search the table to see if there are any BIOS entries
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// we can replace.
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//
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for (i = 0; i < AmdK6RegionCount; i++) {
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if (AmdK6Regions[i].RegionFlags & AMDK6_REGION_FLAGS_BIOS) {
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return &AmdK6Regions[i];
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}
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}
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//
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// No free HW MTRRs and no reusable entries.
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//
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return FALSE;
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}
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}
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//
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// Find the next free region in the table.
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//
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for (i = 0; i < AmdK6RegionCount; i++) {
|
|
if (AmdK6Regions[i].BaseAddress == AMDK6_REGION_UNUSED) {
|
|
|
|
if (Type == MmWriteCombined) {
|
|
AmdMtrrHwUsageCount++;
|
|
}
|
|
return &AmdK6Regions[i];
|
|
}
|
|
}
|
|
|
|
|
|
DBGMSG("AmdK6FindFreeRegion: Region Table is Full!\n");
|
|
|
|
return NULL;
|
|
}
|
|
|
|
NTSTATUS
|
|
KiAmdK6MtrrCommitChanges (
|
|
VOID
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
Commits the values in the table to hardware.
|
|
|
|
This procedure builds the MTRR images into the KiAmdK6Mtrr variable and
|
|
calls KiLoadMTRR to actually load the register.
|
|
|
|
Arguments:
|
|
|
|
None.
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
--*/
|
|
|
|
{
|
|
ULONG i, dwWcRangeCount = 0;
|
|
ULONG RangeTemp, RangeMask;
|
|
|
|
//
|
|
// Reset the MTRR image for both MTRRs disabled.
|
|
//
|
|
|
|
KiAmdK6Mtrr.u.hw.mtrr0.type = AMDK6_MTRR_TYPE_DISABLED;
|
|
KiAmdK6Mtrr.u.hw.mtrr1.type = AMDK6_MTRR_TYPE_DISABLED;
|
|
|
|
//
|
|
// Find the Write Combining Regions, if any and set up the MTRR register.
|
|
//
|
|
|
|
for (i = 0; i < AmdK6RegionCount; i++) {
|
|
|
|
//
|
|
// Is this a valid region, and is it a write combined type?
|
|
//
|
|
|
|
if ((AmdK6Regions[i].BaseAddress != AMDK6_REGION_UNUSED) &&
|
|
(AmdK6Regions[i].RegionType == MmWriteCombined)) {
|
|
|
|
//
|
|
// Calculate the correct mask for this range size. The
|
|
// BaseAddress and size were validated and adjusted in
|
|
// AmdK6MtrrSetMemoryType().
|
|
//
|
|
// Start with 128K and scan for all legal range values and
|
|
// build the appropriate range mask at the same time.
|
|
//
|
|
|
|
RangeTemp = 0x00020000;
|
|
RangeMask = 0xfffe0000;
|
|
|
|
while (RangeTemp != 0) {
|
|
if (RangeTemp == AmdK6Regions[i].Size) {
|
|
break;
|
|
}
|
|
RangeTemp <<= 1;
|
|
RangeMask <<= 1;
|
|
}
|
|
if (RangeTemp == 0) {
|
|
|
|
//
|
|
// Not a valid range size. This can never happen!!
|
|
//
|
|
|
|
DBGMSG ("AmdK6MtrrCommitChanges: Bad WC range in region table!\n");
|
|
|
|
return STATUS_NOT_SUPPORTED;
|
|
}
|
|
|
|
//
|
|
// Add the region to the next available register.
|
|
//
|
|
|
|
if (dwWcRangeCount == 0) {
|
|
|
|
KiAmdK6Mtrr.u.hw.mtrr0.base = AmdK6Regions[i].BaseAddress >> 17;
|
|
KiAmdK6Mtrr.u.hw.mtrr0.mask = RangeMask >> 17;
|
|
KiAmdK6Mtrr.u.hw.mtrr0.type = AMDK6_MTRR_TYPE_WC;
|
|
dwWcRangeCount++;
|
|
|
|
} else if (dwWcRangeCount == 1) {
|
|
|
|
KiAmdK6Mtrr.u.hw.mtrr1.base = AmdK6Regions[i].BaseAddress >> 17;
|
|
KiAmdK6Mtrr.u.hw.mtrr1.mask = RangeMask >> 17;
|
|
KiAmdK6Mtrr.u.hw.mtrr1.type = AMDK6_MTRR_TYPE_WC;
|
|
dwWcRangeCount++;
|
|
|
|
} else {
|
|
|
|
//
|
|
// Should never happen! This should have been caught in
|
|
// the calling routine.
|
|
//
|
|
|
|
DBGMSG ("AmdK6MtrrCommitChanges: Not enough MTRR registers to satisfy region table!\n");
|
|
|
|
return STATUS_NOT_SUPPORTED;
|
|
}
|
|
}
|
|
}
|
|
|
|
//
|
|
// Commit the changes to hardware.
|
|
//
|
|
|
|
KiLoadMTRR(NULL);
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
VOID
|
|
KiAmdK6MtrrWRMSR (
|
|
VOID
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
Write the AMD K6 MTRRs.
|
|
|
|
Note: Access to KiAmdK6Mtrr has been synchronized around this
|
|
call.
|
|
|
|
Arguments:
|
|
|
|
None.
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
--*/
|
|
|
|
{
|
|
//
|
|
// Write the MTRRs
|
|
//
|
|
|
|
WRMSR (AMDK6_MTRR_MSR, KiAmdK6Mtrr.u.QuadPart);
|
|
}
|
|
|
|
|