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132 lines
3.0 KiB
132 lines
3.0 KiB
/*++
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Copyright (c) 2001 Microsoft Corporation
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Module Name:
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shpcmasks.c
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Abstract:
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This module contains global data indicating the type of each of the
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bits in the SHPC register set.
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Author:
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Davis Walker (dwalker) 2 Feb 2001
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Revision History:
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--*/
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#include "hpsp.h"
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UCHAR ConfigWriteMask[] = {
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0x00,
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0x00, // Capability Header
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0xFF, // DwordSelect
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0x00, // Pending
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0xFF,
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0xFF,
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0xFF,
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0xFF // Data
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};
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//
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// Any bit set to 1 in this mask is RWC, so writing 1 to it will cause
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// it to be cleared. All writes to these bits (other than those
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// explicitly designed to clear these bits) must be 0. The register
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// specific masks are defined in shpc.h.
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//
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ULONG RegisterWriteClearMask[] = {
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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ControllerMaskRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC,
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SlotRWC
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};
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//
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// Any bit set to 1 in this mask is read only. This is a combination of
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// registers that are spec-defined to be read only and those that are
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// reserved, since we are emulating a nice controller that ignores writes
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// to reserved registers.
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// TODO be a mean controller.
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//
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ULONG RegisterReadOnlyMask[] = {
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BaseOffsetRO,
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SlotsAvailDWord1RO | SlotsAvailDWord1RsvdP,
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SlotsAvailDWord2RO | SlotsAvailDWord2RsvdP,
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SlotConfigRO | SlotConfigRsvdP,
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BusConfigRO | BusConfigRsvdP,
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CommandStatusRO | CommandStatusRsvdP,
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IntLocatorRO,
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SERRLocatorRO,
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ControllerMaskRsvdP | ControllerMaskRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ,
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SlotRO | SlotRsvdP | SlotRsvdZ
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};
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