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219 lines
6.0 KiB
219 lines
6.0 KiB
/*--------------------------------------------------------------------------
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*
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* Copyright (C) Cyclades Corporation, 1996-2001.
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* All rights reserved.
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*
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* Cyclom-Y Bus/Port Driver
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*
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* This file: cd1400.h
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*
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* Description: This file contains the Cirrus CD1400 serial
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* controller related contants, macros, addresses,
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* etc.
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*
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* Notes: This code supports Windows 2000 and Windows XP,
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* x86 and ia64 processors.
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*
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* Complies with Cyclades SW Coding Standard rev 1.3.
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*
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*--------------------------------------------------------------------------
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*/
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/*-------------------------------------------------------------------------
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*
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* Change History
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*
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*--------------------------------------------------------------------------
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*
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*
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*--------------------------------------------------------------------------
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*/
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#ifndef CD1400
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#define CD1400 1
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/* max number of chars in the FIFO */
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#define MAX_CHAR_FIFO (12)
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/* Firmware Revision Code */
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#define REV_G 0x46
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/* CD1400 registers */
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/* Global Registers */
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#define GFRCR (2 * 0x40)
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#define CAR (2 * 0x68)
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#define GCR (2 * 0x4b)
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#define SVRR (2 * 0x67)
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#define RICR (2 * 0x44)
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#define TICR (2 * 0x45)
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#define MICR (2 * 0x46)
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#define RIR (2 * 0x6b)
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#define TIR (2 * 0x6a)
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#define MIR (2 * 0x69)
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#define PPR (2 * 0x7e)
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/* Virtual Registers */
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#define RIVR (2 * 0x43)
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#define TIVR (2 * 0x42)
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#define MIVR (2 * 0x41)
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#define TDR (2 * 0x63)
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#define RDSR (2 * 0x62)
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#define MISR (2 * 0x4c)
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#define EOSRR (2 * 0x60)
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/* Channel Registers */
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#define LIVR (2 * 0x18)
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#define CCR (2 * 0x05)
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#define SRER (2 * 0x06)
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#define COR1 (2 * 0x08)
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#define COR2 (2 * 0x09)
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#define COR3 (2 * 0x0a)
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#define COR4 (2 * 0x1e)
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#define COR5 (2 * 0x1f)
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#define CCSR (2 * 0x0b)
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#define RDCR (2 * 0x0e)
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#define SCHR1 (2 * 0x1a)
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#define SCHR2 (2 * 0x1b)
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#define SCHR3 (2 * 0x1c)
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#define SCHR4 (2 * 0x1d)
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#define SCRL (2 * 0x22)
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#define SCRH (2 * 0x23)
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#define LNC (2 * 0x24)
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#define MCOR1 (2 * 0x15)
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#define MCOR2 (2 * 0x16)
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#define RTPR (2 * 0x21)
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#define MSVR1 (2 * 0x6c)
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#define MSVR2 (2 * 0x6d)
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#define PVSR (2 * 0x6f)
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#define RBPR (2 * 0x78)
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#define RCOR (2 * 0x7c)
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#define TBPR (2 * 0x72)
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#define TCOR (2 * 0x76)
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/* Register Settings */
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/* Channel Access Register (CAR) */
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#define CHAN0 0x00
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#define CHAN1 0x01
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#define CHAN2 0x02
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#define CHAN3 0x03
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/* Channel Option Register 1 (COR1) */
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#define COR1_NONE_PARITY 0x10
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#define COR1_ODD_PARITY 0xc0
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#define COR1_EVEN_PARITY 0x40
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#define COR1_MARK_PARITY 0xb0
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#define COR1_SPACE_PARITY 0x30
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#define COR1_PARITY_MASK 0xf0
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#define COR1_PARITY_ENABLE_MASK 0x60
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#define COR1_1_STOP 0x00
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#define COR1_1_5_STOP 0x04
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#define COR1_2_STOP 0x08
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#define COR1_STOP_MASK 0x0c
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#define COR1_5_DATA 0x00
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#define COR1_6_DATA 0x01
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#define COR1_7_DATA 0x02
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#define COR1_8_DATA 0x03
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#define COR1_DATA_MASK 0x03
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/* Channel Option Register 2 (COR2) */
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#define IMPL_XON 0x80
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#define AUTO_TXFL 0x40
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#define EMBED_TX_ENABLE 0x20
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#define LOCAL_LOOP_BCK 0x10
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#define REMOTE_LOOP_BCK 0x08
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#define RTS_AUT_OUTPUT 0x04
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#define CTS_AUT_ENABLE 0x02
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/* Channel Option Register 3 (COR3) */
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#define SPL_CH_DRANGE 0x80 /* special character detect range */
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#define SPL_CH_DET1 0x40 /* enable special char. detect on SCHR4-SCHR3 */
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#define FL_CTRL_TRNSP 0x20 /* Flow Control Transparency */
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#define SPL_CH_DET2 0x10 /* Enable spl char. detect on SCHR2-SCHR1 */
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#define REC_FIFO_12CH 0x0c /* Receive FIFO threshold= 12 chars */
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/* Global Configuration Register (GCR) values */
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#define GCR_CH0_IS_SERIAL 0x00
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/* Prescaler Period Register (PPR) values */
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#define CLOCK_20_1MS 0x27
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#define CLOCK_25_1MS 0x31
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#define CLOCK_60_1MS 0x75
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/* Channel Command Register (CCR) values */
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#define CCR_RESET_CHANNEL 0x80
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#define CCR_RESET_CD1400 0x81
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#define CCR_FLUSH_TXFIFO 0x82
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#define CCR_CORCHG_COR1 0x42
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#define CCR_CORCHG_COR2 0x44
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#define CCR_CORCHG_COR1_COR2 0x46
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#define CCR_CORCHG_COR3 0x48
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#define CCR_CORCHG_COR3_COR1 0x4a
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#define CCR_CORCHG_COR3_COR2 0x4c
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#define CCR_CORCHG_COR1_COR2_COR3 0x4e
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#define CCR_SENDSC_SCHR1 0x21
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#define CCR_SENDSC_SCHR2 0x22
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#define CCR_SENDSC_SCHR3 0x23
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#define CCR_SENDSC_SCHR4 0x24
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#define CCR_DIS_RX 0x11
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#define CCR_ENA_RX 0x12
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#define CCR_DIS_TX 0x14
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#define CCR_ENA_TX 0x18
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#define CCR_DIS_TX_RX 0x15
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#define CCR_DIS_TX_ENA_RX 0x16
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#define CCR_ENA_TX_DIS_RX 0x19
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#define CCR_ENA_TX_RX 0x1a
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/* Service Request Enable Register (SRER) values */
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#define SRER_TXRDY 0x04
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#define SRER_TXMPTY 0x02
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// Read from CD1400 registers
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#define CD1400_READ(ChipAddress,IsPci,Register) \
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(READ_REGISTER_UCHAR((ChipAddress)+((Register)<<(IsPci))))
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// Write to CD1400 registers
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#define CD1400_WRITE(ChipAddress,IsPci,Register,Value) \
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do \
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{ \
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WRITE_REGISTER_UCHAR( \
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(ChipAddress)+ ((Register) << (IsPci)), \
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(UCHAR)(Value) \
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); \
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} while (0);
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#define CD1400_DISABLE_ALL_INTERRUPTS(ChipAddress,IsPci,CdChannel) \
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do \
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{ \
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CD1400_WRITE((ChipAddress),(IsPci),CAR,(CdChannel & 0x03)); \
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CD1400_WRITE((ChipAddress),(IsPci),SRER,0x00); \
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\
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} while (0);
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#endif /* CD1400 */
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