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355 lines
17 KiB
355 lines
17 KiB
/******************************************************************************
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*
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* $Workfile: 16cx5x.h $
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*
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* $Author: Golden $
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*
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* $Revision: 6 $
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*
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* $Modtime: 10/11/99 14:21 $
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*
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* Description: Contains private 16Cx9x UART family definitions.
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*
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******************************************************************************/
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#if !defined(_16CX5X_H) /* _16CX5X.H */
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#define _16CX5X_H
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/******************************************************************************
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* UART REGISTERS
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******************************************************************************/
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#define TRANSMIT_HOLDING_REGISTER 0x00 /* Write Only. */
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#define RECEIVE_BUFFER_REGISTER 0x00 /* Read Only. */
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#define DIVISOR_LATCH_LSB 0x00 /* Read/Write When DLAB is Set. */
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#define DIVISOR_LATCH_MSB 0x01 /* Read/Write When DLAB is Set. */
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#define INTERRUPT_ENABLE_REGISTER 0x01 /* Read/Write. */
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#define FIFO_CONTROL_REGISTER 0x02 /* Write Only. */
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#define INTERRUPT_IDENT_REGISTER 0x02 /* Read Only. */
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#define LINE_CONTROL_REGISTER 0x03 /* Read/Write. */
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#define MODEM_CONTROL_REGISTER 0x04 /* Read/Write. */
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#define LINE_STATUS_REGISTER 0x05 /* Read Only. */
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#define MODEM_STATUS_REGISTER 0x06 /* Read Only. */
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#define SCRATCH_PAD_REGISTER 0x07 /* Read/Write. */
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/******************************************************************************
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* THR: Transmittter Holding Register - WRITE ONLY
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******************************************************************************/
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#define THR TRANSMIT_HOLDING_REGISTER
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/******************************************************************************
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* RBR: Receive Buffer Register - READ ONLY
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******************************************************************************/
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#define RBR RECEIVE_BUFFER_REGISTER
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/******************************************************************************
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* IER: Interrupt Enable Register - READ/WRITE
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******************************************************************************/
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#define IER INTERRUPT_ENABLE_REGISTER
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#define IER_INT_RDA 0x01 /* Bit 0: Enable Receive Data Available Interrupt (RXRDY). */
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#define IER_INT_THR 0x02 /* Bit 1: Enable Transmitter Holding Register Empty Interrupt (THRE). */
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#define IER_INT_RLS 0x04 /* Bit 2: Enable Receiver Line Status Interrupt (RXSTAT). */
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#define IER_INT_MS 0x08 /* Bit 3: Enable Modem Status Interrupt (MODEM). */
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#define IER_SLEEP_EN 0x10 /* Bit 4: Enable Sleep Mode (16750+). */
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#define IER_ALTSLEEP_EN 0x20 /* Bit 5: Enable Low Power Mode (16750+). */
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#define IER_SPECIAL_CHR 0x20 /* Bit 5: Enable Level 5 Interupts - Special Char Detect (16950+ Enhanced Mode) */
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#define IER_INT_RTS 0x40 /* Bit 6: Enable RTS Interrupt Mask (16950+ Enhanced Mode). */
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#define IER_INT_CTS 0x80 /* Bit 7: Enable CTS Interrupt Mask (16950+ Enhanced Mode). */
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/******************************************************************************
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* FCR: FIFO Control Register - WRITE ONLY
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******************************************************************************/
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#define FCR FIFO_CONTROL_REGISTER
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#define FCR_FIFO_ENABLE 0x01 /* Bit 0: Enable FIFOs */
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#define FCR_FLUSH_RX_FIFO 0x02 /* Bit 1: Clear Receive FIFO. */
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#define FCR_FLUSH_TX_FIFO 0x04 /* Bit 2: Clear Transmit FIFO. */
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#define FCR_DMA_MODE 0x08 /* Bit 3: DMA Mode Select. Change RXRDY & TXRDY Pins From Mode 1 to Mode 2. */
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/* 16C950 - 650 Mode only. */
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#define FCR_THR_TRIG_LEVEL_1 0x00 /* Bits 4:5 - Set Transmit FIFO Trigger Level to 16 Bytes in 650 mode. */
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#define FCR_THR_TRIG_LEVEL_2 0x10 /* Bits 4:5 - Set Transmit FIFO Trigger Level to 32 Bytes in 650 mode. */
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#define FCR_THR_TRIG_LEVEL_3 0x20 /* Bits 4:5 - Set Transmit FIFO Trigger Level to 64 Bytes in 650 mode. */
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#define FCR_THR_TRIG_LEVEL_4 0x30 /* Bits 4:5 - Set Transmit FIFO Trigger Level to 112 Bytes in 650 mode. */
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#define FCR_750_FIFO 0x20 /* Bit 5: Enable 64 Bit FIFO (16C750) */
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#define FCR_TRIG_LEVEL_1 0x00 /* Bits 6:7 - Set Receive FIFO Trigger Level to 1 Byte on 16C550A. */
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#define FCR_TRIG_LEVEL_2 0x40 /* Bits 6:7 - Set Receive FIFO Trigger Level to 4 Bytes on 16C550A. */
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#define FCR_TRIG_LEVEL_3 0x80 /* Bits 6:7 - Set Receive FIFO Trigger Level to 8 Bytes on 16C550A. */
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#define FCR_TRIG_LEVEL_4 0xC0 /* Bits 6:7 - Set Receive FIFO Trigger Level to 16 Bytes on 16C550A. */
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/******************************************************************************
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* IIR: Interrupt Identification Register. or ISR: Interrupt Status Register - READ ONLY
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******************************************************************************/
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#define IIR INTERRUPT_IDENT_REGISTER
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#define IIR_NO_INT_PENDING 0x01 /* Bit 0: No Interrupt Pending. */
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/* Interrupt Priorities */
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#define IIR_RX_STAT_MSK 0x06 /* Bits 1:2 - Receiver Line Status Interrupt (Level 1 - Highest). */
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#define IIR_RX_MSK 0x04 /* Bits 1:2 - Received Data Available Interrupt (Level 2a). */
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#define IIR_RXTO_MSK 0x0C /* Bits 1:2 - Received Data Time Out Interrupt (Level 2b). */
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#define IIR_TX_MSK 0x02 /* Bits 1:2 - Transmitter Holding Empty Interrupt (Level 3). */
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#define IIR_MODEM_MSK 0x00 /* Bits 1:2 - Modem Status Interrupt (Level 4). */
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#define IIR_TO_INT_PENDING 0x08 /* Bit 3: Time-out Interrupt Pending. */
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#define IIR_S_CHR_MSK 0x10 /* Bit 4: Special Char (16C950 - Enhanced Mode) (Level 5) */
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#define IIR_CTS_RTS_MSK 0x20 /* Bit 4: CTS/RTS Interrupt (16C950 - Enhanced Mode)(Level 6 - Lowest) */
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#define IIR_64BYTE_FIFO 0x20 /* Bit 5: 64 Byte FIFO Enabeled (16C750). */
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#define IIR_NO_FIFO 0x00 /* Bits 6:7 - No FIFO. */
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#define IIR_FIFO_UNUSABLE 0x40 /* Bits 6:7 - FIFO Enabled But Unusable (16550 Only). */
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#define IIR_FIFO_ENABLED 0xC0 /* Bits 6:7 - FIFO Enabled And Usable. */
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#define IIR_FIFO_MASK 0xC0 /* Bits 6:7 - Bit mask, */
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/******************************************************************************
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* LCR: Line Control Register. - READ/WRITE
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******************************************************************************/
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#define LCR LINE_CONTROL_REGISTER
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#define LCR_DATALEN_5 0x00 /* Bits 0:1 - Sets Data Word Length to 5 Bits. */
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#define LCR_DATALEN_6 0x01 /* Bits 0:1 - Sets Data Word Length to 6 Bits. */
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#define LCR_DATALEN_7 0x02 /* Bits 0:1 - Sets Data Word Length to 7 Bits. */
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#define LCR_DATALEN_8 0x03 /* Bits 0:1 - Sets Data Word Length to 8 Bits. */
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#define LCR_STOPBITS 0x04 /* Bit 2 - 2 Stop Bits for 6,7,8 Bit Words or 1.5 Stop Bits for 5 Bit Words. */
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#define LCR_NO_PARITY 0x00 /* Bits 3:5 - No Parity. */
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#define LCR_ODD_PARITY 0x08 /* Bits 3:5 - Odd Parity. */
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#define LCR_EVEN_PARITY 0x18 /* Bits 3:5 - Even Parity. */
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#define LCR_MARK_PARITY 0x28 /* Bits 3:5 - High Parity - Mark (Forced to 1). */
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#define LCR_SPACE_PARITY 0x38 /* Bits 3:5 - Low Parity - Space (Forced to 0). */
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#define LCR_TX_BREAK 0x40 /* Bit 6 - Set Break Enable. */
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#define LCR_DLAB 0x80 /* Divisor Latch Access Bit - Allows Access To Low And High Divisor Registers. */
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#define LCR_ACCESS_650 0xBF /* Access to 650 Compatiblity Registers (16C950) */
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/******************************************************************************
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* MCR: Modem Control Register - READ/WRITE
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******************************************************************************/
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#define MCR MODEM_CONTROL_REGISTER
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#define MCR_SET_DTR 0x01 /* Bit 0: Force DTR (Data Terminal Ready). */
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#define MCR_SET_RTS 0x02 /* Bit 1: Force RTS (Request To Send). */
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#define MCR_OUT1 0x04 /* Bit 2: Aux Output 1. */
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#define MCR_OUT2 0x08 /* Bit 3: Aux Output 2. */
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#define MCR_INT_EN 0x08 /* Bit 3: (16C950) */
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#define MCR_LOOPBACK 0x10 /* Bit 4: Enable Loopback Mode. */
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#define MCR_750CTSRTS 0x20 /* Bit 5: Automatic Flow Control Enabled RTS/CTS (16C750) */
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#define MCR_XON_ANY 0x20 /* Bit 5: Xon-Any is enabled (16C950 - Enhanced Mode) */
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#define MCR_IRDA_MODE 0x40 /* Bit 6: Enable IrDA mode - requires 16x clock. (16C950 - Enhanced Mode) */
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#define MCR_CPR_EN 0x80 /* Bit 7: Enable Baud Prescale (16C950 - Enhanced Mode) */
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/******************************************************************************
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* LSR: Line Status Register - READ ONLY
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******************************************************************************/
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#define LSR LINE_STATUS_REGISTER
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#define LSR_RX_DATA 0x01 /* Bit 0: Data Ready. */
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#define LSR_ERR_OE 0x02 /* Bit 1: Overrun Error. */
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#define LSR_ERR_PE 0x04 /* Bit 2: Parity Error. */
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#define LSR_RX_BIT9 0x04 /* Bit 2: 9th Rx Data Bit (16C950 - 9 bit data mode only) */
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#define LSR_ERR_FE 0x08 /* Bit 3: Framing Error. */
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#define LSR_ERR_BK 0x10 /* Bit 4: Break Interrupt. */
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#define LSR_THR_EMPTY 0x20 /* Bit 5: Empty Transmitter Holding Register. */
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#define LSR_TX_EMPTY 0x40 /* Bit 6: Empty Data Holding Registers. */
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#define LSR_ERR_DE 0x80 /* Bit 7: Error In Received FIFO. */
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#define LSR_ERR_MSK LSR_ERR_OE + LSR_ERR_PE + LSR_ERR_FE + LSR_ERR_BK + LSR_ERR_DE
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/******************************************************************************
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* MSR: Modem Status Register - READ ONLY
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******************************************************************************/
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#define MSR MODEM_STATUS_REGISTER
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#define MSR_CTS_CHANGE 0x01 /* Bit 0: Delta Clear To Send. */
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#define MSR_DSR_CHANGE 0x02 /* Bit 1: Delta Data Set Ready. */
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#define MSR_RI_DROPPED 0x04 /* Bit 2: Trailing Edge Ring Indicator (A Change From Low To High). */
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#define MSR_DCD_CHANGE 0x08 /* Bit 3: Delta Data Carrier Detect. */
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#define MSR_CTS 0x10 /* Bit 4: Clear To Send (Current State of CTS). */
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#define MSR_DSR 0x20 /* Bit 5: Data Set Ready (Current State of DSR). */
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#define MSR_RI 0x40 /* Bit 6: Ring Indicator (Current State of RI). */
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#define MSR_DCD 0x80 /* Bit 7: Data Carrier Detect (Current State of DCD). */
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/******************************************************************************
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* SR: Scratch Pad Register - READ/WRITE
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******************************************************************************/
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#define SPR SCRATCH_PAD_REGISTER
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#define SPR_TX_BIT9 0x01 /* Bit 0: 9th Tx Data Bit (16C950 - 9 bit data mode only) */
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/******************************************************************************
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* Oxford Semiconductor's 16C950 UART Specific Macros
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******************************************************************************/
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/******************************************************************************
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* 650 COMPATIBLE REGISTERS
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* To Access these registers LCR MUST be set to 0xBF
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******************************************************************************/
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#define EFR 0x02 /* Enhanced Features Register. */
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/* Bits 0:1 In band transmit flow control mode. */
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/* 10.11.1999 ARG - ESIL 0927 */
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/* Definitions for Tx XON/XOFF bits in the EFR corrected to use bits 0:1 */
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#define EFR_TX_XON_XOFF_DISABLED 0x00 /* Bits 0:1 Transmit XON/XOFF Disabled. */
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#define EFR_TX_XON_XOFF_2 0x01 /* Bits 0:1 Transmit XON/XOFF Enabled using chars in XON2 and XOFF2 */
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#define EFR_TX_XON_XOFF_1 0x02 /* Bits 0:1 Transmit XON/XOFF Enabled using chars in XON1 and XOFF1 */
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/* Bits 2:3 In band receive flow control mode. */
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/* 10.11.1999 ARG - ESIL 0927 */
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/* Definitions for Rx XON/XOFF bits in the EFR corrected to use bits 2:3 */
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#define EFR_RX_XON_XOFF_DISABLED 0x00 /* Bits 2:3 Receive XON/XOFF Disabled. */
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#define EFR_RX_XON_XOFF_2 0x04 /* Bits 2:3 Receive XON/XOFF Enabled using chars in XON2 and XOFF2 */
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#define EFR_RX_XON_XOFF_1 0x08 /* Bits 2:3 Receive XON/XOFF Enabled using chars in XON1 and XOFF1 */
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#define EFR_ENH_MODE 0x10 /* Bit 4: Enable Enhanced Mode. */
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#define EFR_SPECIAL_CHR 0x20 /* Bit 5: Enable Special Character Detect. */
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#define EFR_RTS_FC 0x40 /* Bit 6: Enable Automatic RTS Flow Control. */
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#define EFR_CTS_FC 0x80 /* Bit 7: Enable Automatic CTS Flow Control. */
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#define XON1 0x04 /* XON Character 1 */
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#define XON2 0x05 /* XON Character 2 */
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#define XOFF1 0x06 /* XOFF Character 1 */
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#define XOFF2 0x07 /* XOFF Character 2 */
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#define SPECIAL_CHAR1 XON1 /* Special Character 1 (16C950 - 9 bit data mode only) */
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#define SPECIAL_CHAR2 XON2 /* Special Character 2 (16C950 - 9 bit data mode only) */
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#define SPECIAL_CHAR3 XOFF1 /* Special Character 3 (16C950 - 9 bit data mode only) */
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#define SPECIAL_CHAR4 XOFF2 /* Special Character 4 (16C950 - 9 bit data mode only) */
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/*****************************************************************************/
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/* 950 SPECIFIC REGISTERS */
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#define ASR 0x01 /* Advanced Status Register */
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#define ASR_TX_DISABLED 0x01 /* Transmitter Disabled By In-Band Flow Control (XOFF). */
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#define ASR_RTX_DISABLED 0x02 /* Remote Transmitter Disabled By In-Band Flow Control (XOFF). */
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#define ASR_RTS 0x04 /* Remote Transmitter Disabled By RTS Out-Of-Band Flow Ctrl. */
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#define ASR_DTR 0x08 /* Remote Transmitter Disabled By DTR Out-Of-Band Flow Ctrl. */
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#define ASR_SPECIAL_CHR 0x10 /* Special Character Detected in the RHR. */
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#define ASR_FIFO_SEL 0x20 /* Bit reflects the unlatched state of the FIFOSEL pin. */
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#define ASR_FIFO_SIZE 0x40 /* Bit not set: FIFOs are 16 Deep. Bit Set: FIFOs are 128 Deep */
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#define ASR_TX_IDLE 0x80 /* Transmitter is Idle. */
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/* Receiver FIFO Fill Level Register */
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#define RFL 0x03 /* Minimum characters in the Rx FIFO. */
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/* Transmitter FIFO Fill Level Register */
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#define TFL 0x04 /* Maximum characters in the Tx FIFO. */
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/* Indexed Control Register Set Access Register */
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#define ICR LINE_STATUS_REGISTER
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/*****************************************************************************/
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/*INDEXED CONTROL REGISTER SET OFFSETS */
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/* Advanced Control Register */
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#define ACR 0x00 /* Aditional Control Register. */
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#define ACR_DISABLE_RX 0x01 /* Receiver Disable. */
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#define ACR_DISABLE_TX 0x02 /* Tranmitter Disable. */
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#define ACR_DSR_FC 0x04 /* Enable Automatic DSR Flow Control */
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#define ACR_DTR_FC 0x08 /* Enable Automatic DTR Flow Control */
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#define ACR_DSRDTR_FC 0x0C /* Enable Automatic DSR/DTR Flow Control. */
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#define ACR_DTRDFN_MSK 0x18 /* */
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#define ACR_TRIG_LEV_EN 0x20 /* Enable 16950 Enhanced Interrupt & trig. levels defined by RTH, TTL, FCL & FCH. */
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#define ACR_ICR_READ_EN 0x40 /* Enables Read Accesss to the Indexed Control Registers. */
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#define ACR_ASR_EN 0x80 /* Additional Status Enable: Enables ASR, TFL, RFL. */
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/* Clock Prescaler Register */
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#define CPR 0x01 /* Clock Prescaler Register. */
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#define CPR_FRACT_MSK 0x07 /* Mask for fractional part of clock prescaler. */
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#define CPR_INTEGER_MSK 0xF8 /* Mask for integer part of clock prescaler. */
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#define TCR 0x02 /* Times Clock Register to operate at baud rates to 50Mbps. */
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#define CKS 0x03 /* Clock Select Register. */
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#define TTL 0x04 /* Transmitter Interrupt Trigger Level. */
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#define RTL 0x05 /* Receiver Interrupt Trigger Level. */
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#define FCL 0x06 /* Flow Control Lower Trigger Level. */
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#define FCH 0x07 /* Flow Control Higher Trigger Level. */
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/* Identification Registers */
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#define ID1 0x08 /* 0x16 for OX16C950 */
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#define ID2 0x09 /* 0xC9 for OX16C950 */
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#define ID3 0x0A /* 0x50 for OX16C950 */
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#define REV 0x0B /* UART Revision: 0x1 for integrated 16C950 in rev A of OX16PCI954. */
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#define UART_TYPE_950 0x00
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#define UART_TYPE_952 0x02
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#define UART_TYPE_954 0x04
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#define UART_TYPE_NON95x 0xF0
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#define UART_REV_A 0x00
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#define UART_REV_B 0x01
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#define UART_REV_C 0x02
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#define UART_REV_D 0x03
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/* Channel Soft Reset Register */
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#define CSR 0x0C /* Channel Soft Reset Register - Write 0x0 to reset the channel. */
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/* Nine-Bit Mode Register */
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#define NMR 0x0D /* Nine-Bit Mode Register */
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#define NMR_9BIT_EN 0x01 /* Enable 9-Bit mode. */
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#define MDM 0x0E /* Modem Disable Mask */
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#define RFC 0x0F /* Readable FCR. - Current state of FCR Register. */
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#define GDS 0x10 /* Good Data Status Register. */
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#define CTR 0xFF /* Register for Testing purposes only - Must not use. */
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/******************************************************************************/
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/* Local Configuration Register Offsets */
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#define LCC 0x00 /* Local Configuration and Control Regiseter */
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#define MIC 0x04 /* Multi-purpose IO Configuration Register */
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#define LT1 0x08 /* Local Bus Configuration Register 1 - Local Bus Timing Parameter Register. */
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#define LT2 0x0C /* Local Bus Configuration Register 2 - Local Bus Timing Parameter Register. */
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#define URL 0x10 /* UART Receiver FIFO Levels. */
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#define UTL 0x14 /* UART Transmitter FIFO Levels. */
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#define UIS 0x18 /* UART Interrupt Source Register. */
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#define GIS 0x1C /* Global Interrupt Status Register. */
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/* Supported 950s */
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#define MIN_SUPPORTED_950_REV UART_REV_A
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#define MAX_SUPPORTED_950_REV UART_REV_B
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/* Supported 952s */
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#define MIN_SUPPORTED_952_REV UART_REV_B
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#define MAX_SUPPORTED_952_REV UART_REV_B
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/* Supported 954s */
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#define MIN_SUPPORTED_954_REV UART_REV_A
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#define MAX_SUPPORTED_954_REV UART_REV_A
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/* Prototypes. */
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/* End of prototypes. */
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#endif /* End of 16CX5X.H */
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