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338 lines
11 KiB
338 lines
11 KiB
//+-------------------------------------------------------------------------
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//
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// Microsoft Windows
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//
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// Copyright (C) Microsoft Corporation, 1997 - 1999
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//
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// File: intel.h
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//
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//--------------------------------------------------------------------------
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#if !defined (___intel_h___)
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#define ___intel_h___
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#include "stddef.h"
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#include "ntddk.h"
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#include "ntdddisk.h"
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#include "ide.h"
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#define INTEL_PCI_VENDOR_ID ((USHORT)0x8086)
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#define PIIX_DEVICE_ID ((USHORT)0x1230)
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#define PIIX3_DEVICE_ID ((USHORT)0x7010)
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#define PIIX4_DEVICE_ID ((USHORT)0x7111)
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#define ICH_DEVICE_ID ((USHORT)0x2411)
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#define ICH0_DEVICE_ID ((USHORT)0x2421)
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#define ICH2_LOWEND_DEVICE_ID ((USHORT)0x2441)
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#define ICH2_MOBILE_DEVICE_ID ((USHORT)0x244A)
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#define ICH2_HIGHEND_DEVICE_ID ((USHORT)0x244B)
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#define ICH3_DEVICE_ID_1 ((USHORT)0x248A)
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#define ICH3_DEVICE_ID_2 ((USHORT)0x248B)
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#define ICH4_DEVICE_ID_1 ((USHORT)0x24C1)
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#define ICH4_DEVICE_ID_2 ((USHORT)0x24CA)
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#define ICH4_DEVICE_ID_3 ((USHORT)0x24CB)
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#define ICH5_DEVICE_ID_1 ((USHORT)0x24D1)
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#define ICH5_DEVICE_ID_2 ((USHORT)0x24DB)
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#define SINGLE_CHANNEL_IDE_DEVICE_ID ((USHORT)0x7199)
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#define IA64_IDE_CONTROLLER_DEVICE_ID ((USHORT)0x7601)
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#define IS_INTEL(vendorId) (vendorId == INTEL_PCI_VENDOR_ID)
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#define IS_PIIX(deviceId) (deviceId == PIIX_DEVICE_ID)
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#define IS_PIIX3(deviceId) (deviceId == PIIX3_DEVICE_ID)
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#define IS_PIIX4(deviceId) (deviceId == PIIX4_DEVICE_ID)
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#define IS_ICH_(deviceId) (deviceId == ICH_DEVICE_ID)
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#define IS_ICH0(deviceId) (deviceId == ICH0_DEVICE_ID || deviceId == IA64_IDE_CONTROLLER_DEVICE_ID)
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#define IS_ICH2_LOW(deviceId) (deviceId == ICH2_LOWEND_DEVICE_ID)
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#define IS_ICH2_MOBILE(deviceId) (deviceId == ICH2_MOBILE_DEVICE_ID)
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#define IS_ICH2_HIGH(deviceId) (deviceId == ICH2_HIGHEND_DEVICE_ID)
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#define IS_ICH2(deviceId) (IS_ICH2_LOW(deviceId) || IS_ICH2_MOBILE(deviceId) || IS_ICH2_HIGH(deviceId))
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#define IS_ICH3(deviceId) ((deviceId == ICH3_DEVICE_ID_1) || (deviceId == ICH3_DEVICE_ID_2))
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#define IS_ICH4(deviceId) ((deviceId == ICH4_DEVICE_ID_1) || (deviceId == ICH4_DEVICE_ID_2) || (deviceId == ICH4_DEVICE_ID_3))
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#define IS_ICH5(deviceId) ((deviceId == ICH5_DEVICE_ID_1) || (deviceId == ICH5_DEVICE_ID_2))
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#define IS_SINGLE_IDE(deviceId) (deviceId == SINGLE_CHANNEL_IDE_DEVICE_ID)
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#define IS_UDMA33_CONTROLLER(deviceId) (IS_PIIX4(deviceId) || IS_ICH0(deviceId) || IS_ICH_(deviceId) || IS_SINGLE_IDE(deviceId) || IS_ICH2(deviceId) || IS_ICH3(deviceId) || IS_ICH4(deviceId) || IS_ICH5(deviceId))
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#define IS_UDMA66_CONTROLLER(deviceId) (IS_ICH_(deviceId) || IS_ICH2(deviceId) || IS_ICH3(deviceId) || IS_ICH4(deviceId) || IS_ICH5(deviceId))
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#define IS_UDMA100_CONTROLLER(deviceId) (IS_ICH2_MOBILE(deviceId) || IS_ICH2_HIGH(deviceId) || IS_ICH3(deviceId) || IS_ICH4(deviceId) || IS_ICH5(deviceId))
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#define IS_UDMA_CONTROLLER(deviceId) (IS_UDMA33_CONTROLLER(deviceId) || IS_UDMA66_CONTROLLER(deviceId) || IS_UDMA100_CONTROLLER(deviceId))
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#pragma pack(1)
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typedef struct _PIIX_SPECIAL_TIMING_REGISTER {
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union {
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UCHAR AsUChar;
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struct {
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UCHAR FastTimingBankDriveSelect:1;
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UCHAR IoReadySamplePointEnableDriveSelect:1;
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UCHAR PrefetchAndPostingEnable:1;
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UCHAR DmaTimingEnable:1;
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} b;
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};
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} PIIX_SPECIAL_TIMING_REGISTER, *PPIIX_SPECIAL_TIMING_REGISTER;
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typedef struct _PIIX_TIMING_REGISTER {
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union {
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struct {
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union {
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struct {
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UCHAR Device0SpecialTiming:4;
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UCHAR Device1SpecialTiming:4;
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} n;
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struct {
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UCHAR FastTimingBankDriveSelect0:1;
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UCHAR IoReadySamplePointEnableDriveSelect0:1;
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UCHAR PrefetchAndPostingEnable0:1;
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UCHAR DmaTimingEnable0:1;
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UCHAR FastTimingBankDriveSelect1:1;
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UCHAR IoReadySamplePointEnableDriveSelect1:1;
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UCHAR PrefetchAndPostingEnable1:1;
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UCHAR DmaTimingEnable1:1;
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} b;
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};
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UCHAR RecoveryTime:2;
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UCHAR Reserved:2;
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UCHAR IoReadySamplePoint:2;
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UCHAR SlaveTimingEnable:1;
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UCHAR ChannelEnable:1;
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}b;
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USHORT AsUShort;
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};
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} PIIX_TIMING_REGISTER, *PPIIX_TIMING_REGISTER;
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typedef struct _PIIX3_SLAVE_TIMING_REGISTER {
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union {
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struct {
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UCHAR Channel0RecoveryTime:2;
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UCHAR Channel0IoReadySamplePoint:2;
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UCHAR Channel1RecoveryTime:2;
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UCHAR Channel1IoReadySamplePoint:2;
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} b;
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UCHAR AsUChar;
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};
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} PIIX3_SLAVE_TIMING_REGISTER, *PPIIX3_SLAVE_TIMING_REGISTER;
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typedef struct _PIIX4_UDMA_CONTROL_REGISTER {
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union {
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struct {
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UCHAR Channel0Drive0UdmaEnable:1;
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UCHAR Channel0Drive1UdmaEnable:1;
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UCHAR Channel1Drive0UdmaEnable:1;
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UCHAR Channel1Drive1UdmaEnable:1;
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UCHAR Reserved:4;
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} b;
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UCHAR AsUChar;
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};
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}PIIX4_UDMA_CONTROL_REGISTER, *PPIIX4_UDMA_CONTROL_REGISTER;
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typedef struct _PIIX4_UDMA_TIMING_REGISTER {
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union {
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struct {
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UCHAR Drive0CycleTime:2;
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UCHAR Reserved0:2;
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UCHAR Drive1CycleTime:2;
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UCHAR Reserved1:2;
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} b;
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UCHAR AsUChar;
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};
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}PIIX4_UDMA_TIMING_REGISTER, *PPIIX4_UDMA_TIMING_REGISTER;
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typedef struct _ICH_IO_CONFIG_REGISTER {
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union {
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USHORT AsUShort;
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struct {
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USHORT PrimaryMasterBaseClock:1;
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USHORT PrimarySlaveBaseClock:1;
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USHORT SecondaryMasterBaseClock:1;
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USHORT SecondarySlaveBaseClock:1;
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USHORT PrimaryMasterCableReady:1;
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USHORT PrimarySlaveCableReady:1;
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USHORT SecondaryMasterCableReady:1;
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USHORT SecondarySlaveCableReady:1;
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USHORT Reserved1:2;
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USHORT WriteBufferPingPongEnable:1;
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USHORT Reserved2:1;
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USHORT FastPrimaryMasterBaseClock:1;
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USHORT FastPrimarySlaveBaseClock:1;
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USHORT FastSecondaryMasterBaseClock:1;
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USHORT FastSecondarySlaveBaseClock:1;
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/***
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union {
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USHORT Reserved3:4;
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struct {
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USHORT FastPrimaryMasterBaseClock:1;
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USHORT FastPrimarySlaveBaseClock:1;
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USHORT FastSecondaryMasterBaseClock:1;
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USHORT FastSecondarySlaveBaseClock:1;
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}f;
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};
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***/
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} b;
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}; // offset 54
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}ICH_IO_CONFIG_REGISTER, *PICH_IO_CONFIG_REGISTER;
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#define PIIX4_UDMA_MODE2_TIMING 2
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#define PIIX4_UDMA_MODE1_TIMING 1
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#define PIIX4_UDMA_MODE0_TIMING 0
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typedef struct _PIIX4_PCI_CONFIG_DATA {
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PCIIDE_CONFIG_HEADER h;
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PIIX_TIMING_REGISTER Timing[MAX_IDE_CHANNEL]; // offset 40, 41, 42, 43
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PIIX3_SLAVE_TIMING_REGISTER SlaveTiming; // offset 44
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UCHAR Reserved0[3]; // offset 45, 46, 47
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PIIX4_UDMA_CONTROL_REGISTER UdmaControl; // offset 48
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UCHAR Reserved1[1]; // offset 49
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PIIX4_UDMA_TIMING_REGISTER UdmaTiming[MAX_IDE_CHANNEL]; // offset 4a, 4b
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} PIIX4_PCI_CONFIG_DATA, *PPIIX4_PCI_CONFIG_DATA;
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#define ICH2_UDMA_MODE5_TIMING 1
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#define ICH_UDMA_MODE4_TIMING 2
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#define ICH_UDMA_MODE3_TIMING 1
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typedef enum {
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NoUdma=0,
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Udma33,
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Udma66,
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Udma100
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}CONTROLLER_MODE;
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typedef struct _ICH_PCI_CONFIG_DATA {
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PIIX4_PCI_CONFIG_DATA Piix4PciConfigData;
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UCHAR Reserved2[8]; // offset 4c-53
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ICH_IO_CONFIG_REGISTER IoConfig; // offset 54
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} ICH_PCI_CONFIG_DATA, *PICH_PCI_CONFIG_DATA;
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#pragma pack()
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typedef struct _DEVICE_EXTENSION {
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USHORT DeviceId;
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ULONG TransferModeSupported[MAX_IDE_CHANNEL][MAX_IDE_DEVICE];
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BOOLEAN CableReady[MAX_IDE_CHANNEL][MAX_IDE_DEVICE];
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CONTROLLER_MODE UdmaController;
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IDENTIFY_DATA IdentifyData[MAX_IDE_DEVICE];
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} DEVICE_EXTENSION, *PDEVICE_EXTENSION;
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#define PIIX_TIMING_CHANNEL_ENABLE 0x8000
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#define PIIX_TIMING_SLAVE_TIMING_ENABLE 0x4000
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#define PIIX_TIMING_DMA_TIMING_ENABLE(x) (x ? 0x0008 : 0)
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#define PIIX_TIMING_PREFETCH_AND_POSTING_ENABLE(x) (x ? 0x0004 : 0)
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#define PIIX_TIMING_IOREADY_SAMPLE_POINT_ENABLE(x) (x ? 0x0002 : 0)
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#define PIIX_TIMING_FAST_TIMING_BANK_ENABLE(x) (x ? 0x0001 : 0)
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#define UDMA_MASK(controller, cable, enableUdma66, mask) {\
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switch (controller) { \
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case Udma100: mask &= 0xffffffff;enableUdma66=1;break; \
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case Udma66: mask &= 0x0000ffff;break; \
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case Udma33: mask &= 0x00003fff;break; \
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default: mask &= 0x000007ff;break; \
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} \
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if (!(cable && enableUdma66)) { \
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mask &= 0x00003fff; \
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} \
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}
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typedef enum {
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PiixMode_NotPresent = 0,
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PiixMode_Mode0,
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PiixMode_Mode2,
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PiixMode_Mode3,
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PiixMode_Mode4,
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PiixMode_MaxMode
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} PIIX_TIMING_MODE;
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NTSTATUS
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DriverEntry(
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IN PDRIVER_OBJECT DriverObject,
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IN PUNICODE_STRING RegistryPath
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);
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NTSTATUS
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PiixIdeGetControllerProperties (
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IN PVOID DeviceExtension,
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IN PIDE_CONTROLLER_PROPERTIES ControllerProperties
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);
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IDE_CHANNEL_STATE
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PiixIdeChannelEnabled (
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IN PVOID DeviceHandle,
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IN ULONG Channel
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);
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BOOLEAN
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PiixIdeSyncAccessRequired (
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IN PVOID DeviceHandle
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);
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NTSTATUS
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PiixIdeTransferModeSelect (
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IN PDEVICE_EXTENSION DeviceExtension,
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IN OUT PPCIIDE_TRANSFER_MODE_SELECT TransferModeSelect
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);
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NTSTATUS
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PiixIdeUdmaModesSupported (
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IN IDENTIFY_DATA IdentifyData,
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IN OUT PULONG BestXferMode,
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IN OUT PULONG CurrentMode
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);
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#include "timing.h"
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#endif // ___intel_h___
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