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507 lines
20 KiB
507 lines
20 KiB
//***************************************************************************
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//
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// Module Name:
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//
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// TVP4020.h
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//
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// Abstract:
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//
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// This module contains the definitions for the P2 internal RAMDAC.
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//
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// Environment:
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//
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// Kernel mode
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//
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//
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// Copyright (c) 1995 AccelGraphics, Inc.
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//
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//***************************************************************************
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//
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// TI TVP4020 RAMDAC definitions
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// This set of registers resides at &(pCtrlRegs->ExternalVideo)
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//
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typedef struct _tvp4020_regs {
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RAMDAC_REG pciAddrWr; // 0x00 - palette/cursor RAM write address, Index Register
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RAMDAC_REG palData; // 0x01 - palette RAM data
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RAMDAC_REG pixelMask; // 0x02 - pixel read mask
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RAMDAC_REG pciAddrRd; // 0x03 - palette/cursor RAM read address
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RAMDAC_REG curColAddr; // 0x04 - cursor color address
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RAMDAC_REG curColData; // 0x05 - cursor color data
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RAMDAC_REG Reserved1; // 0x06 - reserved
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RAMDAC_REG Reserved2; // 0x07 - reserved
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RAMDAC_REG Reserved3; // 0x08 - reserved
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RAMDAC_REG Reserved4; // 0x09 - reserved
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RAMDAC_REG indexData; // 0x0A - indexed data
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RAMDAC_REG curRAMData; // 0x0B - cursor RAM data
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RAMDAC_REG cursorXLow; // 0x0C - cursor position X low byte
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RAMDAC_REG cursorXHigh; // 0x0D - cursor position X high byte
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RAMDAC_REG cursorYLow; // 0x0E - cursor position Y low byte
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RAMDAC_REG cursorYHigh; // 0x0F - cursor position Y high byte
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} TVP4020RAMDAC, *pTVP4020RAMDAC;
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//
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// macro declared by any function wishing to use the P2 internal RAMDAC . MUST be declared
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// after P2_DECL.
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//
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#define TVP4020_DECL \
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pTVP4020RAMDAC pTVP4020Regs = (pTVP4020RAMDAC)(hwDeviceExtension->pRamdac)
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//
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// use the following macros as the address to pass to the
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// VideoPortWriteRegisterUlong function
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//
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// Palette Access
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#define __TVP4020_PAL_WR_ADDR ((PULONG)&(pTVP4020Regs->pciAddrWr.reg))
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#define __TVP4020_PAL_RD_ADDR ((PULONG)&(pTVP4020Regs->pciAddrRd.reg))
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#define __TVP4020_PAL_DATA ((PULONG)&(pTVP4020Regs->palData.reg))
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//
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// Pixel mask
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//
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#define __TVP4020_PIXEL_MASK ((PULONG)&(pTVP4020Regs->pixelMask.reg))
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//
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// Access to the indexed registers
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//
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#define __TVP4020_INDEX_ADDR ((PULONG)&(pTVP4020Regs->pciAddrWr.reg))
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#define __TVP4020_INDEX_DATA ((PULONG)&(pTVP4020Regs->indexData.reg))
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//
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// Access to the Cursor
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//
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#define __TVP4020_CUR_RAM_WR_ADDR ((PULONG)&(pTVP4020Regs->pciAddrWr.reg))
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#define __TVP4020_CUR_RAM_RD_ADDR ((PULONG)&(pTVP4020Regs->palAddrRd.reg))
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#define __TVP4020_CUR_RAM_DATA ((PULONG)&(pTVP4020Regs->curRAMData.reg))
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#define __TVP4020_CUR_COL_ADDR ((PULONG)&(pTVP4020Regs->curColAddr.reg))
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#define __TVP4020_CUR_COL_DATA ((PULONG)&(pTVP4020Regs->curColData.reg))
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//
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// Cursor position control
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//
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#define __TVP4020_CURSOR_X_LSB ((PULONG)&(pTVP4020Regs->cursorXLow.reg))
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#define __TVP4020_CURSOR_X_MSB ((PULONG)&(pTVP4020Regs->cursorXHigh.reg))
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#define __TVP4020_CURSOR_Y_LSB ((PULONG)&(pTVP4020Regs->cursorYLow.reg))
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#define __TVP4020_CURSOR_Y_MSB ((PULONG)&(pTVP4020Regs->cursorYHigh.reg))
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// ----------------------Values for some direct registers-----------------------
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/********************************************************************************/
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/* DIRECT REGISTER - CURSOR POSITION CONTROL */
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/********************************************************************************/
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//
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// ** TVP4020_CUR_X_LSB
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// ** TVP4020_CUR_X_MSB
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// ** TVP4020_CUR_Y_LSB
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// ** TVP4020_CUR_Y_MSB
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// Default - undefined
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// Values written into those registers represent the BOTTOM-RIGHT corner
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// of the cursor. If 0 is in X or Y position - the cursor is off the screen
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// Only 12 bits are used, giving the range from 0 to 4095 ( 0x0000 - 0x0FFF)
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// The size of the cursor is (64,64) (0x40, 0x40)
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//
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#define TVP4020_CURSOR_OFFSCREEN 0x00 // Cursor offscreen
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/********************************************************************************/
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/* DIRECT REGISTER - CURSOR COLORS */
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/********************************************************************************/
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#define TVP4020_CURSOR_COLOR0 0x01
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#define TVP4020_CURSOR_COLOR1 0x02
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#define TVP4020_CURSOR_COLOR2 0x03
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/********************************************************************************/
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/* INDIRECT REGISTER - CURSOR CONTROL */
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/********************************************************************************/
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#define __TVP4020_CURSOR_CONTROL 0x06 // Indirect cursor control -
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// Default - 0x00
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#define TVP4020_CURSOR_SIZE_32 (0 << 6)// 32x32 cursor
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#define TVP4020_CURSOR_SIZE_64 (1 << 6)// 32x32 cursor
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#define TVP4020_CURSOR_32_SEL(i) ((i) << 4)// one of 4 32x32 cursors DABO: changed to << 4
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#define TVP4020_CURSOR_RAM_ADDRESS(x) (((x) & 0x03) << 2)// High bits of cursor RAM address
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#define TVP4020_CURSOR_RAM_MASK ((0x03) << 2) // Mask for high bits of cursor RAM address
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// DABO: Added constants for cursor mode
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#define TVP4020_CURSOR_OFF 0x00 // Cursor off
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#define TVP4020_CURSOR_COLOR 0x01 // 2-bits select color
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#define TVP4020_CURSOR_XGA 0x02 // 2-bits select XOR
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#define TVP4020_CURSOR_XWIN 0x03 // 2-bits select transparency/color
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/********************************************************************************/
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/* INDIRECT REGISTER - COLOR MODE REGISTER */
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/********************************************************************************/
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#define __TVP4020_COLOR_MODE 0x18 // Color Mode Register
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// Default - 0x00
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#define TVP4020_TRUE_COLOR_ENABLE (1 << 7)// True Color data accesses LUT
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#define TVP4020_TRUE_COLOR_DISABLE (0 << 7)// Non true color accesses LUT
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#define TVP4020_RGB_MODE (1 << 5)// RGB mode DABO: Swapped 0/1 (0=BGR, 1=RGB)
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#define TVP4020_BGR_MODE (0 << 5)// BGR mode
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#define TVP4020_VGA_SELECT (0 << 4)// select VGA mode
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#define TVP4020_GRAPHICS_SELECT (1 << 4)// select graphics modes
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#define TVP4020_PIXEL_MODE_CI8 (0 << 0)// pseudo color or VGA mode
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#define TVP4020_PIXEL_MODE_332 (1 << 0)// 332 true color
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#define TVP4020_PIXEL_MODE_2320 (2 << 0)// 232 off
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#define TVP4020_PIXEL_MODE_2321 (3 << 0)//
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#define TVP4020_PIXEL_MODE_5551 (4 << 0)//
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#define TVP4020_PIXEL_MODE_4444 (5 << 0)//
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#define TVP4020_PIXEL_MODE_565 (6 << 0)//
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#define TVP4020_PIXEL_MODE_8888 (8 << 0)//
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#define TVP4020_PIXEL_MODE_PACKED (9 << 0)// 24 bit packed
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/********************************************************************************/
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/* INDIRECT REGISTER - MODE CONTROL REGISTER */
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/********************************************************************************/
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#define __TVP4020_MODE_CONTROL 0x19 // Mode control
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// Default - 0x00
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#define TVP4020_PRIMARY_INPUT (0 << 4)// Primary input throuh palette
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#define TVP4020_SECONDARY_INPUT (1 << 4)// Secondary input throuh palette
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#define TVP4020_5551_DBL_BUFFER (1 << 2)// Enable 5551 dbl buffer
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#define TVP4020_5551_PACKED (0 << 2)// Packed 555 mode
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#define TVP4020_ENABLE_STATIC_DBL_BUFFER (1 << 1)// Static dbl buffer enabled
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#define TVP4020_DISABLE_STATIC_DBL_BUFFER (1 << 1)// Static dbl buffer disabled
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#define TVP4020_SELECT_FRONT_MODE (0 << 0)// Front mode
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#define TVP4020_SELECT_BACK_MODE (1 << 0)// Back mode
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/********************************************************************************/
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/* INDIRECT REGISTER - PALETTE PAGE */
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/********************************************************************************/
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#define __TVP4020_PALETTE_PAGE 0x1C //
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// Default - 0x00
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/********************************************************************************/
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/* INDIRECT REGISTER - MISC CONTROL */
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/********************************************************************************/
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#define __TVP4020_MISC_CONTROL 0x1E //
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// Default - 0x00
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#define TVP4020_SYNC_ENABLE (1 << 5)// Output SYNC info onto IOG
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#define TVP4020_SYNC_DISABLE (0 << 5)// No SYNC IOG output
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#define TVP4020_PEDESTAL_0 (0 << 4)// 0 IRE blanking pedestal
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#define TVP4020_PEDESTAL_75 (1 << 4)// 7.5 IRE blanking pedestal
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#define TVP4020_VSYNC_INVERT (1 << 3)// invert VSYNC output polarity
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#define TVP4020_VSYNC_NORMAL (0 << 3)// normal VSYNC output polarity
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#define TVP4020_HSYNC_INVERT (1 << 2)// invert HSYNC output polarity
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#define TVP4020_HSYNC_NORMAL (0 << 3)// normal HSYNC output polarity
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#define TVP4020_DAC_8BIT (1 << 1)// DAC is in 8-bit mode
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#define TVP4020_DAC_6BIT (0 << 1)// DAC is in 6-bit mode
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#define TVP4020_DAC_POWER_ON (0 << 0)// Turn DAC Power on
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#define TVP4020_DAC_POWER_OFF (1 << 0)// Turn DAC Power off
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/********************************************************************************/
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/* INDIRECT REGISTER - COLOR KEY CONTROL */
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/********************************************************************************/
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#define __TVP4020_CK_CONTROL 0x40 //
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// Default - 0x00
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/********************************************************************************/
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/* INDIRECT REGISTER - COLOR KEY OVERLAY */
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/********************************************************************************/
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#define __TVP4020_CK_OVR_REG 0x41 //
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// Default - 0x00
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/********************************************************************************/
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/* INDIRECT REGISTER - COLOR KEY RED */
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/********************************************************************************/
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#define __TVP4020_CK_RED_REG 0x42 //
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// Default - 0x00
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/********************************************************************************/
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/* INDIRECT REGISTER - COLOR KEY GREEN */
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/********************************************************************************/
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#define __TVP4020_CK_GREEN_REG 0x43 //
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// Default - 0x00
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/********************************************************************************/
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/* INDIRECT REGISTER - COLOR KEY BLUE */
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/********************************************************************************/
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#define __TVP4020_CK_BLUE_REG 0x44 //
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// Default - 0x00
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/********************************************************************************/
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/* INDIRECT REGISTER - PIXEL CLOCK PLL */
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/********************************************************************************/
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#define __TVP4020_PIXCLK_REG_A1 0x20
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#define __TVP4020_PIXCLK_REG_A2 0x21
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#define __TVP4020_PIXCLK_REG_A3 0x22
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#define __TVP4020_PIXCLK_REG_B1 0x23
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#define __TVP4020_PIXCLK_REG_B2 0x24
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#define __TVP4020_PIXCLK_REG_B3 0x25
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#define __TVP4020_PIXCLK_REG_C1 0x26
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#define __TVP4020_PIXCLK_REG_C2 0x27
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#define __TVP4020_PIXCLK_REG_C3 0x28
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#define __TVP4020_PIXCLK_STATUS 0x29
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/********************************************************************************/
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/* INDIRECT REGISTER - MEMORU CLOCK PLL */
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/********************************************************************************/
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#define __TVP4020_MEMCLK_REG_1 0x30
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#define __TVP4020_MEMCLK_REG_2 0x31
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#define __TVP4020_MEMCLK_REG_3 0x32
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#define __TVP4020_MEMCLK_STATUS 0x33
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#if 0
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// need a delay between each write to the 4020. The only way to guarantee
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// that the write has completed is to read from a Permedia2 control register.
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// Reading forces any posted writes to be flushed out.
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#define TVP4020_DELAY \
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{ \
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volatile LONG __junk; \
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__junk = VideoPortReadRegisterUlong (FB_MODE_SEL); \
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__junk = VideoPortReadRegisterUlong (FB_MODE_SEL); \
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}
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#else
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#define TVP4020_DELAY
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#endif
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// macro to load a given data value into an internal TVP4020 register.
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//
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#define TVP4020_SET_INDEX_REG(index) \
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{ \
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DEBUG_PRINT((3, "*(0x%X) <-- 0x%X\n", __TVP4020_INDEX_ADDR, (index) & 0xff)); \
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VideoPortWriteRegisterUlong(__TVP4020_INDEX_ADDR, (ULONG)((index) & 0xff)); \
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TVP4020_DELAY; \
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}
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#define TVP4020_WRITE_INDEX_REG(index, data) \
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{ \
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TVP4020_SET_INDEX_REG(index); \
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DEBUG_PRINT((3, "*(0x%X) <-- 0x%X\n", __TVP4020_INDEX_DATA, (data) & 0xff)); \
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VideoPortWriteRegisterUlong(__TVP4020_INDEX_DATA, (ULONG)((data) & 0xff)); \
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TVP4020_DELAY; \
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}
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#define TVP4020_READ_INDEX_REG(index, data) \
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{ \
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TVP4020_SET_INDEX_REG(index); \
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data = VideoPortReadRegisterUlong(__TVP4020_INDEX_DATA) & 0xff; \
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TVP4020_DELAY; \
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DEBUG_PRINT((3, "0x%X <-- *(0x%X)\n", data, __TVP4020_INDEX_DATA)); \
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}
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// DABO: For compatibility with TVP3026
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#define TVP4020_LOAD_CURSOR_CTRL(data) \
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{ \
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volatile LONG __temp; \
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TVP4020_READ_INDEX_REG(__TVP4020_CURSOR_CONTROL, __temp); \
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__temp &= ~(0x03) ; \
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__temp |= ((data) & 0x03) ; \
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TVP4020_WRITE_INDEX_REG(__TVP4020_CURSOR_CONTROL, __temp); \
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}
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//
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// macros to write a given RGB triplet into cursors 0, 1 and 2
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//
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#define TVP4020_SET_CURSOR_COLOR0(red, green, blue) \
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{ \
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VideoPortWriteRegisterUlong(__TVP4020_CUR_COL_ADDR, (ULONG)(TVP4020_CURSOR_COLOR0)); \
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TVP4020_DELAY; \
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VideoPortWriteRegisterUlong(__TVP4020_CUR_COL_DATA, (ULONG)(red)); \
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TVP4020_DELAY; \
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VideoPortWriteRegisterUlong(__TVP4020_CUR_COL_DATA, (ULONG)(green)); \
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TVP4020_DELAY; \
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VideoPortWriteRegisterUlong(__TVP4020_CUR_COL_DATA, (ULONG)(blue)); \
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TVP4020_DELAY; \
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}
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#define TVP4020_SET_CURSOR_COLOR1(red, green, blue) \
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{ \
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VideoPortWriteRegisterUlong(__TVP4020_CUR_COL_ADDR, (ULONG)(TVP4020_CURSOR_COLOR1)); \
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TVP4020_DELAY; \
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VideoPortWriteRegisterUlong(__TVP4020_CUR_COL_DATA, (ULONG)(red)); \
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TVP4020_DELAY; \
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VideoPortWriteRegisterUlong(__TVP4020_CUR_COL_DATA, (ULONG)(green)); \
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TVP4020_DELAY; \
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VideoPortWriteRegisterUlong(__TVP4020_CUR_COL_DATA, (ULONG)(blue)); \
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TVP4020_DELAY; \
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}
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#define TVP4020_SET_CURSOR_COLOR2(red, green, blue) \
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{ \
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VideoPortWriteRegisterUlong(__TVP4020_CUR_COL_ADDR, (ULONG)(TVP4020_CURSOR_COLOR2)); \
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TVP4020_DELAY; \
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VideoPortWriteRegisterUlong(__TVP4020_CUR_COL_DATA, (ULONG)(red)); \
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TVP4020_DELAY; \
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VideoPortWriteRegisterUlong(__TVP4020_CUR_COL_DATA, (ULONG)(green)); \
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TVP4020_DELAY; \
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VideoPortWriteRegisterUlong(__TVP4020_CUR_COL_DATA, (ULONG)(blue)); \
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TVP4020_DELAY; \
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}
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//
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// macros to load a given RGB triple into the TVP4020 palette. Send the starting
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// index and then send RGB triples. Auto-increment is turned on.
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// Use TVP4020_PALETTE_START and multiple TVP4020_LOAD_PALETTE calls to load
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// a contiguous set of entries. Use TVP4020_LOAD_PALETTE_INDEX to load a set
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// of sparse entries.
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//
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#define TVP4020_PALETTE_START_WR(index) \
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{ \
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VideoPortWriteRegisterUlong(__TVP4020_PAL_WR_ADDR, (ULONG)(index)); \
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TVP4020_DELAY; \
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}
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#define TVP4020_PALETTE_START_RD(index) \
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{ \
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VideoPortWriteRegisterUlong(__TVP4020_PAL_RD_ADDR, (ULONG)(index)); \
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TVP4020_DELAY; \
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}
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#define TVP4020_LOAD_PALETTE(red, green, blue) \
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{ \
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VideoPortWriteRegisterUlong(__TVP4020_PAL_DATA, (ULONG)(red)); \
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TVP4020_DELAY; \
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VideoPortWriteRegisterUlong(__TVP4020_PAL_DATA, (ULONG)(green)); \
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TVP4020_DELAY; \
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VideoPortWriteRegisterUlong(__TVP4020_PAL_DATA, (ULONG)(blue)); \
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TVP4020_DELAY; \
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}
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#define TVP4020_LOAD_PALETTE_INDEX(index, red, green, blue) \
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{ \
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VideoPortWriteRegisterUlong(__TVP4020_PAL_WR_ADDR, (ULONG)(index)); \
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TVP4020_DELAY; \
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VideoPortWriteRegisterUlong(__TVP4020_PAL_DATA, (ULONG)(red)); \
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TVP4020_DELAY; \
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VideoPortWriteRegisterUlong(__TVP4020_PAL_DATA, (ULONG)(green)); \
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TVP4020_DELAY; \
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VideoPortWriteRegisterUlong(__TVP4020_PAL_DATA, (ULONG)(blue)); \
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TVP4020_DELAY; \
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}
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//
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// macro to read back a given RGB triple from the TVP4020 palette. Use after
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// a call to TVP4020_PALETTE_START_RD
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//
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#define TVP4020_READ_PALETTE(red, green, blue) \
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{ \
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red = (UCHAR)(VideoPortReadRegisterUlong(__TVP4020_PAL_DATA) & 0xff); \
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TVP4020_DELAY; \
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green = (UCHAR)(VideoPortReadRegisterUlong(__TVP4020_PAL_DATA) & 0xff); \
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TVP4020_DELAY; \
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blue = (UCHAR)(VideoPortReadRegisterUlong(__TVP4020_PAL_DATA) & 0xff); \
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TVP4020_DELAY; \
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}
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//
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// macros to set/get the pixel read mask. The mask is 8 bits wide and gets
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// replicated across all bytes that make up a pixel.
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//
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#define TVP4020_SET_PIXEL_READMASK(mask) \
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{ \
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VideoPortWriteRegisterUlong(__TVP4020_PIXEL_MASK, (ULONG)(mask)); \
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TVP4020_DELAY; \
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}
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#define TVP4020_READ_PIXEL_READMASK(mask) \
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{ \
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mask = VideoPortReadRegisterUlong(__TVP4020_PIXEL_MASK) & 0xff; \
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}
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//
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// macros to load values into the cursor array
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//
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#define TVP4020_CURSOR_ARRAY_START(offset) \
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{ \
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volatile LONG __temp; \
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TVP4020_READ_INDEX_REG(__TVP4020_CURSOR_CONTROL, __temp); \
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__temp &= ~TVP4020_CURSOR_RAM_MASK ; \
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__temp |= TVP4020_CURSOR_RAM_ADDRESS((offset)>> 8) ; \
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TVP4020_WRITE_INDEX_REG(__TVP4020_CURSOR_CONTROL, __temp); \
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VideoPortWriteRegisterUlong(__TVP4020_CUR_RAM_WR_ADDR, (ULONG)((offset)& 0xff)); \
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TVP4020_DELAY; \
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}
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//
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// DABO: Need a similar macro to set the read address for cursor RAM?
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// DABO: changed to __TVP4020_CUR_RAM_DATA
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//
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#define TVP4020_LOAD_CURSOR_ARRAY(data) \
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{ \
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VideoPortWriteRegisterUlong(__TVP4020_CUR_RAM_DATA, (ULONG)(data)); \
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TVP4020_DELAY; \
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}
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//
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// DABO: changed to __TVP4020_CUR_RAM_DATA
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//
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|
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#define TVP4020_READ_CURSOR_ARRAY(data) \
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{ \
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data = VideoPortReadRegisterUlong(__TVP4020_CUR_RAM_DATA) & 0xff; \
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TVP4020_DELAY; \
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}
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//
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// macro to move the cursor
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//
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|
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#define TVP4020_MOVE_CURSOR(x, y) \
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{ \
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VideoPortWriteRegisterUlong(__TVP4020_CURSOR_X_LSB, (ULONG)((x) & 0xff)); \
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TVP4020_DELAY; \
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VideoPortWriteRegisterUlong(__TVP4020_CURSOR_X_MSB, (ULONG)((x) >> 8)); \
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TVP4020_DELAY; \
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VideoPortWriteRegisterUlong(__TVP4020_CURSOR_Y_LSB, (ULONG)((y) & 0xff)); \
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TVP4020_DELAY; \
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VideoPortWriteRegisterUlong(__TVP4020_CURSOR_Y_MSB, (ULONG)((y) >> 8)); \
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TVP4020_DELAY; \
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}
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//
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// macro to change the cursor hotspot
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//
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#define TVP4020_CURSOR_HOTSPOT(x, y) \
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{ \
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TVP4020_DELAY; \
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}
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