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120 lines
5.4 KiB
120 lines
5.4 KiB
page ,132
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;-----------------------------Module-Header-----------------------------;
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; Module Name: EGAVGA.INC
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;
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; This file contains the external definitions of the EGA/VGA specific
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; locations which driver output routines need to reference.
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;
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; Copyright (c) Microsoft Corporation 1989 - 1993
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;
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;-----------------------------------------------------------------------;
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;-----------------------------------------------------------------------;
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; Miscellaneous Registers used only at EGA/VGA initialization time
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MISC_OUTPUT EQU 0C2h ;Miscellaneous Output Register
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CRTC_ADDR EQU 0D4h ;CRTC Address Register for color mode
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CRTC_DATA EQU 0D5h ;CRTC Data Register for color mode
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GRAF_1_POS EQU 0CCh ;Graphics 1 Address Register
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GRAF_2_POS EQU 0CAh ;Graphics 2 Address Register
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ATTR_READ EQU 0DAh ;Attribute Controler Read Address
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ATTR_WRITE EQU 0C0h ;Attribute Controler Write Address
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IN_STAT_0 EQU 0C2h ;Input Status Register 0
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IN_STAT_1 EQU 0DAh ;Input Status Register 1
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; EGA/VGA Register Definitions.
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;
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; The following definitions are the EGA/VGA registers and values
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; used by this driver. All other registers are set up at
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; when the EGA/VGA is placed into graphics mode and never altered
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; afterwards.
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;
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; All unspecified bits in the following registers must be 0.
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EGA_BASE EQU 300h ;Base address of the EGA (3xx)
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VGA_BASE EQU 300h ;Base address of the VGA (3xx)
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; EGA/VGA Register Definitions.
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EGA_BASE EQU 300h ;Base address of the EGA (3xx)
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VGA_BASE EQU 300h ;Base address of the VGA (3xx)
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; SEQUencer Registers Used
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SEQ_ADDR EQU 0C4h ;SEQUencer Address Register
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SEQ_DATA EQU 0C5h ;SEQUencer Data Register
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SEQ_MAP_MASK EQU 02h ;Write Plane Enable Mask
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MM_C0 EQU 00000001b ; C0 plane enable
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MM_C1 EQU 00000010b ; C1 plane enable
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MM_C2 EQU 00000100b ; C2 plane enable
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MM_C3 EQU 00001000b ; C3 plane enable
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MM_ALL EQU 00001111b ; All planes
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SEQ_MODE EQU 04h ;Memory Mode
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SM_ALPHA EQU 00000001b ; Char map select enable
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SM_EXTENDED EQU 00000010b ; Extended memory present
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SM_ODD_PLANE EQU 00000100b ; Odd/even bytes to same plane
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SM_CHAIN4 EQU 00001000b ; Chain4 mode
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; Graphics Controller Registers Used
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GRAF_ADDR EQU 0CEh ;Graphics Controller Address Register
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GRAF_DATA EQU 0CFh ;Graphics Controller Data Register
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GRAF_SET_RESET EQU 00h ; Set/Reset Plane Color
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GRAF_ENAB_SR EQU 01h ; Set/Reset Enable
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GRAF_COL_COMP EQU 02h ; Color Compare Register
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GRAF_DATA_ROT EQU 03h ; Data Rotate Register
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DR_ROT_CNT EQU 00000111b ; Data Rotate Count
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DR_SET EQU 00000000b ; Data Unmodified
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DR_AND EQU 00001000b ; Data ANDed with latches
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DR_OR EQU 00010000b ; Data ORed with latches
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DR_XOR EQU 00011000b ; Data XORed with latches
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GRAF_READ_MAP EQU 04h ; Read Map Select Register
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RM_C0 EQU 00000000b ; Read C0 plane
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RM_C1 EQU 00000001b ; Read C1 plane
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RM_C2 EQU 00000010b ; Read C2 plane
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RM_C3 EQU 00000011b ; Read C3 plane
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GRAF_MODE EQU 05h ; Mode Register
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M_PROC_WRITE EQU 00000000b ; Write processor data rotated
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M_LATCH_WRITE EQU 00000001b ; Write latched data
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M_COLOR_WRITE EQU 00000010b ; Write processor data as color
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M_AND_WRITE EQU 00000011b ; Write (procdata AND bitmask)
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M_DATA_READ EQU 00000000b ; Read selected plane
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M_COLOR_READ EQU 00001000b ; Read color compare
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GRAF_MISC EQU 06h ; Miscellaneous Register
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MS_NON_ALPHA EQU 00000001b ; Char generator disabled
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MS_ODD_EVEN EQU 00000010b ; Map odd addresses to even
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MS_A0000_128K EQU 00000000b ; Memory present at A0000, 128kb
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MS_A0000_64K EQU 00000100b ; Memory present at A0000, 64kb
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MS_B0000_32K EQU 00001000b ; Memory present at B0000, 32kb
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MS_B8000_32K EQU 00001100b ; Memory present at B8000, 32kb
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MS_ADDR_MASK EQU 00001100b
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GRAF_CDC EQU 07h ; Color Don't Care Register
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GRAF_BIT_MASK EQU 08h ; Bit Mask Register
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; Various sizes for EGA/VGA data structures
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;-----------------------------------------------------------------------;
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; The pointer parameters are the size of the pointer as received from
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; DeviceSetCursor.
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;-----------------------------------------------------------------------;
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PTR_HEIGHT EQU 32
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PTR_WIDTH EQU 4 ;Width in bytes of pointer
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PTR_WIDTH_BITS EQU PTR_WIDTH*8 ;Width in bits of pointer
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