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184 lines
6.1 KiB
184 lines
6.1 KiB
/******************************Module*Header*******************************\
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*
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* Module Name: init.c
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* Author: Goran Devic, Mark Einkauf
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* Purpose: Initialize Laguna3D 3D engine
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*
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* Copyright (c) 1997 Cirrus Logic, Inc.
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*
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\**************************************************************************/
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/*********************************************************************
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* Include Files
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**********************************************************************/
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#include "precomp.h"
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#include "mcdhw.h"
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extern DWORD _InitDisplayList( PDEV *ppdev, DWORD dwListLen );
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/*********************************************************************
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* Local Macros
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**********************************************************************/
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// Set the register and the cache in LL_State to a specific value
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#define SETREG(Offset,Reg,Value) \
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*(ppdev->LL_State.pRegs + (Offset)) = ppdev->LL_State.Reg = (Value); /*inp(0x80); inp(0x80)*/
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// setreg, no cache: do not cache state for this register
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#define SETREG_NC(reg, value) \
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(*(ppdev->LL_State.pRegs + reg) = value); /*inp(0x80); inp(0x80)*/
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// Clears the range of registers
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#define CLEAR_RANGE( StartReg, EndReg ) \
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memset( (void *)(ppdev->LL_State.pRegs + (StartReg)), 0, ((EndReg) - (StartReg)+1)*4 )
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/*********************************************************************
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* Local Variables
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**********************************************************************/
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/*********************************************************************
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* Local Functions
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**********************************************************************/
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DWORD LL_InitLib( PDEV *ppdev )
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{
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int i, j, error_code;
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// =========== REGISTER SETTINGS ==============
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// Set all 3D registers in the order
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CLEAR_RANGE( X_3D, DU_ORTHO_ADD_3D );// Clear 3D interpolators
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SETREG_NC( WIDTH1_3D, 0x10000 ); // Init polyengine reg WIDTH1_3D to 1
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CLEAR_RANGE( A_3D, DA_ORTHO_3D ); // Clear 3D interpolators
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SETREG_NC( CONTROL_MASK_3D, 0 ); // Enable writes
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SETREG_NC( CONTROL0_3D, 0 );
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CLEAR_RANGE( COLOR_MIN_BOUNDS_3D, COLOR_MAX_BOUNDS_3D );
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ppdev->LL_State.rColor_Min_Bounds = 0;
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ppdev->LL_State.rColor_Max_Bounds = 0;
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SETREG_NC( CONTROL1_3D, 0 );
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// Set Base0 address register:
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// * Color buffer X offset
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// * Color buffer location in RDRAM
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// * Z buffer location in RDRAM
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// * Textures in RDRAM
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// * Pattern offset of 0
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//
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SETREG_NC( BASE0_ADDR_3D, 0 );
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// Set Base1 address register:
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// * Color buffer Y offset to 0
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// * Z buffer Y offset to 0
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//
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SETREG_NC( BASE1_ADDR_3D, 0 );
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// Set texture control register:
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// * Texture U, V masks to 16
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// * Texture U, V wraps
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// * Texel mode temporarily to 0
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// * Texel lookop to no lookup
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// * Texture data is lighting source
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// * Filtering disabled
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// * Texture polarity of type 0
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// * Texture masking diasabled
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// * Texture mask function to Write mask
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// * Address mux to 0
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// * CLUT offset to 0
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//
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SETREG_NC( TX_CTL0_3D, 0 );
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SETREG_NC( TX_XYBASE_3D, 0 );
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SETREG_NC( TX_CTL1_3D, 0 ); // Set tex color bounds
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#if DRIVER_5465
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// FUTURE: verify that filter set of mask_thresh=0,step_bilinear=smooth_bilinear=0,frac=0x7 is OK
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SETREG_NC( TX_CTL2_3D, (0x7 << 24) ); // Set tex color bounds and filter to true bilinear
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#else // DRIVER_5465
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SETREG_NC( TX_CTL2_3D, 0); // Set tex color bounds
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#endif // DRIVER_5465
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SETREG_NC( COLOR0_3D, 0 );
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SETREG_NC( COLOR1_3D, 0 );
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// Don't write Z_Collide - will cause interrupt...
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//SETREG_NC( Z_COLLIDE_3D, 0 );
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CLEAR_RANGE( STATUS0_3D, PATTERN_RAM_7_3D );
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SETREG_NC( X_CLIP_3D, 0 );
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SETREG_NC( Y_CLIP_3D, 0 );
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SETREG_NC( TEX_SRAM_CTRL_3D, 0 ); // Set a 2D ctrl reg
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// =========== HOST XY UNIT REGISTERS ==============
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SETREG_NC( HXY_HOST_CTRL_3D, 0 );
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SETREG_NC( HXY_BASE0_ADDRESS_PTR_3D, 0 );
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SETREG_NC( HXY_BASE0_START_XY_3D, 0 );
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SETREG_NC( HXY_BASE0_EXTENT_XY_3D, 0 );
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SETREG_NC( HXY_BASE1_ADDRESS_PTR_3D, 0 );
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SETREG_NC( HXY_BASE1_OFFSET0_3D, 0 );
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SETREG_NC( HXY_BASE1_LENGTH_3D, 0 );
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SETREG_NC( MAILBOX0_3D, 0 );
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SETREG_NC( MAILBOX1_3D, 0 );
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SETREG_NC( MAILBOX2_3D, 0 );
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SETREG_NC( MAILBOX3_3D, 0 );
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// =========== PREFETCH UNIT REGISTERS ==============
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SETREG_NC( PF_CTRL_3D, 0); // Disable Prefetch
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SETREG_NC( PF_BASE_ADDR_3D, 0 ); // Set prefetch base reg
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SETREG_NC( PF_INST_3D, IDLE ); // Write IDLE instruction
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SETREG_NC( PF_DEST_ADDR_3D, 0 ); // Set prefetch dest address
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SETREG_NC( PF_FB_SEG_3D, 0 ); // Set frame segment reg
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SETREG_NC( PF_STATUS_3D, 0 ); // Reset Display_List_Switch
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// FUTURE - Host Master Control hardcoded to single read/write
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#if 0
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ppdev->LL_State.fSingleRead = ppdev->LL_State.fSingleWrite = 1;
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SETREG_NC( HOST_MASTER_CTRL_3D, // Set host master control
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(ppdev->LL_State.fSingleRead << 1) | ppdev->LL_State.fSingleWrite );
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#endif
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SETREG_NC( PF_CTRL_3D, 0x19); // Fetch on request
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// Initialize display list (displist.c)
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//
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if( (error_code = _InitDisplayList( ppdev, SIZE_TEMP_DL )) != LL_OK )
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return( error_code );
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// the 4x4 pattern from LL3D - thought to be best for 3 bit dither
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ppdev->LL_State.dither_array.pat[0] = 0x04150415;
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ppdev->LL_State.dither_array.pat[1] = 0x62736273;
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ppdev->LL_State.dither_array.pat[2] = 0x15041504;
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ppdev->LL_State.dither_array.pat[3] = 0x73627362;
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ppdev->LL_State.dither_array.pat[4] = 0x04150415;
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ppdev->LL_State.dither_array.pat[5] = 0x62736273;
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ppdev->LL_State.dither_array.pat[6] = 0x15041504;
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ppdev->LL_State.dither_array.pat[7] = 0x73627362;
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ppdev->LL_State.dither_x_offset = 0;
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ppdev->LL_State.dither_y_offset = 0;
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ppdev->LL_State.pattern_ram_state = PATTERN_RAM_INVALID;
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return( LL_OK );
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}
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