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806 lines
22 KiB
806 lines
22 KiB
/****************************************************************************
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*****************************************************************************
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*
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* ******************************************
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* * Copyright (c) 1995, Cirrus Logic, Inc. *
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* * All Rights Reserved *
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* ******************************************
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*
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* PROJECT: Laguna I (CL-GD5462) -
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*
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* FILE: cirrus.h
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*
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* AUTHOR: Benny Ng
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*
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* DESCRIPTION:
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* This module contains the definitions for the Cirrus
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* Logic Laguna NT miniport driver. (kernel mode only)
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* Based on the S3 miniport from NT DDK.
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*
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* Copyright (c) 1995, 1996 Cirrus Logic, Inc.
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*
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* MODULES:
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*
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* REVISION HISTORY:
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* 5/30/95 Benny Ng Initial version
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*
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* $Log: X:/log/laguna/nt35/miniport/cl546x/CIRRUS.H $
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*
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* Rev 1.46 Apr 20 1998 10:48:56 frido
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* Oops. I missed a semi colon.
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*
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* Rev 1.45 Apr 20 1998 10:47:02 frido
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* PDR#11350. Added CLResetHw prototype.
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*
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* Rev 1.44 Mar 25 1998 10:17:14 frido
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* Added CLGetMonitorSyncPolarity function declaration.
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*
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* Rev 1.43 Mar 25 1998 10:08:40 frido
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* Added dwPolarity field to HW_DEVICE_EXTENSION structure.
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*
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* Rev 1.42 Feb 24 1998 15:10:38 frido
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* Added GetDDCInformation for NT 5.0.
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*
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* Rev 1.41 Feb 18 1998 14:16:28 frido
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* PDR#11209. Added status to ReadByte.
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*
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* Rev 1.40 Jan 22 1998 11:10:18 frido
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* Added dwFBMTTRReg variable for Write Combining on i386.
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*
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* Rev 1.39 Jan 07 1998 10:55:52 frido
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* Added fLowRes field.
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*
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* Rev 1.38 Nov 03 1997 16:46:20 phyang
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* Added data and function declarations for USB Fix and better EDID support.
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*
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* Rev 1.37 Oct 23 1997 15:50:42 phyang
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* Moved globals for DDC filter function to HW_DEVICE_EXTENSION.
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*
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* Rev 1.36 23 Oct 1997 11:18:04 noelv
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*
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* Added globals for DDC filter function.
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*
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* Rev 1.35 04 Sep 1997 11:35:04 bennyn
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* Extended the register space from 8000h to A000h
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*
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* Rev 1.34 28 Aug 1997 17:13:08 noelv
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* Added Setmode prototype.
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*
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* Rev 1.33 20 Aug 1997 09:31:36 bennyn
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*
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* Added automatically detects PnP monitor support
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*
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* Rev 1.32 13 Aug 1997 11:22:14 noelv
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* Added [5465AD] setcion to MODE.INI
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*
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* Rev 1.31 01 Aug 1997 16:29:56 noelv
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* Removed BIOS and VGA from IOCTL_VIDEO_RESET_DEVICE
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*
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* Rev 1.30 23 Jul 1997 09:12:00 bennyn
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*
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* Added BIOSVersion into HwDeviceExtension structure
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*
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* Rev 1.29 21 Jul 1997 13:51:10 bennyn
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*
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* Added EDID data into HwDeviceExtension structure
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*
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* Rev 1.28 20 Jun 1997 13:44:02 bennyn
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*
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* Added power manager data to HW Extension structure
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*
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* Rev 1.27 30 Apr 1997 16:42:04 noelv
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* Moved global SystemIoBusNumber into the device extension, where it belongs.
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*
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* Rev 1.26 24 Apr 1997 10:09:22 SueS
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* Added prototype for CLEnablePCIConfigMMIO.
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*
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* Rev 1.25 23 Apr 1997 06:58:42 SueS
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* Added PCI slot number to HW_DEVICE_EXTENSION structure. Added function
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* prototypes for some kernel calls.
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*
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* Rev 1.24 22 Apr 1997 11:02:02 noelv
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*
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* Added forward compatible chip ids.
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*
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* Rev 1.23 04 Apr 1997 14:46:44 noelv
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* Removed VL access ranges. REarranged VGA access ranges.
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* Changed call to SetMode() to include the new parameter.
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*
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* Rev 1.22 28 Feb 1997 11:20:44 SueS
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* Added structures and defines used in HalGetAdapter call.
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*
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* Rev 1.21 21 Feb 1997 14:41:32 noelv
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* Oops. I swapped the frame buffer and register address spaces by accident.
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*
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* Rev 1.20 21 Feb 1997 12:53:24 noelv
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* AGP and 5465 4meg support
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*
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* Rev 1.19 21 Jan 1997 11:29:48 noelv
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* Added LG_NONE
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*
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* Rev 1.18 14 Jan 1997 12:31:42 noelv
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* Split MODE.INI by chip type
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*
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* Rev 1.17 14 Nov 1996 15:27:00 noelv
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*
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* Removed warning for HalAllocCommonBuffer
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*
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* Rev 1.16 13 Nov 1996 15:24:14 SueS
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* Added new include file for use with log file option.
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*
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* Rev 1.15 13 Nov 1996 08:17:48 noelv
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*
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* Cleaned up support for 5464 register set.
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*
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* Rev 1.14 07 Nov 1996 09:40:26 bennyn
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* Added device ID for BD and 5465
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*
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* Rev 1.13 23 Oct 1996 15:59:34 noelv
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* Added bus mastering stuff.
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*
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* Rev 1.12 21 Aug 1996 10:11:46 noelv
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* Added defines for chip ids
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*
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* Rev 1.11 20 Aug 1996 11:26:40 noelv
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* Bugfix release from Frido 8-19-96
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*
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* Rev 1.1 15 Aug 1996 12:45:28 frido
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* Added #include 'type.h".
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* Added prototype for SetMode() function.
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*
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* Rev 1.0 14 Aug 1996 17:12:10 frido
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* Initial revision.
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*
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* Rev 1.10 17 Jul 1996 09:42:20 noelv
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* Fixed location of STATUS register.
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*
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* Rev 1.9 15 Jul 1996 17:18:24 noelv
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* Added wait for idle before mode switch
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*
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* Rev 1.8 19 Jun 1996 11:04:10 noelv
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* New mode switch code.
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*
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* Rev 1.7 13 May 1996 14:52:54 bennyn
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*
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* Added 5464 support
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*
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* Rev 1.6 10 Apr 1996 17:58:06 bennyn
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* Conditional turn of HD_BRST_EN
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*
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* Rev 1.5 02 Mar 1996 12:30:46 noelv
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* Miniport now patches the ModeTable with information read from the BIOS
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*
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* Rev 1.4 07 Dec 1995 16:33:10 noelv
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* Changed MAX_SLOTS to 32
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*
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* Rev 1.3 18 Sep 1995 10:02:26 bennyn
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*
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* Rev 1.2 23 Aug 1995 14:45:26 bennyn
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*
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* Rev 1.1 17 Aug 1995 08:18:08 BENNYN
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*
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*
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* Rev 1.0 24 Jul 1995 13:22:54 NOELV
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* Initial revision.
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*
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****************************************************************************
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****************************************************************************/
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/*----------------------------- INCLUDES ----------------------------------*/
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#include <dderror.h>
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#include <devioctl.h>
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#include <miniport.h>
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#include <ntddvdeo.h>
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#include <video.h>
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#include "logfile.h"
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#include "type.h"
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#include "clioctl.h"
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/*----------------------------- DEFINES -----------------------------------*/
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//
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// Vendor and Device ID definitions
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//
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#define VENDOR_ID 0x1013 // Vender Id for Cirrus Logic
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#define CL_GD5462 0x00D0 // 5462
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#define CL_GD5464 0x00D4 // 5464
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#define CL_GD5464_BD 0x00D5 // 5464 BD
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#define CL_GD5465 0x00D6 // 5465
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//
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// These Laguna chips don't exist yet, but we'll support them when
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// they get here, 'cause we're FORWARD COMPATIBLE! All future
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// chips are GUARENTEED to look and act just like the 5465.
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// Yep, yep, yep! (sigh.)
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//
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#define CL_GD546x_D7 0x00D7
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#define CL_GD546x_D8 0x00D8
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#define CL_GD546x_D9 0x00D9
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#define CL_GD546x_DA 0x00DA
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#define CL_GD546x_DB 0x00DB
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#define CL_GD546x_DC 0x00DC
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#define CL_GD546x_DD 0x00DD
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#define CL_GD546x_DE 0x00DE
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#define CL_GD546x_DF 0x00DF
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//
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// I'm preparing to rip all the VGA out of the miniport.
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// This flag is to allow me to get it right the
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// first time.
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//
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#define USE_VGA 1
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//
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// How much memory to lock down for bus mastered host data transfers
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//
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#define SIZE_BUS_MASTER_BUFFER (4*1024)
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//
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// Default mode: VGA mode 3
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//
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#define DEFAULT_MODE 0
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//
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// Laguna memory-mapped registers
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//
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#define STATUS_REG 0x400
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#define VSCONTROL_REG 0x3FC
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#define CONTROL_REG 0x402
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#define OFFSET_2D_REG 0x405
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#define TILE_CTRL_REG 0x407
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#define LNCNTL_REG 0x50E
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//
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// PCI memory-mapped registers
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//
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#define PCI_COMMAND_REG 0x304
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#define PCI_BASE_ADDR_0_REG 0x0310 // Base Address 0 register
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#define PCI_BASE_ADDR_1_REG 0x0314 // Base Address 1 register
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//
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// Number of PCI slots in a machine.
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//
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#define MAX_SLOTS 256
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//
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// Number of access ranges used by the Laguna.
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//
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#if USE_VGA
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#define FIRST_VGA_ACCESS_RANGE 0
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#define LAST_VGA_ACCESS_RANGE 2
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#define NUM_VGA_ACCESS_RANGES 3
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#define FIRST_MM_ACCESS_RANGE 3
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#define LAST_MM_ACCESS_RANGE 4
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#define NUM_MM_ACCESS_RANGES 2
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#define MM_REGISTER_ACCESS_RANGE 3
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#define MM_FRAME_BUFFER_ACCESS_RANGE 4
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#define TOTAL_ACCESS_RANGES NUM_VGA_ACCESS_RANGES + NUM_MM_ACCESS_RANGES
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#else
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#define FIRST_VGA_ACCESS_RANGE 0
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#define LAST_VGA_ACCESS_RANGE 2
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#define NUM_VGA_ACCESS_RANGES 3
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#define FIRST_MM_ACCESS_RANGE 3
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#define LAST_MM_ACCESS_RANGE 4
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#define NUM_MM_ACCESS_RANGES 2
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#define MM_REGISTER_ACCESS_RANGE 3
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#define MM_FRAME_BUFFER_ACCESS_RANGE 4
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#define TOTAL_ACCESS_RANGES NUM_VGA_ACCESS_RANGES + NUM_MM_ACCESS_RANGES
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#endif
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//
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// If we don't know how much register space the chip decodes, we guess
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//
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#define DEFAULT_RESERVED_REGISTER_SPACE 0xA000
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#define DEFAULT_RESERVED_REGISTER_MASK 0xFFFF8000 // 32 k
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//
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// If we don't know how much frame buffer space the chip decodes, we guess
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//
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#define DEFAULT_RESERVED_FB_SPACE 0x02000000 // 32 meg
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#define DEFAULT_RESERVED_FB_MASK 0xFE000000 // 32 meg
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//
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// Palette-related info.
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// Highest valid DAC color register index.
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//
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#define VIDEO_MAX_COLOR_REGISTER 0xFF
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#if USE_VGA
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//
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// Register definitions used with VideoPortRead/Write functions
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// VGA IO index
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//
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#define SEQ_ADDRESS_PORT 0x0014 // Sequence Controller Address
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#define SEQ_DATA_PORT 0x0015 // Sequence Controller Data register
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#define IND_SR_6 0x0006 // Index in Sequencer to enable exts
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#define IND_SR_9 0x0009 // Scratch pad register SR9
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#define IND_SR_14 0x0014 // Scratch pad register SR14
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#define CRTC_ADDRESS_PORT_MONO 0x0004 // Mono mode CRTC Address
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#define CRTC_DATA_PORT_MONO 0x0005 // Mono mode CRTC Data register
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#define CRTC_ADDRESS_PORT_COLOR 0x0024 // Color mode CRTC Address
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#define CRTC_DATA_PORT_COLOR 0x0025 // Color mode CRTC Data register
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#define IND_CL_ID_REG 0x0027 // index in CRTC of ID Register
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#endif
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//
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// Register definitions used with VideoPortRead/Write functions
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// Memory-mapped IO index
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//
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#define DAC_PIXEL_MASK_PORT 0x00A0 // DAC pixel mask reg
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#define DAC_ADDRESS_WRITE_PORT 0x00A8 // DAC register write index reg
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#define DAC_DATA_REG_PORT 0x00AC // DAC data transfer reg
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#define MISC_OUTPUT_REG_READ_PORT 0x0080 // Misc Output reg read port
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//
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// Define the supported version numbers for the device description structure.
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//
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#define DEVICE_DESCRIPTION_VERSION 0
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#define DEVICE_DESCRIPTION_VERSION1 1
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//
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// Define the page size for the Intel 386 as 4096 (0x1000).
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//
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#define PAGE_SIZE (ULONG)0x1000
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//
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// Define the index of max.frequency table for each resolution.
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//
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#define MODE_640_INDEX 0
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#define MODE_720_INDEX 1
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#define MODE_800_INDEX 2
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#define MODE_832_INDEX 3
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#define MODE_1024_INDEX 4
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#define MODE_1152_INDEX 5
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#define MODE_1280_INDEX 6
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#define MODE_1600_INDEX 7
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#define INVALID_MODE_INDEX 8
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//
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// bios stuff
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//
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#define VESA_POWER_FUNCTION 0x4f10
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#define VESA_POWER_ON 0x0000
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#define VESA_POWER_STANDBY 0x0100
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#define VESA_POWER_SUSPEND 0x0200
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#define VESA_POWER_OFF 0x0400
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#define VESA_GET_POWER_FUNC 0x0000
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#define VESA_SET_POWER_FUNC 0x0001
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#define VESA_STATUS_SUCCESS 0x004f
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/*----------------------------- TYPEDEFS ----------------------------------*/
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//
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// Used to pass information about the common buffer from the miniport to the display driver.
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//
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typedef struct _COMMON_BUFFER_INFO {
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PUCHAR PhysAddress;
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PUCHAR VirtAddress;
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ULONG Length;
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} COMMON_BUFFER_INFO;
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//
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// Mode table structure
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// Structure used for the mode table informations
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//
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typedef struct {
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BOOLEAN ValidMode; // TRUE: Mode is valid.
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ULONG ChipType; // Chips which support this mode.
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USHORT fbType; // color or monochrome, text or graphics,
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// via VIDEO_MODE_COLOR and VIDEO_MODE_GRAPHICS
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// and interlace or non-interlace via
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// VIDEO_MODE_INTERLACED
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USHORT Frequency; // Frequency
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USHORT BIOSModeNum; // BIOS Mode number
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USHORT BytesPerScanLine; // Bytes Per Scan Line
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USHORT XResol; // Horizontal resolution in pixels or char
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USHORT YResol; // Vertical resolution in pixels or char
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UCHAR XCharSize; // Char cell width in pixels
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UCHAR YCharSize; // Char cell height in pixels
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UCHAR NumOfPlanes; // Number of memory planes
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UCHAR BitsPerPixel; // Bits per pixel
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UCHAR MonitorTypeVal; // Monitor type setting bytes
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UCHAR *SetModeString; // Instruction string used by SetMode().
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} MODETABLE, *PMODETABLE;
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//
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// Valid flags for ChipType field.
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// Must match defines in CGLMODE.C
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//
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#define LG_NONE (0 )
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#define LG_ALL (1 )
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#define LG_5462 (1 << 1)
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#define LG_5464 (1 << 2)
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#define LG_5465 (1 << 3)
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#define LG_5465AD (1 << 4)
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#define ALWAY_ON_VS_CLK_CTL 0x0000C0A0 // VW_CLK, RAMDAC_CLK
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typedef struct _LG_PWRMGR_DATA {
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WORD wInitSignature;
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int Mod_refcnt[TOTAL_MOD];
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DWORD ACPI_state;
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DWORD VS_clk_ctl_state;
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} LGPWRMGR_DATA, *P_LGPWRMGR_DATA;
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//
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// Define device extension structure. This is device dependent/private
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// information.
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//
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typedef struct _HW_DEVICE_EXTENSION {
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LGPWRMGR_DATA PMdata; // Power manager data area
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#if USE_VGA
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PUCHAR IOAddress; // base I/O address of VGA ports.
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#endif
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PUCHAR FrameAddress; // base virtual address of video memory
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ULONG FrameLength;
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PUCHAR RegisterAddress; // base virtual address of Register Space
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ULONG RegisterLength;
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PHYSICAL_ADDRESS PhysicalFrameAddress;
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ULONG PhysicalFrameLength;
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UCHAR PhysicalFrameInIoSpace;
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PHYSICAL_ADDRESS PhysicalRegisterAddress;
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ULONG PhysicalRegisterLength;
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UCHAR PhysicalRegisterInIoSpace;
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DWORD dwFBMTRRReg;
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ULONG AdapterMemorySize; // Installed RAM
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ULONG CurrentModeNum; // Current Mode Number
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PMODETABLE CurrentMode; // pointer current mode information
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ULONG ChipID; // PCI Device ID
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ULONG ChipRev; // PCI Chip Revision
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ULONG NumAvailableModes; // number of available modes
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ULONG NumTotalModes; // total number of modes
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ULONG PowerState; // Power state =
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// VideoPowerOn or VideoPowerStandBy or
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// VideoPowerSuspend or VideoPowerOff
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UCHAR TileSize; // Tile size
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UCHAR TiledMode; // Tiled mode or 0xFF if error
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UCHAR TiledTPL; // Tiled mode TPL
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UCHAR TiledInterleave; // Tiled Interleave
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PUCHAR PhysicalCommonBufferAddr;
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PUCHAR VirtualCommonBufferAddr;
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ULONG CommonBufferSize;
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ULONG SlotNumber; // PCI slot number
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unsigned long SystemIoBusNumber; // Bus number (0=PCI, 1=AGP)
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WORD BIOSVersion;
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// DDC2B & EDID data
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DWORD dwDDCFlag;
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BOOLEAN EDIDFlag;
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UCHAR EDIDBuffer[128];
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ULONG ulEDIDMaxTiming;
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USHORT usMaxVtFrequency;
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USHORT usMaxXResolution;
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USHORT usMaxFrequencyTable[8];
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BOOLEAN MultiSyncFlag;
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ULONG ulMaxHzFrequency;
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// USB fix flag
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DWORD dwAGPDataStreamingFlag;
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DWORD fLowRes;
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// Monitor sync polarity.
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DWORD dwPolarity;
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|
// secondary adapter can't access VGA resources
|
|
ULONG Dont_Do_VGA;
|
|
|
|
// output clock and data lines need to be inverted on some chips or cards
|
|
// (used only in CLDDC2B.c)
|
|
UCHAR I2Cflavor;
|
|
|
|
BOOLEAN MonitorEnabled;
|
|
|
|
} HW_DEVICE_EXTENSION, *PHW_DEVICE_EXTENSION;
|
|
|
|
|
|
//
|
|
// Define the device description structure.
|
|
//
|
|
typedef struct _DEVICE_DESCRIPTION {
|
|
ULONG Version;
|
|
BOOLEAN Master;
|
|
BOOLEAN ScatterGather;
|
|
BOOLEAN DemandMode;
|
|
BOOLEAN AutoInitialize;
|
|
BOOLEAN Dma32BitAddresses;
|
|
BOOLEAN IgnoreCount;
|
|
BOOLEAN Reserved1; // must be false
|
|
BOOLEAN Reserved2; // must be false
|
|
ULONG BusNumber;
|
|
ULONG DmaChannel;
|
|
INTERFACE_TYPE InterfaceType;
|
|
DMA_WIDTH DmaWidth;
|
|
DMA_SPEED DmaSpeed;
|
|
ULONG MaximumLength;
|
|
ULONG DmaPort;
|
|
} DEVICE_DESCRIPTION, *PDEVICE_DESCRIPTION;
|
|
|
|
|
|
/*-------------------------- External FUNCTIONS -----------------------------*/
|
|
typedef struct _ADAPTER_OBJECT *PADAPTER_OBJECT; // ntndis
|
|
|
|
PVOID
|
|
HalAllocateCommonBuffer(
|
|
PADAPTER_OBJECT AdapterObject,
|
|
ULONG Length,
|
|
PPHYSICAL_ADDRESS LogicalAddress,
|
|
BOOLEAN CacheEnabled
|
|
);
|
|
|
|
PVOID
|
|
HalFreeCommonBuffer(
|
|
PADAPTER_OBJECT AdapterObject,
|
|
ULONG Length,
|
|
PPHYSICAL_ADDRESS LogicalAddress,
|
|
PVOID VirtualAddress,
|
|
BOOLEAN CacheEnabled
|
|
);
|
|
|
|
PADAPTER_OBJECT
|
|
HalGetAdapter(
|
|
PDEVICE_DESCRIPTION DeviceDescription,
|
|
PULONG NumberOfMapRegisters
|
|
);
|
|
|
|
VOID
|
|
RtlZeroMemory (
|
|
VOID UNALIGNED *Destination,
|
|
ULONG Length
|
|
);
|
|
|
|
ULONG
|
|
HalGetBusDataByOffset(
|
|
IN BUS_DATA_TYPE BusDataType,
|
|
IN ULONG BusNumber,
|
|
IN ULONG SlotNumber,
|
|
IN PVOID Buffer,
|
|
IN ULONG Offset,
|
|
IN ULONG Length
|
|
);
|
|
|
|
ULONG
|
|
HalSetBusDataByOffset(
|
|
IN BUS_DATA_TYPE BusDataType,
|
|
IN ULONG BusNumber,
|
|
IN ULONG SlotNumber,
|
|
IN PVOID Buffer,
|
|
IN ULONG Offset,
|
|
IN ULONG Length
|
|
);
|
|
|
|
|
|
/*-------------------------- GLOBAL FUNCTIONS -----------------------------*/
|
|
//
|
|
// Global Reference.
|
|
//
|
|
extern MODETABLE ModeTable[];
|
|
extern ULONG TotalVideoModes;
|
|
|
|
|
|
VP_STATUS CLFindAdapter(
|
|
PVOID HwDeviceExtension,
|
|
PVOID HwContext,
|
|
PWSTR ArgumentString,
|
|
PVIDEO_PORT_CONFIG_INFO ConfigInfo,
|
|
PUCHAR Again
|
|
);
|
|
|
|
BOOLEAN CLInitialize(
|
|
PVOID HwDeviceExtension
|
|
);
|
|
|
|
#if _WIN32_WINNT >= 0x0500
|
|
|
|
ULONG CLGetChildDescriptor(
|
|
IN PVOID HwDeviceExtension,
|
|
IN PVIDEO_CHILD_ENUM_INFO ChildEnumInfo,
|
|
OUT PVIDEO_CHILD_TYPE VideoChildType,
|
|
OUT PVOID pChildDescriptor,
|
|
OUT PULONG UId,
|
|
OUT PVOID pUnused
|
|
);
|
|
|
|
VP_STATUS CLGetPowerState(
|
|
PVOID HwDeviceExtension,
|
|
ULONG HwId,
|
|
PVIDEO_POWER_MANAGEMENT VideoPowerControl
|
|
);
|
|
|
|
VP_STATUS CLSetPowerState(
|
|
PVOID HwDeviceExtension,
|
|
ULONG HwId,
|
|
PVIDEO_POWER_MANAGEMENT VideoPowerControl
|
|
);
|
|
|
|
#endif
|
|
|
|
BOOLEAN ReadDataLine(
|
|
PHW_DEVICE_EXTENSION HwDeviceExtension
|
|
);
|
|
|
|
BOOLEAN ReadClockLine(
|
|
PHW_DEVICE_EXTENSION HwDeviceExtension
|
|
);
|
|
|
|
VOID WriteClockLine(
|
|
PHW_DEVICE_EXTENSION HwDeviceExtension,
|
|
UCHAR data
|
|
);
|
|
|
|
VOID WriteDataLine(
|
|
PHW_DEVICE_EXTENSION HwDeviceExtension,
|
|
UCHAR data
|
|
);
|
|
|
|
VOID WaitVSync(
|
|
PHW_DEVICE_EXTENSION HwDeviceExtension
|
|
);
|
|
|
|
#if _WIN32_WINNT >= 0x0500
|
|
BOOLEAN GetDDCInformation(
|
|
PHW_DEVICE_EXTENSION HwDeviceExtension,
|
|
PVOID QueryBuffer,
|
|
ULONG BufferSize
|
|
);
|
|
#endif
|
|
|
|
void VS_Control_Hack(PHW_DEVICE_EXTENSION HwDeviceExtension, BOOL Enable);
|
|
|
|
void Output_To_VS_CLK_CONTROL(PHW_DEVICE_EXTENSION HwDeviceExtension, DWORD val);
|
|
|
|
void PMNT_Init(PHW_DEVICE_EXTENSION HwDeviceExtension);
|
|
|
|
VP_STATUS PMNT_SetACPIState (PHW_DEVICE_EXTENSION HwDeviceExtension, ULONG state);
|
|
|
|
VP_STATUS PMNT_GetACPIState (PHW_DEVICE_EXTENSION HwDeviceExtension, ULONG* state);
|
|
|
|
VP_STATUS PMNT_SetHwModuleState (PHW_DEVICE_EXTENSION HwDeviceExtension,
|
|
ULONG hwmod, ULONG state);
|
|
|
|
VP_STATUS PMNT_GetHwModuleState (PHW_DEVICE_EXTENSION HwDeviceExtension,
|
|
ULONG hwmod, ULONG* state);
|
|
|
|
void PMNT_Close (PHW_DEVICE_EXTENSION HwDeviceExtension);
|
|
|
|
#if 1 // PDR#11350
|
|
BOOLEAN CLResetHw(
|
|
PHW_DEVICE_EXTENSION HwDeviceExtension,
|
|
ULONG Columns,
|
|
ULONG Rows
|
|
);
|
|
#endif
|
|
|
|
BOOLEAN CLStartIO(
|
|
PVOID HwDeviceExtension,
|
|
PVIDEO_REQUEST_PACKET RequestPacket
|
|
);
|
|
|
|
VP_STATUS CLSetColorLookup(
|
|
PHW_DEVICE_EXTENSION HwDeviceExtension,
|
|
PVIDEO_CLUT ClutBuffer,
|
|
ULONG ClutBufferSize
|
|
);
|
|
|
|
BOOLEAN CLIsPresent(
|
|
PHW_DEVICE_EXTENSION HwDeviceExtension
|
|
);
|
|
|
|
ULONG CLFindVmemSize(
|
|
PHW_DEVICE_EXTENSION HwDeviceExtension
|
|
);
|
|
|
|
VOID CLWriteRegistryInfo(
|
|
PHW_DEVICE_EXTENSION hwDeviceExtension,
|
|
BOOLEAN hdbrsten
|
|
);
|
|
|
|
VOID CLValidateModes(
|
|
PHW_DEVICE_EXTENSION HwDeviceExtension
|
|
);
|
|
|
|
VOID CLCopyModeInfo(
|
|
PHW_DEVICE_EXTENSION HwDeviceExtension,
|
|
PVIDEO_MODE_INFORMATION videoModes,
|
|
ULONG ModeIndex,
|
|
PMODETABLE ModeInfo
|
|
);
|
|
|
|
VP_STATUS CLSetMode(
|
|
PHW_DEVICE_EXTENSION HwDeviceExtension,
|
|
PVIDEO_MODE Mode
|
|
);
|
|
|
|
BOOLEAN CLSetMonitorType(
|
|
PHW_DEVICE_EXTENSION HwDeviceExtension,
|
|
USHORT VertScanlines,
|
|
UCHAR MonitorTypeVal
|
|
);
|
|
|
|
VP_STATUS CLPowerManagement(
|
|
PHW_DEVICE_EXTENSION HwDeviceExtension,
|
|
PVIDEO_POWER_MANAGEMENT pPMinfo,
|
|
BOOLEAN SetPowerState
|
|
);
|
|
|
|
BOOLEAN CLEnablePciBurst(
|
|
PHW_DEVICE_EXTENSION hwDeviceExtension
|
|
);
|
|
|
|
VP_STATUS CLFindLagunaOnPciBus(
|
|
PHW_DEVICE_EXTENSION hwDeviceExtension,
|
|
PVIDEO_ACCESS_RANGE pAccessRanges
|
|
);
|
|
|
|
VOID CLPatchModeTable (
|
|
PHW_DEVICE_EXTENSION HwDeviceExtension
|
|
);
|
|
|
|
VOID ClAllocateCommonBuffer(
|
|
PHW_DEVICE_EXTENSION HwDeviceExtension
|
|
);
|
|
|
|
VOID CLEnableTiling(
|
|
PHW_DEVICE_EXTENSION HwDeviceExtension,
|
|
PMODETABLE pReqModeTable
|
|
);
|
|
|
|
VP_STATUS CLEnablePCIConfigMMIO(
|
|
PHW_DEVICE_EXTENSION HwDeviceExtension
|
|
);
|
|
|
|
void SetMode(BYTE *pModeTable, BYTE *pMemory, BYTE * pBinaryData, ULONG SkipIO);
|
|
|
|
//
|
|
// The rest of this file isn't used.
|
|
//
|
|
|
|
#if 0
|
|
#if ENABLE_BUS_MASTERING
|
|
HW_DMA_RETURN CLStartDma(
|
|
PHW_DEVICE_EXTENSION HwDeviceExtension,
|
|
PVIDEO_REQUEST_PACKET RequestPacket,
|
|
PVOID pMappedUserEvent,
|
|
PVOID pDisplayEvent,
|
|
PVOID pDmaCompletionEvent
|
|
);
|
|
#endif
|
|
|
|
#if ENABLE_BUS_MASTERING
|
|
PUCHAR IoBuffer;
|
|
ULONG IoBufferSize;
|
|
PVOID DmaHandle;
|
|
#endif
|
|
#endif
|