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792 lines
24 KiB
792 lines
24 KiB
/*++
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Copyright (c) 1999, 2000 Microsoft Corporation
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Module Name:
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ehci.h
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Abstract:
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Definitions from Enhanced USB 2.0
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controller specification
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Environment:
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Kernel & user mode
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Revision History:
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1-1-00 : created jdunn
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--*/
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#ifndef EHCI_H
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#define EHCI_H
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#include <PSHPACK4.H>
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//
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// Don't use <PSHPACK1.H> on shared memory data structures that should only
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// be accessed using 4-byte load/store instructions (e.g use ld4 instructions
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// instead of ld1 instructions on ia64 machines).
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//
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// maximum time to wait for reset to go low in microseconds
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#define USBEHCI_MAX_RESET_TIME 500
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#define EHCI_PAGE_SIZE 0x1000
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//
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// Host Controler Hardware Registers as accessed in memory
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//
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//
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// HCLENGTHVERION - Capability Register Length / Interface Versoin Number
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//
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typedef union _HCLENGTHVERSION {
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ULONG ul;
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struct {
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ULONG HcCapLength:8; // 0-7
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ULONG Reserved:8; // 8-15
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ULONG HcVersion:16; // 16-31
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};
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} HCLENGTHVERSION, *PHCLENGTHVERSION;
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C_ASSERT((sizeof(HCLENGTHVERSION) == sizeof(ULONG)));
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//
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// HCSPARAMS - Structural Parameters
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//
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typedef union _HCSPARAMS {
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ULONG ul;
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struct {
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ULONG NumberOfPorts:4; // 0-3
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ULONG PortPowerControl:1; // 4
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ULONG Reserved1:3; // 5-7
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ULONG NumberOfPortsPerCompConroller:4; // 8-11
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ULONG NumberOfCompControllers:4; // 12-15
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ULONG PortLEDs:1; // 16
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ULONG Reserved2:15; // 17-31
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};
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} HCSPARAMS, *PHCSPARMS;
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C_ASSERT((sizeof(HCSPARAMS) == sizeof(ULONG)));
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//
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// HCCPARAMS - Capability Parameters
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//
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typedef union _HCCPARAMS {
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ULONG ul;
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struct {
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ULONG Bit64Addressing:1; // 0
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ULONG ProgramableFrameList:1; // 1
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ULONG AsynSchedulePark:1; // 2
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ULONG Reserved1:1; // 3
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ULONG IsochronousThreshold:4; // 4-7
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ULONG EECP:8; // 8-15
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ULONG Reserved2:16; // 16-31
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};
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} HCCPARAMS, *PHCCPARMS;
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C_ASSERT((sizeof(HCCPARAMS) == sizeof(ULONG)));
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//
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// EECP Register
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//
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#define EECP_CAP_RESERVED 0x00
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#define EECP_PRE_OS_HANDOFF 0x01
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typedef union _HC_EECP {
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ULONG ul;
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struct {
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ULONG CapId:8; // 0-7
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ULONG NextCap:8; // 8-15
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ULONG CapData:16; // 16-31
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};
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} HC_EECP, *PHC_EECP;
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C_ASSERT((sizeof(HC_EECP) == sizeof(ULONG)));
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//
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// EECP BIOS Registers
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//
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typedef union _USBLEGSUP {
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ULONG ul;
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struct {
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ULONG CapId:8; // 0-7
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ULONG NextCap:8; // 8-15
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ULONG HcBIOSowned:1; // 16
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ULONG Reserved1:7; // 17-23
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ULONG HcOSowned:1; // 24
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ULONG Reserved2:7; // 25-31
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};
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} USBLEGSUP, *PUSBLEGSUP;
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C_ASSERT((sizeof(USBLEGSUP) == sizeof(ULONG)));
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typedef union _USBLEGCTLSTS {
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ULONG ul;
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struct {
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ULONG UsbSMIEnable:1; // 0
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ULONG SMIonUSBErrorEn:1; // 1
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ULONG SMIonPortChangeEn:1; // 2
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ULONG SMIonFrameListRolloverEn:1; // 3
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ULONG SMIonHostSystemErrorEn:1; // 4
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ULONG SMIonAsyncAdvanceEn:1; // 5
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ULONG Reserved1:7; // 6-12
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ULONG SMIonOSownershipEn:1; // 13
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ULONG SMIonPCICommandEn:1; // 14
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ULONG SMIonBAREn:1; // 15
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ULONG SMIonUSBComplete:1; // 16
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ULONG SMIonUSBError:1; // 17
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ULONG SMIonPortChange:1; // 18
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ULONG SMIonFrameListRollover:1; // 19
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ULONG SMIonHostSystemError:1; // 20
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ULONG SMIonAsyncAdvance:1; // 21
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ULONG Reserved2:7; // 22-28
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ULONG SMIonOSownership:1; // 29
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ULONG SMIonPCIcommand:1; // 30
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ULONG SMIonBAR:1; // 31
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};
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} USBLEGCTLSTS, *PUSBLEGCTLSTS;
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C_ASSERT((sizeof(USBLEGCTLSTS) == sizeof(ULONG)));
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typedef struct _USB_LEGACYBIOS_REGISTERS {
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USBLEGSUP Caps;
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USBLEGCTLSTS CtlSts;
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} USB_LEGACYBIOS_REGISTERS, *PUSB_LEGACYBIOS_REGISTERS;
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C_ASSERT((sizeof(USB_LEGACYBIOS_REGISTERS) == (2 * sizeof(ULONG))));
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//
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// CAPABILITIES REGISTER
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//
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typedef struct _HC_CAPABILITIES_REGISTER {
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HCLENGTHVERSION HcLengthVersion;
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HCSPARAMS HcStructuralParameters;
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HCCPARAMS HcCapabilityParameters;
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} HC_CAPABILITIES_REGISTER, *PHC_CAPABILITIES_REGISTER;
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C_ASSERT((sizeof(HC_CAPABILITIES_REGISTER) == (3 * sizeof(ULONG))));
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//
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// USBCMD - USB Command Register
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//
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//
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// Definitions for HC_QTD_TOKEN.Pid
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//
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#define HcCmd_FrameListSizeIs1024 0
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#define HcCmd_FrameListSizeIs512 1
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#define HcCmd_FrameListSizeIs256 2
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typedef union _USBCMD {
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ULONG ul;
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struct {
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ULONG HostControllerRun:1; // 0
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ULONG HostControllerReset:1; // 1
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ULONG FrameListSize:2; // 2-3
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ULONG PeriodicScheduleEnable:1; // 4
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ULONG AsyncScheduleEnable:1; // 5
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ULONG IntOnAsyncAdvanceDoorbell:1;// 6
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ULONG HostControllerLightReset:1; // 7
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ULONG Reserved1:8; // 8-15
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ULONG InterruptThreshold:8; // 16-23
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ULONG Reserved2:8; // 24-31
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};
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} USBCMD, *PUSBCMD;
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C_ASSERT((sizeof(USBCMD) == sizeof(ULONG)));
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//
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// USBSTS - USB Status Register
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//
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#define HcInterruptStatusMask 0x0000003F
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#define HcInt_IntOnasyncAdvance 0x00000020
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#define HcInt_HostSystemError 0x00000010
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#define HcInt_FrameListRollover 0x00000008
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#define HcInt_PortChangeDetect 0x00000004
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#define HcInt_UsbError 0x00000002
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#define HcInt_UsbInterrupt 0x00000001
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typedef union _USBSTS {
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ULONG ul;
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struct {
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// controller interrupt status bits
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ULONG UsbInterrupt:1; // 0
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ULONG UsbError:1; // 1
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ULONG PortChangeDetect:1; // 2
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ULONG FrameListRollover:1; // 3
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ULONG HostSystemError:1; // 4
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ULONG IntOnAsyncAdvance:1; // 5
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ULONG ReservedStatus:6; // 6-11
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// controller status
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ULONG HcHalted:1; // 12
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ULONG Reclimation:1; // 13
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ULONG PeriodicScheduleStatus:1; // 14
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ULONG AsyncScheduleStatus:1; // 15
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ULONG Reserved:16; // 16-31
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};
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} USBSTS, *PUSBSTS;
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C_ASSERT((sizeof(USBSTS) == sizeof(ULONG)));
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//
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// USBINTR - USB Interrupt Enable Register
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//
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typedef union _USBINTR {
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ULONG ul;
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struct {
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ULONG UsbInterrupt:1; // 0
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ULONG UsbError:1; // 1
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ULONG PortChangeDetect:1; // 2
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ULONG FrameListRollover:1; // 3
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ULONG HostSystemError:1; // 4
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ULONG IntOnAsyncAdvance:1; // 5
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//HostSystemError
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//HostControllerProcessError
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ULONG Reserved:26; // 6-31
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};
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} USBINTR, *PUSBINTR;
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C_ASSERT((sizeof(USBINTR) == sizeof(ULONG)));
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//
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// FRNUM - Frame Number Register
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//
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typedef union _FRINDEX {
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ULONG ul;
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struct {
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ULONG FrameListCurrentIndex:14;
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ULONG Reserved:18;
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};
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} FRINDEX, *PFRINDEX;
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C_ASSERT((sizeof(FRINDEX) == sizeof(ULONG)));
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//
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// CONFIGFLAG -
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//
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typedef union _CONFIGFLAG {
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ULONG ul;
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struct {
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ULONG RoutePortsToEHCI:1;
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ULONG Reserved:31;
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};
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} CONFIGFLAG, *PCONFIGFLAG;
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C_ASSERT((sizeof(CONFIGFLAG) == sizeof(ULONG)));
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//
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// PORTSC - Port Status and Control Register
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//
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typedef union _PORTSC {
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ULONG ul;
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struct {
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ULONG PortConnect:1; // 0
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ULONG PortConnectChange:1; // 1
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ULONG PortEnable:1; // 2
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ULONG PortEnableChange:1; // 3
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ULONG OvercurrentActive:1; // 4
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ULONG OvercurrentChange:1; // 5
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ULONG ForcePortResume:1; // 6
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ULONG PortSuspend:1; // 7
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ULONG PortReset:1; // 8
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ULONG HighSpeedDevice:1; // 9
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ULONG LineStatus:2; // 10-11
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ULONG PortPower:1; // 12
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ULONG PortOwnedByCC:1; // 13
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ULONG PortIndicator:2; // 14-15
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ULONG PortTestControl:4; // 16-19
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ULONG WakeOnConnect:1; // 20
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ULONG WakeOnDisconnect:1; // 21
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ULONG WakeOnOvercurrent:1; // 22
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ULONG Reserved:9; // 23-31
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};
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} PORTSC, *PPORTSC;
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C_ASSERT((sizeof(PORTSC) == sizeof(ULONG)));
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// OPERATIONAL REGISTER
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typedef struct _HC_OPERATIONAL_REGISTER {
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// 00h
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USBCMD UsbCommand;
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USBSTS UsbStatus;
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USBINTR UsbInterruptEnable;
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FRINDEX UsbFrameIndex;
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// 10h
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HW_32BIT_PHYSICAL_ADDRESS SegmentSelector;
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HW_32BIT_PHYSICAL_ADDRESS PeriodicListBase;
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HW_32BIT_PHYSICAL_ADDRESS AsyncListAddr;
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//ULONG Reserved;
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ULONG PciTrigger;
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// 20h
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ULONG ReservedB0[4];
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// 30h
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ULONG ReservedB1[4];
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// 40h
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CONFIGFLAG ConfigFlag;
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PORTSC PortRegister[1];
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} HC_OPERATIONAL_REGISTER, *PHC_OPERATIONAL_REGISTER;
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//#define HcDTYPE_iTD 0 // iterative TD
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//#define HcDTYPE_QH 1 // queue head
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//#define HcDTYPE_siTD 2 // isochronousTD
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// note that bits 0,1,2 are used for QH type
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// bits 4, and 5 are used for the nak cnt in the
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// transfer overlay
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#define HW_LINK_FLAGS_MASK 0x0000001f
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typedef union _HW_LINK_POINTER {
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HW_32BIT_PHYSICAL_ADDRESS HwAddress;
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// this screws up the 64-bit compiler
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#if 0
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struct {
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ULONG Terminate:1; // 0
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ULONG DType:2; // 1-2
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ULONG ReservedMBZ:2; // 3-4
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ULONG PhysicalAddressBits:27; // 5-31
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};
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#endif
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} HW_LINK_POINTER, *PHW_LINK_POINTER;
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#define EHCI_TERMINATE_BIT 0x00000001 // 00001
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#define EHCI_DTYPE_QH 0x00000002 // 00010
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#define EHCI_DTYPE_SITD 0x00000004 // 00100
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#define EHCI_RsvdMBZ 0x00000018 // 11000
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#define EHCI_DTYPE_Mask 0x0000001E // 11110
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#define SET_T_BIT(addr) ((addr) |= EHCI_TERMINATE_BIT)
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#define SET_SITD(addr) do {\
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((addr) &= ~EHCI_DTYPE_Mask);\
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((addr) |= EHCI_DTYPE_SITD);\
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} while (0)
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#define SET_QH(addr) do {\
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((addr) &= ~EHCI_DTYPE_Mask);\
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((addr) |= EHCI_DTYPE_QH);\
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} while (0)
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C_ASSERT((sizeof(HW_LINK_POINTER) == sizeof(ULONG)));
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//
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// Isochronous Transfer Descriptor
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//
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typedef union _HC_ITD_BUFFER_POINTER0 {
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ULONG ul;
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struct {
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ULONG DeviceAddress:7; // 0-6
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ULONG Reserved:1; // 7
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ULONG EndpointNumber:4; // 8-11
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ULONG BufferPointer:20; // 12-31
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};
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} HC_ITD_BUFFER_POINTER0, *PHC_ITD_BUFFER_POINTER0;
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C_ASSERT((sizeof(HC_ITD_BUFFER_POINTER0) == sizeof(ULONG)));
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typedef union _HC_ITD_BUFFER_POINTER1 {
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ULONG ul;
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struct {
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ULONG MaxPacketSize:11; // 0-10
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ULONG Direction:1; // 11
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ULONG BufferPointer:20; // 12-31
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};
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} HC_ITD_BUFFER_POINTER1, *PHC_ITD_BUFFER_POINTER1;
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C_ASSERT((sizeof(HC_ITD_BUFFER_POINTER1) == sizeof(ULONG)));
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typedef union _HC_ITD_BUFFER_POINTER2 {
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ULONG ul;
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struct {
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ULONG Multi:2; // 0-1
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ULONG Reserved:10; // 2-11
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ULONG BufferPointer:20; // 12-31
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};
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} HC_ITD_BUFFER_POINTER2, *PHC_ITD_BUFFER_POINTER2;
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C_ASSERT((sizeof(HC_ITD_BUFFER_POINTER2) == sizeof(ULONG)));
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typedef union _HC_ITD_BUFFER_POINTER {
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ULONG ul;
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struct {
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ULONG Reserved:12; // 0-11
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ULONG BufferPointer:20; // 12-31
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};
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} HC_ITD_BUFFER_POINTER, *PHC_ITD_BUFFER_POINTER;
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C_ASSERT((sizeof(HC_ITD_BUFFER_POINTER) == sizeof(ULONG)));
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typedef union _HC_ITD_TRANSACTION {
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ULONG ul;
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struct {
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ULONG Offset:12; // 0-11
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ULONG PageSelect:3; // 12-14
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ULONG InterruptOnComplete:1; // 15
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ULONG Length:12; // 16-27
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ULONG XactError:1; // 28
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ULONG BabbleDetect:1; // 29
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ULONG DataBufferError:1; // 30
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ULONG Active:1; // 31
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};
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} HC_ITD_TRANSACTION, *PHC_ITD_TRANSACTION;
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C_ASSERT((sizeof(HC_ITD_TRANSACTION) == sizeof(ULONG)));
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typedef struct _HW_ISOCHRONOUS_TD {
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HW_LINK_POINTER NextLink;
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HC_ITD_TRANSACTION Transaction[8];
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HC_ITD_BUFFER_POINTER0 BufferPointer0;
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HC_ITD_BUFFER_POINTER1 BufferPointer1;
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HC_ITD_BUFFER_POINTER2 BufferPointer2;
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HC_ITD_BUFFER_POINTER BufferPointer3;
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HC_ITD_BUFFER_POINTER BufferPointer4;
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HC_ITD_BUFFER_POINTER BufferPointer5;
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HC_ITD_BUFFER_POINTER BufferPointer6;
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ULONG BufferPointer64[7];
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ULONG Pad[9];
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} HW_ISOCHRONOUS_TD, *PHW_ISOCHRONOUS_TD;
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C_ASSERT((sizeof(HW_ISOCHRONOUS_TD) == 128));
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//
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// Split Transaction Isochronous Transfer Descriptor
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//
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typedef union _HC_SITD_CAPS {
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ULONG ul;
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struct {
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ULONG DeviceAddress:7; // 0-6
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ULONG Reserved0:1; // 7
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ULONG EndpointNumber:4; // 8-11
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ULONG Reserved1:4; // 12-15
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ULONG HubAddress:7; // 16-22
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ULONG Reserved2:1; // 23
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ULONG PortNumber:7; // 24-30
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ULONG Direction:1; // 31
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};
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} HC_SITD_CAPS, *PHC_SITD_CAPS;
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C_ASSERT((sizeof(HC_SITD_CAPS) == sizeof(ULONG)));
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typedef union _HC_SITD_CONTROL {
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ULONG ul;
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struct {
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ULONG sMask:8; // 0-7
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ULONG cMask:8; // 8-15
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ULONG Reserved:16; // 16-31
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};
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} HC_SITD_CONTROL, *PHC_SITD_CONTROL;
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C_ASSERT((sizeof(HC_SITD_CONTROL) == sizeof(ULONG)));
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typedef union _HC_SITD_STATE {
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ULONG ul;
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struct {
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ULONG Reserved0:1; // 0
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ULONG SplitXState:1; // 1
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ULONG MissedMicroframe:1; // 2
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ULONG XactErr:1; // 3
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ULONG BabbleDetected:1; // 4
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ULONG DataBufferError:1; // 5
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ULONG ERR:1; // 6
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ULONG Active:1; // 7
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ULONG cProgMask:8; // 8-15
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ULONG BytesToTransfer:10; // 16-25
|
|
ULONG Reserved1:4; // 26-29
|
|
ULONG PageSelect:1; // 30
|
|
ULONG InterruptOnComplete:1; // 31
|
|
};
|
|
} HC_SITD_STATE, *PHC_SITD_STATE;
|
|
|
|
C_ASSERT((sizeof(HC_SITD_STATE) == sizeof(ULONG)));
|
|
|
|
// Tposition
|
|
#define TPOS_ALL 0
|
|
#define TPOS_BEGIN 1
|
|
|
|
typedef union _HC_SITD_BUFFER_POINTER1 {
|
|
ULONG ul;
|
|
struct {
|
|
ULONG Tcount:3; // 0-2
|
|
ULONG Tposition:2; // 3-4
|
|
ULONG Reseved:7; // 5-11
|
|
ULONG BufferPointer:20; // 12-31
|
|
};
|
|
} HC_SITD_BUFFER_POINTER1, *PHC_SITD_BUFFER_POINTER1;
|
|
|
|
C_ASSERT((sizeof(HC_SITD_BUFFER_POINTER1) == sizeof(ULONG)));
|
|
|
|
typedef union _HC_SITD_BUFFER_POINTER0 {
|
|
ULONG ul;
|
|
struct {
|
|
ULONG CurrentOffset:12; // 0-11
|
|
ULONG BufferPointer:20; // 12-31
|
|
};
|
|
} HC_SITD_BUFFER_POINTER0, *PHC_SITD_BUFFER_POINTER0;
|
|
|
|
C_ASSERT((sizeof(HC_SITD_BUFFER_POINTER0) == sizeof(ULONG)));
|
|
|
|
typedef struct _HW_SPLIT_ISOCHRONOUS_TD {
|
|
HW_LINK_POINTER NextLink;
|
|
HC_SITD_CAPS Caps;
|
|
HC_SITD_CONTROL Control;
|
|
HC_SITD_STATE State;
|
|
HC_SITD_BUFFER_POINTER0 BufferPointer0;
|
|
HC_SITD_BUFFER_POINTER1 BufferPointer1;
|
|
HW_LINK_POINTER BackPointer;
|
|
ULONG BufferPointer64_0;
|
|
ULONG BufferPointer64_1;
|
|
ULONG Pad[7];
|
|
} HW_SPLIT_ISOCHRONOUS_TD, *PHW_SPLIT_ISOCHRONOUS_TD;
|
|
|
|
|
|
C_ASSERT((sizeof(HW_SPLIT_ISOCHRONOUS_TD) == 64));
|
|
|
|
//
|
|
// Queue Element Transfer Descriptor
|
|
//
|
|
|
|
//
|
|
// Definitions for HC_QTD_TOKEN.Pid
|
|
//
|
|
|
|
#define HcTOK_Out 0
|
|
#define HcTOK_In 1
|
|
#define HcTOK_Setup 2
|
|
#define HcTOK_Reserved 3
|
|
|
|
#define HcTOK_PingDoOut 0
|
|
#define HcTOK_PingDoPing 1
|
|
|
|
#define HcTOK_Toggle0 0
|
|
#define HcTOK_Toggle1 1
|
|
|
|
typedef union _HC_BUFFER_POINTER {
|
|
ULONG ul;
|
|
struct {
|
|
ULONG CurrentOffset:12; // 0-11
|
|
ULONG BufferPointer:20; // 12-31
|
|
};
|
|
} HC_BUFFER_POINTER, *PHC_BUFFER_POINTER;
|
|
|
|
C_ASSERT((sizeof(HC_BUFFER_POINTER) == sizeof(ULONG)));
|
|
|
|
|
|
typedef union _HC_QTD_TOKEN {
|
|
ULONG ul;
|
|
struct {
|
|
// status bits
|
|
ULONG PingState:1; // 0
|
|
ULONG SplitXstate:1; // 1
|
|
ULONG MissedMicroFrame:1; // 2
|
|
ULONG XactErr:1; // 3
|
|
ULONG BabbleDetected:1; // 4
|
|
ULONG DataBufferError:1; // 5
|
|
ULONG Halted:1; // 6
|
|
ULONG Active:1; // 7
|
|
|
|
ULONG Pid:2; // 8-9
|
|
ULONG ErrorCounter:2; // 10-11
|
|
ULONG C_Page:3; // 12-14
|
|
ULONG InterruptOnComplete:1; // 15
|
|
|
|
ULONG BytesToTransfer:15; // 16-30
|
|
ULONG DataToggle:1; // 31
|
|
};
|
|
} HC_QTD_TOKEN, *PHC_QTD_TOKEN;
|
|
|
|
C_ASSERT((sizeof(HC_QTD_TOKEN) == sizeof(ULONG)));
|
|
|
|
|
|
typedef struct _HW_QUEUE_ELEMENT_TD {
|
|
HW_LINK_POINTER Next_qTD;
|
|
HW_LINK_POINTER AltNext_qTD;
|
|
HC_QTD_TOKEN Token;
|
|
HC_BUFFER_POINTER BufferPage[5];
|
|
ULONG BufferPage64[5];
|
|
ULONG Pad[3];
|
|
} HW_QUEUE_ELEMENT_TD, *PHW_QUEUE_ELEMENT_TD;
|
|
|
|
C_ASSERT((sizeof(HW_QUEUE_ELEMENT_TD) == 64));
|
|
|
|
|
|
typedef union HC_OVLAY_8 {
|
|
ULONG ul;
|
|
struct {
|
|
// status bits
|
|
ULONG CprogMask:8; // 0-7
|
|
ULONG Buffer:24;
|
|
};
|
|
} HC_OVLAY_8, *PHC_OVLAY_8;
|
|
|
|
C_ASSERT((sizeof(HC_OVLAY_8) == sizeof(ULONG)));
|
|
|
|
typedef union HC_OVLAY_9 {
|
|
ULONG ul;
|
|
struct {
|
|
// status bits
|
|
ULONG fTag:5; // 0-4
|
|
ULONG Sbytes:7; // 5-11
|
|
ULONG Buffer:20;
|
|
};
|
|
} HC_OVLAY_9, *PHC_OVLAY_9;
|
|
|
|
C_ASSERT((sizeof(HC_OVLAY_9) == sizeof(ULONG)));
|
|
|
|
|
|
typedef struct _HW_OVERLAY_AREA {
|
|
HW_LINK_POINTER Next_qTD; // dw4
|
|
HW_LINK_POINTER AltNext_qTD; // dw5
|
|
HC_QTD_TOKEN Token; // dw6
|
|
HC_BUFFER_POINTER BufferPage0; // dw7
|
|
HC_OVLAY_8 OverlayDw8;
|
|
HC_OVLAY_9 OverlayDw9;
|
|
HC_BUFFER_POINTER BufferPage3;
|
|
HC_BUFFER_POINTER BufferPage4;
|
|
ULONG BufferPage64[5];
|
|
ULONG Pad[3];
|
|
} HW_OVERLAY_AREA, *PHW_OVERLAY_AREA;
|
|
|
|
C_ASSERT((sizeof(HW_QUEUE_ELEMENT_TD) == 64));
|
|
|
|
//
|
|
// General Transfer Descriptor
|
|
//
|
|
|
|
typedef union _HW_TRANSFER_DESCRIPTOR {
|
|
HW_QUEUE_ELEMENT_TD qTD;
|
|
HW_OVERLAY_AREA Ov;
|
|
} HW_TRANSFER_DESCRIPTOR, *PHW_TRANSFER_DESCRIPTOR;
|
|
|
|
C_ASSERT((sizeof(HW_TRANSFER_DESCRIPTOR) == 64));
|
|
|
|
|
|
//
|
|
// Definitions for HC_ENDPOINT_CHARACTERSITICS.DataToggleControl
|
|
//
|
|
#define HcEPCHAR_Ignore_Toggle 0 // ignore DT bit from incomming QTD
|
|
#define HcEPCHAR_Toggle_From_qTD 1 // DT from incomming QTD
|
|
|
|
//
|
|
// Definitions for HC_ENDPOINT_CHARACTERSITICS.EndpointSpeed
|
|
//
|
|
|
|
#define HcEPCHAR_FullSpeed 0 // 12Mbs
|
|
#define HcEPCHAR_LowSpeed 1 // 1.5Mbs
|
|
#define HcEPCHAR_HighSpeed 2 // 480Mbs
|
|
#define HcEPCHAR_Reserved 3
|
|
|
|
|
|
typedef union _HC_ENDPOINT_CHARACTERSITICS {
|
|
ULONG ul;
|
|
struct {
|
|
ULONG DeviceAddress:7; // 0-6
|
|
ULONG Reserved1:1; // 7
|
|
ULONG EndpointNumber:4; // 8-11
|
|
ULONG EndpointSpeed:2; // 12-13
|
|
ULONG DataToggleControl:1; // 14
|
|
ULONG HeadOfReclimationList:1; // 15
|
|
ULONG MaximumPacketLength:11; // 16-26
|
|
ULONG ControlEndpointFlag:1; // 27
|
|
ULONG NakReloadCount:4; // 28-31
|
|
} ;
|
|
} HC_ENDPOINT_CHARACTERSITICS, *PHC_ENDPOINT_CHARACTERSITICS;
|
|
|
|
C_ASSERT((sizeof(HC_ENDPOINT_CHARACTERSITICS) == sizeof(ULONG)));
|
|
|
|
|
|
typedef union _HC_ENDPOINT_CAPABILITIES {
|
|
ULONG ul;
|
|
struct {
|
|
ULONG InterruptScheduleMask:8; // 0-7
|
|
ULONG SplitCompletionMask:8; // 8-15
|
|
ULONG HubAddress:7; // 16-22
|
|
ULONG PortNumber:7; // 23-29
|
|
ULONG HighBWPipeMultiplier:2; // 30-31
|
|
};
|
|
} HC_ENDPOINT_CAPABILITIES, *PHC_ENDPOINT_CAPABILITIES;
|
|
|
|
C_ASSERT((sizeof(HC_ENDPOINT_CAPABILITIES) == sizeof(ULONG)));
|
|
|
|
//
|
|
// Queue Head Descriptor
|
|
//
|
|
|
|
typedef struct _HW_QUEUEHEAD_DESCRIPTOR {
|
|
|
|
HW_LINK_POINTER HLink; // horizontal link ptr dw:0
|
|
HC_ENDPOINT_CHARACTERSITICS EpChars; // dw:1
|
|
HC_ENDPOINT_CAPABILITIES EpCaps; // dw:2
|
|
HW_LINK_POINTER CurrentTD; // dw:3
|
|
HW_TRANSFER_DESCRIPTOR Overlay; // dw:4-11
|
|
|
|
} HW_QUEUEHEAD_DESCRIPTOR, *PHW_QUEUEHEAD_DESCRIPTOR;
|
|
|
|
C_ASSERT((sizeof(HW_QUEUEHEAD_DESCRIPTOR) == 80));
|
|
|
|
#include <POPPACK.H>
|
|
|
|
#endif /* EHCI_H */
|