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570 lines
25 KiB
570 lines
25 KiB
/*++
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Copyright (c) 1999 Microsoft Corporation
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Module Name:
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openhci.h
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Abstract:
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Definitions from OPENHCI 1.0 USB specification
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Environment:
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Kernel & user mode
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Revision History:
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12-28-95 : created jfuller & kenray
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--*/
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#ifndef OPENHCI_H
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#define OPENHCI_H
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#include <PSHPACK4.H>
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//
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// Don't use <PSHPACK1.H> on shared memory data structures that should only
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// be accessed using 4-byte load/store instructions (e.g use ld4 instructions
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// instead of ld1 instructions on ia64 machines).
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//
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#define MAXIMUM_OVERHEAD 210
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#define OHCI_PAGE_SIZE 0x1000
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// #define OHCI_PAGE_SIZE 0x20
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#define OHCI_PAGE_SIZE_MASK (OHCI_PAGE_SIZE - 1)
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//
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// 7.1.1 HcRevision Register
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// Definition of Host Controller Revision register
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//
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typedef union _HC_REVISION {
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ULONG ul;
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struct {
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ULONG Rev:8;
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ULONG :24;
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};
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} HC_REVISION, *PHC_REVISION;
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C_ASSERT(sizeof(HC_REVISION) == 4);
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//
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// 7.1.2 HcControl Register
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// Definition of Host Controller Control register
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//
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typedef union _HC_CONTROL {
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ULONG ul;
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struct {
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ULONG ControlBulkServiceRatio:2;
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ULONG PeriodicListEnable:1;
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ULONG IsochronousEnable:1;
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ULONG ControlListEnable:1;
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ULONG BulkListEnable:1;
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ULONG HostControllerFunctionalState:2;
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ULONG InterruptRouting:1;
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ULONG RemoteWakeupConnected:1;
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ULONG RemoteWakeupEnable:1;
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ULONG :21;
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};
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} HC_CONTROL, *PHC_CONTROL;
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C_ASSERT(sizeof(HC_CONTROL) == 4);
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#define HcCtrl_CBSR_MASK 0x00000003L
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#define HcCtrl_CBSR_1_to_1 0x00000000L
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#define HcCtrl_CBSR_2_to_1 0x00000001L
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#define HcCtrl_CBSR_3_to_1 0x00000002L
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#define HcCtrl_CBSR_4_to_1 0x00000003L
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#define HcCtrl_PeriodicListEnable 0x00000004L
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#define HcCtrl_IsochronousEnable 0x00000008L
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#define HcCtrl_ControlListEnable 0x00000010L
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#define HcCtrl_BulkListEnable 0x00000020L
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#define HcCtrl_ListEnableMask 0x00000038L
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#define HcCtrl_HCFS_MASK 0x000000C0L
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#define HcCtrl_HCFS_USBReset 0x00000000L
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#define HcCtrl_HCFS_USBResume 0x00000040L
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#define HcCtrl_HCFS_USBOperational 0x00000080L
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#define HcCtrl_HCFS_USBSuspend 0x000000C0L
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#define HcCtrl_InterruptRouting 0x00000100L
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#define HcCtrl_RemoteWakeupConnected 0x00000200L
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#define HcCtrl_RemoteWakeupEnable 0x00000400L
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#define HcHCFS_USBReset 0x00000000
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#define HcHCFS_USBResume 0x00000001
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#define HcHCFS_USBOperational 0x00000002
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#define HcHCFS_USBSuspend 0x00000003
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//
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// 7.1.3 HcCommandStatus Register
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// Definition of Host Controller Command/Status register
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//
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typedef union _HC_COMMAND_STATUS {
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ULONG ul; // use HcCmd flags below
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struct {
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ULONG HostControllerReset:1;
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ULONG ControlListFilled:1;
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ULONG BulkListFilled:1;
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ULONG OwnershipChangeRequest:1;
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ULONG :12;
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ULONG SchedulingOverrunCount:2;
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ULONG :14;
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};
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} HC_COMMAND_STATUS, *PHC_COMMAND_STATUS;
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C_ASSERT(sizeof(HC_COMMAND_STATUS) == 4);
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#define HcCmd_HostControllerReset 0x00000001
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#define HcCmd_ControlListFilled 0x00000002
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#define HcCmd_BulkListFilled 0x00000004
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#define HcCmd_OwnershipChangeRequest 0x00000008
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#define HcCmd_SOC_Mask 0x00030000
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#define HcCmd_SOC_Offset 16
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#define HcCmd_SOC_Mask_LowBits 0x00000003
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//
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// 7.3.1 HcFmInterval Register
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// Definition of Host Controller Frame Interval register
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//
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typedef union _HC_FM_INTERVAL {
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ULONG ul; // use HcFmI flags below
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struct {
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ULONG FrameInterval:14;
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ULONG :2;
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ULONG FSLargestDataPacket:15;
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ULONG FrameIntervalToggle:1;
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};
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} HC_FM_INTERVAL, *PHC_FM_INTERVAL;
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C_ASSERT(sizeof(HC_FM_INTERVAL) == 4);
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#define HcFmI_FRAME_INTERVAL_MASK 0x00003FFF
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#define HcFmI_FS_LARGEST_DATA_PACKET_MASK 0x7FFF0000
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#define HcFmI_FS_LARGEST_DATA_PACKET_SHIFT 16
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#define HcFmI_FRAME_INTERVAL_TOGGLE 0x80000000
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//
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// 7.3.2 HcFmRemaining Register
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// Definition of Host Controller Frame Remaining register
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//
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typedef union _HC_FM_REMAINING {
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ULONG ul;
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struct {
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ULONG FrameRemaining:14;
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ULONG :17;
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ULONG FrameRemainingToggle:1;
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};
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} HC_FM_REMAINING, *PHC_FM_REMAINING;
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C_ASSERT(sizeof(HC_FM_REMAINING) == 4);
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//
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// 7.3.3 HcFmNumber Register
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// Definition of Host Controller Frame Number register
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//
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typedef union _HC_FM_NUMBER {
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ULONG ul;
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struct {
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ULONG FrameNumber:16;
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ULONG :16;
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};
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} HC_FM_NUMBER, *PHC_FM_NUMBER;
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C_ASSERT(sizeof(HC_FM_NUMBER) == 4);
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#define HcFmNumber_MASK 0x0000FFFF
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#define HcFmNumber_RESERVED 0xFFFF0000
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//
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// 7.4.1 HcRhDescriptorA Register
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// Definition of Host Controller Root Hub DescriptorA register
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//
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typedef union _HC_RH_DESCRIPTOR_A {
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ULONG ul;
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struct {
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ULONG NumberDownstreamPorts:8;
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ULONG HubChars:16;
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ULONG PowerOnToPowerGoodTime:8;
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} s;
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} HC_RH_DESCRIPTOR_A, *PHC_RH_DESCRIPTOR_A;
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C_ASSERT(sizeof(HC_RH_DESCRIPTOR_A) == 4);
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#define HcDescA_PowerSwitchingModePort 0x00000100L
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#define HcDescA_NoPowerSwitching 0x00000200L
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#define HcDescA_DeviceType 0x00000400L
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#define HcDescA_OvercurrentProtectionMode 0x00000800L
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#define HcDescA_NoOvercurrentProtection 0x00001000L
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// HcRhDescriptorA reserved bits which should not be set. Note that although
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// the NumberDownstreamPorts field is 8 bits wide, the maximum number of ports
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// supported by the OpenHCI specification is 15.
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//
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#define HcDescA_RESERVED 0x00FFE0F0L
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//
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// 7.4.2 HcRhDescriptorB Register
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// Definition of Host Controller Root Hub DescritorB register
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//
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typedef union _HC_RH_DESCRIPTOR_B {
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ULONG ul;
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struct {
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USHORT DeviceRemovableMask;
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USHORT PortPowerControlMask;
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};
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} HC_RH_DESCRIPTOR_B, *PHC_RH_DESCRIPTOR_B;
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C_ASSERT(sizeof(HC_RH_DESCRIPTOR_B) == 4);
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//
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// Host Controler Hardware Registers as accessed in memory
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//
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typedef struct _HC_OPERATIONAL_REGISTER {
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// 0 0x00 - 0,4,8,c
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HC_REVISION HcRevision;
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HC_CONTROL HcControl;
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HC_COMMAND_STATUS HcCommandStatus;
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ULONG HcInterruptStatus; // use HcInt flags below
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// 1 0x10
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ULONG HcInterruptEnable; // use HcInt flags below
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ULONG HcInterruptDisable; // use HcInt flags below
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ULONG HcHCCA; // physical pointer to Host Controller Communications Area
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ULONG HcPeriodCurrentED; // physical ptr to current periodic ED
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// 2 0x20
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ULONG HcControlHeadED; // physical ptr to head of control list
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ULONG HcControlCurrentED; // physical ptr to current control ED
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ULONG HcBulkHeadED; // physical ptr to head of bulk list
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ULONG HcBulkCurrentED; // physical ptr to current bulk ED
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// 3 0x30
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ULONG HcDoneHead; // physical ptr to internal done queue
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HC_FM_INTERVAL HcFmInterval;
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HC_FM_REMAINING HcFmRemaining;
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ULONG HcFmNumber;
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// 4 0x40
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ULONG HcPeriodicStart;
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ULONG HcLSThreshold;
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HC_RH_DESCRIPTOR_A HcRhDescriptorA;
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HC_RH_DESCRIPTOR_B HcRhDescriptorB;
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// 5 0x50
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ULONG HcRhStatus; // use HcRhS flags below
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ULONG HcRhPortStatus[15]; // use HcRhPS flags below
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} HC_OPERATIONAL_REGISTER, *PHC_OPERATIONAL_REGISTER;
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C_ASSERT(sizeof(HC_OPERATIONAL_REGISTER) == (0x54 + 4 * 15));
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//
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// 7.1.4 HcInterrruptStatus Register
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// 7.1.5 HcInterruptEnable Register
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// 7.1.6 HcInterruptDisable Register
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//
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#define HcInt_SchedulingOverrun 0x00000001L
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#define HcInt_WritebackDoneHead 0x00000002L
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#define HcInt_StartOfFrame 0x00000004L
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#define HcInt_ResumeDetected 0x00000008L
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#define HcInt_UnrecoverableError 0x00000010L
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#define HcInt_FrameNumberOverflow 0x00000020L
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#define HcInt_RootHubStatusChange 0x00000040L
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#define HcInt_OwnershipChange 0x40000000L
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#define HcInt_MasterInterruptEnable 0x80000000L
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//
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// 7.4.3 HcRhStatus Register
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//
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#define HcRhS_LocalPowerStatus 0x00000001 // read only
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#define HcRhS_OverCurrentIndicator 0x00000002 // read only
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#define HcRhS_DeviceRemoteWakeupEnable 0x00008000 // read only
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#define HcRhS_LocalPowerStatusChange 0x00010000 // read only
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#define HcRhS_OverCurrentIndicatorChange 0x00020000 // read only
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#define HcRhS_ClearGlobalPower 0x00000001 // write only
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#define HcRhS_SetRemoteWakeupEnable 0x00008000 // write only
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#define HcRhS_SetGlobalPower 0x00010000 // write only
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#define HcRhS_ClearOverCurrentIndicatorChange 0x00020000 // write only
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#define HcRhS_ClearRemoteWakeupEnable 0x80000000 // write only
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//
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// 7.4.4 HcRhPortStatus Register
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//
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//
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// The bits in this register have a double meaning depending
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// on if you read or write them
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//
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#define HcRhPS_CurrentConnectStatus 0x00000001 // read only
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#define HcRhPS_PortEnableStatus 0x00000002 // read only
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#define HcRhPS_PortSuspendStatus 0x00000004 // read only
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#define HcRhPS_PortOverCurrentIndicator 0x00000008 // read only
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#define HcRhPS_PortResetStatus 0x00000010 // read only
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#define HcRhPS_PortPowerStatus 0x00000100 // read only
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#define HcRhPS_LowSpeedDeviceAttached 0x00000200 // read only
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#define HcRhPS_ConnectStatusChange 0x00010000 // read only
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#define HcRhPS_PortEnableStatusChange 0x00020000 // read only
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#define HcRhPS_PortSuspendStatusChange 0x00040000 // read only
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#define HcRhPS_OverCurrentIndicatorChange 0x00080000 // read only
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#define HcRhPS_PortResetStatusChange 0x00100000 // read only
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#define HcRhPS_ClearPortEnable 0x00000001 // write only
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#define HcRhPS_SetPortEnable 0x00000002 // write only
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#define HcRhPS_SetPortSuspend 0x00000004 // write only
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#define HcRhPS_ClearPortSuspend 0x00000008 // write only
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#define HcRhPS_SetPortReset 0x00000010 // write only
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#define HcRhPS_SetPortPower 0x00000100 // write only
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#define HcRhPS_ClearPortPower 0x00000200 // write only
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#define HcRhPS_ClearConnectStatusChange 0x00010000 // write only
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#define HcRhPS_ClearPortEnableStatusChange 0x00020000 // write only
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#define HcRhPS_ClearPortSuspendStatusChange 0x00040000 // write only
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#define HcRhPS_ClearPortOverCurrentChange 0x00080000 // write only
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#define HcRhPS_ClearPortResetStatusChange 0x00100000 // write only
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#define HcRhPS_RESERVED (~(HcRhPS_CurrentConnectStatus | \
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HcRhPS_PortEnableStatus | \
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HcRhPS_PortSuspendStatus | \
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HcRhPS_PortOverCurrentIndicator | \
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HcRhPS_PortResetStatus | \
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HcRhPS_PortPowerStatus | \
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HcRhPS_LowSpeedDeviceAttached | \
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HcRhPS_ConnectStatusChange | \
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HcRhPS_PortEnableStatusChange | \
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HcRhPS_PortSuspendStatusChange | \
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HcRhPS_OverCurrentIndicatorChange | \
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HcRhPS_PortResetStatusChange \
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))
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typedef struct _HCCA_BLOCK {
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ULONG HccaInterruptTable[32]; // physical pointer to interrupt lists
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USHORT HccaFrameNumber; // 16-bit current frame number
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USHORT HccaPad1; // When the HC updates
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// HccaFrameNumber, it sets
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// this word to zero.
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ULONG HccaDoneHead; // pointer to done queue
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ULONG Reserved[30]; // pad to 256 bytes
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} HCCA_BLOCK, *PHCCA_BLOCK;
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// this size is defined in the
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// OpenHCI Specification it should always be 256 bytes
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C_ASSERT (sizeof(HCCA_BLOCK) == 256);
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//
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// Host Controller Endpoint Descriptor Control DWORD
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//
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typedef union _HC_ENDPOINT_CONTROL {
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ULONG Control; // use HcEDControl flags below
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struct {
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ULONG FunctionAddress:7;
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ULONG EndpointNumber:4;
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ULONG Direction:2; // use HcEDDirection flags below
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ULONG LowSpeed:1;
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ULONG sKip:1;
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ULONG Isochronous:1;
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ULONG MaxPacket:11;
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ULONG Unused:5; //available for software use
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};
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} HC_ENDPOINT_CONTROL, *PHC_ENDPOINT_CONTROL;
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//
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// Definitions for HC_ENDPOINT_CONTROL.Control
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//
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#define HcEDControl_MPS_MASK 0x07FF0000 // Maximum Packet Size field
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#define HcEDControl_MPS_SHIFT 16 // Shift Count for MPS
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#define HcEDControl_ISOCH 0x00008000 // Bit set for isochronous endpoints
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#define HcEDControl_SKIP 0x00004000 // Bit tells hw to skip this endpoint
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#define HcEDControl_LOWSPEED 0x00002000 // Bit set if device is a low speed device
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#define HcEDControl_DIR_MASK 0x00001800 // Transfer direction field
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#define HcEDControl_DIR_DEFER 0x00000000 // Defer direction select to TD (Control Endpoints)
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#define HcEDControl_DIR_OUT 0x00000800 // Direction is from host to device
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#define HcEDControl_DIR_IN 0x00001000 // Direction is from device to host
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#define HcEDControl_EN_MASK 0x00000780 // Endpoint Number field
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#define HcEDControl_EN_SHIFT 7 // Shift Count for EN
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#define HcEDControl_FA_MASK 0x0000007F // Function Address field
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#define HcEDControl_FA_SHIFT 0 // Shift Count for FA
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//
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// Definitions for HC_ENDPOINT_CONTROL.Direction
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//
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#define HcEDDirection_Defer 0 // Defer direction to TD (Control Endpoints)
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#define HcEDDirection_Out 1 // Direction from host to device
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#define HcEDDirection_In 2 // Direction from device to host
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//
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// Host Controller Endpoint Descriptor, refer to Section 4.2, Endpoint Descriptor
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//
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typedef struct _HW_ENDPOINT_DESCRIPTOR {
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HC_ENDPOINT_CONTROL; // dword 0
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HW_32BIT_PHYSICAL_ADDRESS TailP; //physical pointer to HC_TRANSFER_DESCRIPTOR
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HW_32BIT_PHYSICAL_ADDRESS HeadP; //flags + phys ptr to HC_TRANSFER_DESCRIPTOR
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HW_32BIT_PHYSICAL_ADDRESS NextED; //phys ptr to HC_ENDPOINT_DESCRIPTOR
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} HW_ENDPOINT_DESCRIPTOR, *PHW_ENDPOINT_DESCRIPTOR;
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// NOTE: this structure MUST have 16 byte alignment for the hardware
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C_ASSERT(sizeof(HW_ENDPOINT_DESCRIPTOR) == 16);
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//
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// Definitions for HC_ENDPOINT_DESCRIPTOR.HeadP
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//
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#define HcEDHeadP_FLAGS 0x0000000F //mask for flags in HeadP
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#define HcEDHeadP_HALT 0x00000001 //hardware stopped bit
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#define HcEDHeadP_CARRY 0x00000002 //hardware toggle carry bit
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//
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// HCD Isochronous offset/status words
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//
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typedef union _HC_OFFSET_PSW {
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struct {
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USHORT Offset:13; // Offset within two pages of packet buffer
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USHORT Ones:3; // should be 111b when in Offset format
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};
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struct {
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USHORT Size:11; // Size of packet received
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USHORT :1; // reserved
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USHORT ConditionCode:4; // use HcCC flags below
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};
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USHORT PSW; // use HcPSW flags below
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} HC_OFFSET_PSW, *PHC_OFFSET_PSW;
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//
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// Definitions for HC_OFFSET_PSW.PSW
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//
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#define HcPSW_OFFSET_MASK 0x0FFF // Packet buffer offset field
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#define HcPSW_SECOND_PAGE 0x1000 // Is this packet on 2nd page
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#define HcPSW_ONES 0xE000 // The ones for Offset form
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#define HcPSW_CONDITION_CODE_MASK 0xF000 // Packet ConditionCode field
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#define HcPSW_CONDITION_CODE_SHIFT 12 // shift count for Code
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#define HcPSW_RETURN_SIZE 0x07FF // The size field.
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//
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// HCD Transfer Descriptor Control DWord
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//
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typedef union _HC_TRANSFER_CONTROL {
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ULONG Control; // use HcTDControl flags below
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struct _HC_GENERAL_TD_CONTROL{
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ULONG :16; // available for s/w use in GTD
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ULONG Isochronous:1; // should be 0 for GTD, s/w flag
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ULONG :1; // available for s/w use
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ULONG ShortXferOk:1; // if set don't report error on short transfer
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ULONG Direction:2; // use HcTDDirection flags below
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ULONG IntDelay:3; // use HcTDIntDelay flags below
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ULONG Toggle:2; // use HcTDToggle flags below
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ULONG ErrorCount:2;
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ULONG ConditionCode:4; // use HcCC flags below
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} Asy;
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struct _HC_ISOCHRONOUS_TD_CONTROL{
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ULONG StartingFrame:16;
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ULONG Isochronous:1;// should be 1 for ITD, s/w flag
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ULONG :1; // available for s/w use
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ULONG :3; // available for s/w use in ITD
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ULONG IntDelay:3; // IntDelay
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ULONG FrameCount:3; // one less than number of frames described in ITD
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ULONG :1; // available for s/w use in ITD
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ULONG :4; // ConditionCode
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} Iso;
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} HC_TRANSFER_CONTROL, *PHC_TRANSFER_CONTROL;
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//
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// Definitions for HC_TRANSFER_CONTROL.Control
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//
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#define HcTDControl_STARTING_FRAME 0x0000FFFF // mask for starting frame (Isochronous)
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#define HcTDControl_ISOCHRONOUS 0x00010000 // 1 for Isoch TD, 0 for General TD
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#define HcTDControl_SHORT_XFER_OK 0x00040000 // 0 if short transfers are errors
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#define HcTDControl_DIR_MASK 0x00180000 // Transfer direction field
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#define HcTDControl_DIR_SETUP 0x00000000 // direction is setup packet from host to device
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#define HcTDControl_DIR_OUT 0x00080000 // direction is from host to device
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#define HcTDControl_DIR_IN 0x00100000 // direction is from device to host
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#define HcTDControl_INT_DELAY_MASK 0x00E00000 // Interrupt Delay field
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#define HcTDControl_INT_DELAY_0_MS 0x00000000 // Interrupt at end of frame TD is completed
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#define HcTDControl_INT_DELAY_1_MS 0x00200000 // Interrupt no later than end of 1st frame after TD is completed
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#define HcTDControl_INT_DELAY_2_MS 0x00400000 // Interrupt no later than end of 2nd frame after TD is completed
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#define HcTDControl_INT_DELAY_3_MS 0x00600000 // Interrupt no later than end of 3rd frame after TD is completed
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#define HcTDControl_INT_DELAY_4_MS 0x00800000 // Interrupt no later than end of 4th frame after TD is completed
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#define HcTDControl_INT_DELAY_5_MS 0x00A00000 // Interrupt no later than end of 5th frame after TD is completed
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#define HcTDControl_INT_DELAY_6_MS 0x00C00000 // Interrupt no later than end of 6th frame after TD is completed
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#ifdef NSC
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#define HcTDControl_INT_DELAY_NO_INT 0x00C00000 // Almost infinity but not yet quite.
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#elif DISABLE_INT_DELAY_NO_INT
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#define HcTDControl_INT_DELAY_NO_INT 0x00000000 // Interrupt at the completion of all packets.
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#else
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#define HcTDControl_INT_DELAY_NO_INT 0x00E00000 // Do not cause an interrupt for normal completion of this TD
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#endif
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#define HcTDControl_FRAME_COUNT_MASK 0x07000000 // mask for FrameCount field (Isochronous)
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#define HcTDControl_FRAME_COUNT_SHIFT 24 // shift count for FrameCount (Isochronous)
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#define HcTDControl_FRAME_COUNT_MAX 8 // Max number of for frame count per TD
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#define HcTDControl_TOGGLE_MASK 0x03000000 // mask for Toggle control field
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#define HcTDControl_TOGGLE_FROM_ED 0x00000000 // get data toggle from CARRY field of ED
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#define HcTDControl_TOGGLE_DATA0 0x02000000 // use DATA0 for data PID
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#define HcTDControl_TOGGLE_DATA1 0x03000000 // use DATA1 for data PID
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#define HcTDControl_ERROR_COUNT 0x0C000000 // mask for Error Count field
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#define HcTDControl_CONDITION_CODE_MASK 0xF0000000 // mask for ConditionCode field
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#define HcTDControl_CONDITION_CODE_SHIFT 28 // shift count for ConditionCode
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//
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// Definitions for HC_TRANSFER_CONTROL.Direction
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//
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#define HcTDDirection_Setup 0 // setup packet from host to device
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#define HcTDDirection_Out 1 // direction from host to device
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#define HcTDDirection_In 2 // direction from device to host
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|
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|
//
|
|
// Definitions for Hc_TRANSFER_CONTROL.IntDelay
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|
//
|
|
#define HcTDIntDelay_0ms 0 // interrupt at end of frame TD is completed
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#define HcTDIntDelay_1ms 1 // Interrupt no later than end of 1st frame after TD is completed
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#define HcTDIntDelay_2ms 2 // Interrupt no later than end of 2nd frame after TD is completed
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#define HcTDIntDelay_3ms 3 // Interrupt no later than end of 3rd frame after TD is completed
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#define HcTDIntDelay_4ms 4 // Interrupt no later than end of 4th frame after TD is completed
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#define HcTDIntDelay_5ms 5 // Interrupt no later than end of 5th frame after TD is completed
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|
#define HcTDIntDelay_6ms 6 // Interrupt no later than end of 6th frame after TD is completed
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|
#define HcTDIntDelay_NoInterrupt 7 // do not generate interrupt for normal completion of this TD
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|
|
|
//
|
|
// Definitions for HC_TRANSFER_CONTROL.Toggle
|
|
//
|
|
#define HcTDToggle_FromEd 0 // get toggle for Endpoint Descriptor toggle CARRY bit
|
|
#define HcTDToggle_Data0 2 // use Data0 PID
|
|
#define HcTDToggle_Data1 3 // use Data1 PID
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|
|
|
//
|
|
// Definitions for HC_TRANSFER_CONTROL.ConditionCode and HC_OFFSET_PSW.ConditionCode
|
|
//
|
|
#define HcCC_NoError 0x0UL
|
|
#define HcCC_CRC 0x1UL
|
|
#define HcCC_BitStuffing 0x2UL
|
|
#define HcCC_DataToggleMismatch 0x3UL
|
|
#define HcCC_Stall 0x4UL
|
|
#define HcCC_DeviceNotResponding 0x5UL
|
|
#define HcCC_PIDCheckFailure 0x6UL
|
|
#define HcCC_UnexpectedPID 0x7UL
|
|
#define HcCC_DataOverrun 0x8UL
|
|
#define HcCC_DataUnderrun 0x9UL
|
|
// 0xA // reserved
|
|
// 0xB // reserved
|
|
#define HcCC_BufferOverrun 0xCUL
|
|
#define HcCC_BufferUnderrun 0xDUL
|
|
#define HcCC_NotAccessed 0xEUL
|
|
// 0xF // this also means NotAccessed
|
|
|
|
//
|
|
// Host Controller Transfer Descriptor, refer to Section 4.3, Transfer Descriptors
|
|
//
|
|
typedef struct _HW_TRANSFER_DESCRIPTOR {
|
|
HC_TRANSFER_CONTROL; // dword 0
|
|
ULONG CBP; // phys ptr to start of buffer
|
|
ULONG NextTD; // phys ptr to HC_TRANSFER_DESCRIPTOR
|
|
ULONG BE; // phys ptr to end of buffer (last byte)
|
|
HC_OFFSET_PSW Packet[8]; // isoch & Control packets
|
|
} HW_TRANSFER_DESCRIPTOR, *PHW_TRANSFER_DESCRIPTOR;
|
|
|
|
C_ASSERT((sizeof(HW_TRANSFER_DESCRIPTOR) == 32));
|
|
|
|
#include <POPPACK.H>
|
|
|
|
#endif /* OPENHCI_H */
|