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151 lines
4.3 KiB
151 lines
4.3 KiB
/* *************************************************************************
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** INTEL Corporation Proprietary Information
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**
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** This listing is supplied under the terms of a license
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** agreement with INTEL Corporation and may not be copied
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** nor disclosed except in accordance with the terms of
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** that agreement.
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**
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** Copyright (c) 1995, 1996 Intel Corporation.
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** All Rights Reserved.
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**
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** *************************************************************************
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*/
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// $Author: AGUPTA2 $
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// $Date: 08 Mar 1996 16:46:34 $
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// $Archive: S:\h26x\src\dec\dxblkcpy.cpv $
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// $Header: S:\h26x\src\dec\dxblkcpy.cpv 1.4 08 Mar 1996 16:46:34 AGUPTA2 $
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// $Log: S:\h26x\src\dec\dxblkcpy.cpv $
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//
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// Rev 1.4 08 Mar 1996 16:46:34 AGUPTA2
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// Rewritten to reduce code size by avoiding 32-bit displacements. Added
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// pragma code_seg. May need to optimize for misaligned case.
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//
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//
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// Rev 1.3 31 Jan 1996 13:15:14 RMCKENZX
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// Rewrote file to avoid bank conflicts. Fully unrolled the loop.
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// Module now really will execute in 52 cycles if the cache is hot.
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//
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// Rev 1.2 22 Dec 1995 13:51:06 KMILLS
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// added new copyright notice
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//
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// Rev 1.1 25 Sep 1995 09:03:22 CZHU
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// Added comments on cycle counts
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//
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// Rev 1.0 11 Sep 1995 16:52:26 CZHU
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// Initial revision.
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//
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//
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// Note:
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// - BlockCopy reads and writes in DWORDS.
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// - The __fastcall convention is used.
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// - Code re-written to minimize code size.
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// - We assume the output frame to NOT be in cache.
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// - The constants PITCH and U32 are defined internally (no include files used).
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//
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// Registers used:
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// eax accumulator
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// ebx accumulator
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// ecx destination address
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// edx source address
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// ebp PITCH
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//
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// Pentium cycle count (input cache hot, output cache cold):
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// 33 + 8*(cache miss time) input aligned
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// 81 + 8*(cache miss time) input mis-aligned
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//
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//------------------------------------------------------------------------------
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#include "precomp.h"
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#define U32 unsigned long
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// Already defined in precomp.h
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#define DXPITCH 384
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#pragma code_seg("IACODE2")
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/*
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* Notes:
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* The parameter uDstBlock is in ecx and uSrcBlock is in edx.
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*/
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__declspec(naked)
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void __fastcall BlockCopy (U32 uDstBlock, U32 uSrcBlock)
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{
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__asm {
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push edi
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push ebx
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push ebp
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mov ebp, DXPITCH
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// row 0
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mov eax, [edx]
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mov ebx, [edx+4]
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add edx, ebp
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mov edi, [ecx] // heat output cache
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mov [ecx], eax
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mov [ecx+4], ebx
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// row 1
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add ecx, ebp
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mov eax, [edx]
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mov ebx, [edx+4]
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add edx, ebp
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mov edi, [ecx] // heat output cache
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mov [ecx], eax
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mov [ecx+4], ebx
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add ecx, ebp
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// row 2
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mov eax, [edx]
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mov ebx, [edx+4]
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add edx, ebp
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mov edi, [ecx] // heat output cache
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mov [ecx], eax
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mov [ecx+4], ebx
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// row 3
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add ecx, ebp
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mov eax, [edx]
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mov ebx, [edx+4]
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add edx, ebp
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mov edi, [ecx] // heat output cache
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mov [ecx], eax
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mov [ecx+4], ebx
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add ecx, ebp
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// row 4
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mov eax, [edx]
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mov ebx, [edx+4]
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add edx, ebp
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mov edi, [ecx] // heat output cache
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mov [ecx], eax
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mov [ecx+4], ebx
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// row 5
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add ecx, ebp
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mov eax, [edx]
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mov ebx, [edx+4]
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add edx, ebp
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mov edi, [ecx] // heat output cache
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mov [ecx], eax
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mov [ecx+4], ebx
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add ecx, ebp
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// row 6
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mov eax, [edx]
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mov ebx, [edx+4]
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add edx, ebp
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mov edi, [ecx] // heat output cache
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mov [ecx], eax
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mov [ecx+4], ebx
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// row 7
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add ecx, ebp
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pop ebp
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mov eax, [edx]
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mov ebx, [edx+4]
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mov edi, [ecx] // heat output cache
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mov [ecx], eax
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mov [ecx+4], ebx
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pop ebx
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pop edi
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ret
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} // end of asm
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}
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#pragma code_seg()
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