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176 lines
5.0 KiB
176 lines
5.0 KiB
//
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// AMDAGP8X.sys is a driver, make sure we get the appropriate linkage.
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//
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/*
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******************************************************************************
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* Archive File : $Archive: /Drivers/OS/Hammer/AGP/XP/amdagp/Amdagp8x.h $
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*
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* $History: Amdagp8x.h $
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*
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*
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******************************************************************************
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*/
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//#define _NTDRIVER_
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#include <agp.h>
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//
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// Define the location of the GART aperture control registers
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//
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#define AGP_GART_BUS_ID 0
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#define VENDOR_AMD 0x1022
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#define DEVICE_LOKAR 0x7454
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#define DEVICE_HAMMER 0x1103
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#define VENDORID_MASK 0x0000FFFF
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#define DEVICEID_MASK 0xFFFF0000
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#define CHIPSET_ID_OFFSET 0x00 // Vendor/Device ID Register
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#define STATUS_CMD_OFFSET 0x04 // Status/Command Register
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#define CLASS_REV_OFFSET 0x08 // Class Code/Revision ID Register
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#define APBASE_OFFSET 0x10 // Aperture Base Address
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#define AMD_AGP_CONTROL_OFFSET 0xB0
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#define AMD_APERTURE_SIZE_OFFSET 0xB4
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#define AMD_GART_POINTER_LOW_OFFSET 0xB8
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#define AMD_GART_POINTER_HIGH_OFFSET 0xBC
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#define CAPPTR_OFFSET 0x34
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#define AGP_STATUS_OFFSET 0x04
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#define AGP_COMMAND_OFFSET 0x08
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#define AGP_SIZE_OFFSET 0x0C
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#define PAGE_VALID_BIT 1
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#define CACHE_INVALIDATE_BIT 1
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#define PTE_ERROR_BIT 2
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#define GART_ENABLE_BIT 1
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#define APBASE_64BIT_MASK 0x04
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#define APBASE_ADDRESS_MASK 0xFE000000
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#define APH_SIZE_MASK 0x0E
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#define APH_SIZE_32MB 0x00
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#define APH_SIZE_64MB 0x02
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#define APH_SIZE_128MB 0x04
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#define APH_SIZE_256MB 0x06
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#define APH_SIZE_512MB 0x08
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#define APH_SIZE_1024MB 0x0A
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#define APH_SIZE_2048MB 0x0C
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#define APL_SIZE_MASK 0x0738
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#define APL_SIZE_32MB 0x0738
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#define APL_SIZE_64MB 0x0730
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#define APL_SIZE_128MB 0x0720
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#define APL_SIZE_256MB 0x0700
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#define APL_SIZE_512MB 0x0600
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#define APL_SIZE_1024MB 0x0400
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#define APL_SIZE_2048MB 0x0000
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#define AP_SIZE_COUNT 7
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#define AP_MIN_SIZE (32 * 1024 * 1024)
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#define AP_MAX_SIZE (1024 * 1024 * 1024)
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// Hammer Configuration Registers
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#define GART_APSIZE_OFFSET 0x90
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#define GART_APBASE_OFFSET 0x94
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#define GART_TABLE_OFFSET 0x98
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#define GART_CONTROL_OFFSET 0x9C
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#define GART_APBASE_SHIFT 25
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//
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// Define macros to read/write PCI configuration space
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//
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#define ReadAMDConfig(_slot_,_buf_,_offset_,_size_) \
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{ \
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ULONG _len_; \
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_len_ = HalGetBusDataByOffset(PCIConfiguration, \
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AGP_GART_BUS_ID, \
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(_slot_), \
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(_buf_), \
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(_offset_), \
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(_size_)); \
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}
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#define WriteAMDConfig(_slot_,_buf_,_offset_,_size_) \
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{ \
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ULONG _len_; \
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_len_ = HalSetBusDataByOffset(PCIConfiguration, \
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AGP_GART_BUS_ID, \
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(_slot_), \
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(_buf_), \
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(_offset_), \
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(_size_)); \
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}
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//
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// Define the GART table entry.
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//
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typedef struct _GART_ENTRY_HW {
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ULONG Valid : 1;
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ULONG Coherent : 1;
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ULONG Reserved : 2;
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ULONG PageHigh : 8;
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ULONG PageLow : 20;
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} GART_ENTRY_HW, *PGART_ENTRY_HW;
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//
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// GART Entry states are defined so that all software-only states
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// have the Valid bit clear.
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//
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#define GART_ENTRY_VALID 1 // 001
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#define GART_ENTRY_FREE 0 // 000
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#define GART_ENTRY_COHERENT 2 // 010
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#define GART_ENTRY_WC 4 // 00100
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#define GART_ENTRY_UC 8 // 01000
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#define GART_ENTRY_CC 16 // 10000
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#define GART_ENTRY_RESERVED_WC GART_ENTRY_WC
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#define GART_ENTRY_RESERVED_UC GART_ENTRY_UC
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#define GART_ENTRY_RESERVED_CC GART_ENTRY_CC
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#define GART_ENTRY_VALID_WC (GART_ENTRY_VALID)
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#define GART_ENTRY_VALID_UC (GART_ENTRY_VALID)
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#define GART_ENTRY_VALID_CC (GART_ENTRY_VALID | GART_ENTRY_COHERENT)
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typedef struct _GART_ENTRY_SW {
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ULONG State : 5;
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ULONG Reserved : 27;
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} GART_ENTRY_SW, *PGART_ENTRY_SW;
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typedef struct _GART_PTE {
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union {
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GART_ENTRY_HW Hard;
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ULONG AsUlong;
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GART_ENTRY_SW Soft;
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};
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} GART_PTE, *PGART_PTE;
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#define TABLE_ENTRY_SIZE sizeof(GART_PTE)
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#define NUM_PAGE_ENTRIES_PER_PAGE (PAGE_SIZE/TABLE_ENTRY_SIZE)
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//
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// Define the AMD-specific extension
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//
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typedef struct _AGP_AMD_EXTENSION {
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PHYSICAL_ADDRESS ApertureStart;
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ULONG ApertureLength;
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PGART_PTE Gart;
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ULONG GartLength;
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PHYSICAL_ADDRESS GartPhysical;
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ULONGLONG SpecialTarget;
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} AGP_AMD_EXTENSION, *PAGP_AMD_EXTENSION;
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extern void DisplayStatus(UCHAR);
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