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111 lines
2.5 KiB
111 lines
2.5 KiB
/**
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*** Copyright (C) 1985-1998 Intel Corporation.
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***
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*** The information and source code contained herein is the exclusive property
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*** of Intel Corporation and may not be disclosed, examined, or
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*** reproduced in whole or in part without explicit written authorization from
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*** the Company.
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***
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*** static char sccs_id[] = "@(#)cpu_disp.c 1.9 06/06/00 14:08:14";
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***
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**/
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#include <sect_attribs.h>
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#include <cruntime.h>
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#include <internal.h>
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#undef leave
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#define CPU_HAS_SSE2(x) (((x) & (1 << 26)) != 0)
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#ifdef _MSC_VER
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int __sse2_available_init(void);
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#pragma data_seg(".CRT$XIC")
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_CRTALLOC(".CRT$XIC") static _PIFV pinit = __sse2_available_init;
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#pragma data_seg()
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#endif /* _MSC_VER */
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int __sse2_available;
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int __use_sse2_mathfcns;
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static int
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has_osfxsr_set()
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{
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int ret = 0;
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__try {
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__asm movapd xmm0, xmm1;
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ret = 1;
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}
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__except(1) {
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}
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return ret;
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}
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__declspec(naked) int __sse2_available_init()
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{
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int cpu_feature;
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__asm
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{
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push ebp
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mov ebp, esp
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sub esp, __LOCAL_SIZE
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push ebx
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push edi
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push esi
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pushfd /* if we can't write to bit 21 */
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pop eax /* of the eflags, then we don't */
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mov ecx, eax /* have a cpuid instruction. */
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xor eax, 0x200000
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push eax
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popfd
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pushfd
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pop edx
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sub edx, ecx
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je DONE /* CPUID not available */
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push ecx /* restore eflags */
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popfd
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mov eax, 1
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cpuid
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DONE :
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mov cpu_feature, edx
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}
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__use_sse2_mathfcns = __sse2_available = 0;
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if (CPU_HAS_SSE2(cpu_feature)) {
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if (has_osfxsr_set()) {
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__sse2_available = 1;
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#if !defined(_SYSCRT)
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/*
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* The VC++ CRT will automatically enable the SSE2 implementations
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* when possible. The system CRT will not, so existing apps don't
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* start seeing different results on a Pentium4.
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*/
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__use_sse2_mathfcns = 1;
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#endif
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}
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}
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__asm
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{
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xor eax, eax
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pop esi
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pop edi
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pop ebx
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leave
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ret
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}
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}
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_CRTIMP int __cdecl _set_SSE2_enable(int flag)
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{
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return __use_sse2_mathfcns = flag ? __sse2_available : 0;
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}
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