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410 lines
17 KiB
410 lines
17 KiB
#ifndef IA64PROF_H_INCLUDED
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#define IA64PROF_H_INCLUDED
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/*++
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Copyright (c) 1989-2000 Microsoft Corporation
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Component Name:
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IA64 Profiling
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Module Name:
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ia64prof.h
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Abstract:
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This header file presents the IA64 specific profiling definitions
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Author:
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David N. Cutler (davec) 5-Mar-1989
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Environment:
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ToBeSpecified
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Revision History:
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3/15/2000 Thierry Fevrier ([email protected]):
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Initial version
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--*/
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//
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// Warning: The definition of HALPROFILE_PCR should match the HalReserved[] type definition
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// and the PROCESSOR_PROFILING_INDEX based indexes.
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//
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//
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// IA64 Generic - Number of PMCs / PMDs pairs.
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//
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#define PROCESSOR_IA64_PERFCOUNTERS_PAIRS 4
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typedef struct _HALPROFILE_PCR {
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ULONGLONG ProfilingRunning;
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ULONGLONG ProfilingInterruptHandler;
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ULONGLONG ProfilingInterrupts; // XXTF - DEBUG
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ULONGLONG ProfilingInterruptsWithoutProfiling; // XXTF - DEBUG
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ULONGLONG ProfileSource [ PROCESSOR_IA64_PERFCOUNTERS_PAIRS ];
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ULONGLONG PerfCnfg [ PROCESSOR_IA64_PERFCOUNTERS_PAIRS ];
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ULONGLONG PerfData [ PROCESSOR_IA64_PERFCOUNTERS_PAIRS ];
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ULONGLONG PerfCnfgReload[ PROCESSOR_IA64_PERFCOUNTERS_PAIRS ];
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ULONGLONG PerfDataReload[ PROCESSOR_IA64_PERFCOUNTERS_PAIRS ];
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} HALPROFILE_PCR, *PHALPROFILE_PCR;
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#define HALPROFILE_PCR ( (PHALPROFILE_PCR)(&(PCR->HalReserved[PROCESSOR_PROFILING_INDEX])) )
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//
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// Define space in the HAL-reserved part of the PCR structure for each
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// performance counter's interval count
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//
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// Note that i64prfs.s depends on these positions in the PCR.
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//
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//
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// Per-Processor Profiling Status
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//
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#define HalpProfilingRunning HALPROFILE_PCR->ProfilingRunning
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//
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// Per-Processor registered Profiling Interrupt Handler
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//
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#define HalpProfilingInterruptHandler HALPROFILE_PCR->ProfilingInterruptHandler
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//
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// Per-Processor Profiling Interrupts Status
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//
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#define HalpProfilingInterrupts HALPROFILE_PCR->ProfilingInterrupts
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#define HalpProfilingInterruptsWithoutProfiling HALPROFILE_PCR->ProfilingInterruptsWithoutProfiling
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//
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// Define the currently selected profile source for each counter
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//
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// FIXFIX - Merced Specific.
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#define HalpProfileSource4 (KPROFILE_SOURCE)HALPROFILE_PCR->ProfileSource[0] // PMC4
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#define HalpProfileSource5 (KPROFILE_SOURCE)HALPROFILE_PCR->ProfileSource[1] // PMC5
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#define HalpProfileSource6 (KPROFILE_SOURCE)HALPROFILE_PCR->ProfileSource[2] // PMC6
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#define HalpProfileSource7 (KPROFILE_SOURCE)HALPROFILE_PCR->ProfileSource[3] // PMC7
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__inline
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VOID
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HalpSetProfileSource(
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ULONG Pmcd,
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KPROFILE_SOURCE ProfileSource,
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ULONGLONG ProfileSourceConfig
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)
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{
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ULONG pmcdIdx;
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ASSERTMSG("HAL!HalpSetProfileSource: invalid Pmcd!\n", ((Pmcd >= 4) && ((Pmcd <= 7))));
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pmcdIdx = Pmcd - PROCESSOR_IA64_PERFCOUNTERS_PAIRS;
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(KPROFILE_SOURCE)HALPROFILE_PCR->ProfileSource[pmcdIdx] = ProfileSource;
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(KPROFILE_SOURCE)HALPROFILE_PCR->PerfCnfg[pmcdIdx] = ProfileSourceConfig;
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} // HalpSetProfileSource()
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__inline
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KPROFILE_SOURCE
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HalpGetProfileSource(
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ULONG Pmcd
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)
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{
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ULONG pmcdIdx;
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ASSERTMSG("HAL!HalpGetProfileSource: invalid Pmcd!\n", ((Pmcd >= 4) && ((Pmcd <= 7))));
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pmcdIdx = Pmcd - PROCESSOR_IA64_PERFCOUNTERS_PAIRS;
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return (KPROFILE_SOURCE)HALPROFILE_PCR->ProfileSource[pmcdIdx];
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} // HalpGetProfileSource()
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#define HalpProfileCnfg4 (ULONGLONG)HALPROFILE_PCR->PerfCnfg[0]
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#define HalpProfileCnfg5 (ULONGLONG)HALPROFILE_PCR->PerfCnfg[1]
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#define HalpProfileCnfg6 (ULONGLONG)HALPROFILE_PCR->PerfCnfg[2]
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#define HalpProfileCnfg7 (ULONGLONG)HALPROFILE_PCR->PerfCnfg[3]
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#define PCRProfileData4 ( (PULONGLONG) (&(HALPROFILE_PCR->PerfData[0])) )
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#define PCRProfileData5 ( (PULONGLONG) (&(HALPROFILE_PCR->PerfData[1])) )
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#define PCRProfileData6 ( (PULONGLONG) (&(HALPROFILE_PCR->PerfData[2])) )
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#define PCRProfileData7 ( (PULONGLONG) (&(HALPROFILE_PCR->PerfData[3])) )
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#define PCRProfileCnfg4Reload ( (PULONGLONG) (&(HALPROFILE_PCR->PerfCnfgReload[0])) )
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#define PCRProfileCnfg5Reload ( (PULONGLONG) (&(HALPROFILE_PCR->PerfCnfgReload[1])) )
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#define PCRProfileCnfg6Reload ( (PULONGLONG) (&(HALPROFILE_PCR->PerfCnfgReload[2])) )
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#define PCRProfileCnfg7Reload ( (PULONGLONG) (&(HALPROFILE_PCR->PerfCnfgReload[3])) )
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#define PCRProfileData4Reload ( (PULONGLONG) (&(HALPROFILE_PCR->PerfCnfgReload[0])) )
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#define PCRProfileData5Reload ( (PULONGLONG) (&(HALPROFILE_PCR->PerfDataReload[1])) )
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#define PCRProfileData6Reload ( (PULONGLONG) (&(HALPROFILE_PCR->PerfDataReload[2])) )
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#define PCRProfileData7Reload ( (PULONGLONG) (&(HALPROFILE_PCR->PerfDataReload[3])) )
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//
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// IA64 Monitored Events have
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//
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typedef enum _PMCD_SOURCE_MASK {
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// FIXFIX - 04/2002: First implementation uses defines.
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// : We should use ULONG union and bit fields for next version.
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PMCD_MASK_4 = 0x1,
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PMCD_MASK_5 = 0x2,
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PMCD_MASK_6 = 0x4,
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PMCD_MASK_7 = 0x8,
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PMCD_MASK_45 = (PMCD_MASK_4 | PMCD_MASK_5),
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PMCD_MASK_67 = (PMCD_MASK_6 | PMCD_MASK_7),
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PMCD_MASK_4567 = (PMCD_MASK_4 | PMCD_MASK_5 | PMCD_MASK_6 | PMCD_MASK_7),
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//
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// Source Sets definitions:
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//
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PMCD_MASK_SET = 0xffff0000,
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PMCD_MASK_SET_SHIFT = 0x10,
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PMCD_MASK_SET_PMCD = 0xff,
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PMCD_MASK_SET_PMCD_SHIFT = 0x10,
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PMCD_MASK_SET_PMCD_4 = (4 << PMCD_MASK_SET_PMCD_SHIFT),
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PMCD_MASK_SET_PMCD_5 = (5 << PMCD_MASK_SET_PMCD_SHIFT),
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PMCD_MASK_SET_PMCD_6 = (6 << PMCD_MASK_SET_PMCD_SHIFT),
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PMCD_MASK_SET_PMCD_7 = (7 << PMCD_MASK_SET_PMCD_SHIFT),
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PMCD_MASK_SET_DATA_SHIFT = 0x18,
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PMCD_MASK_SET_L0D_CACHE_0 = ((1 << PMCD_MASK_SET_DATA_SHIFT) | PMCD_MASK_SET_PMCD_5),
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PMCD_MASK_SET_L0D_CACHE_1 = ((2 << PMCD_MASK_SET_DATA_SHIFT) | PMCD_MASK_SET_PMCD_5),
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PMCD_MASK_SET_L0D_CACHE_2 = ((3 << PMCD_MASK_SET_DATA_SHIFT) | PMCD_MASK_SET_PMCD_5),
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PMCD_MASK_SET_L0D_CACHE_3 = ((4 << PMCD_MASK_SET_DATA_SHIFT) | PMCD_MASK_SET_PMCD_5),
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PMCD_MASK_SET_L0D_CACHE_4 = ((5 << PMCD_MASK_SET_DATA_SHIFT) | PMCD_MASK_SET_PMCD_5),
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PMCD_MASK_SET_L0D_CACHE_5 = ((6 << PMCD_MASK_SET_DATA_SHIFT) | PMCD_MASK_SET_PMCD_5),
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PMCD_MASK_SET_L1_CACHE_0 = ((7 << PMCD_MASK_SET_DATA_SHIFT) | PMCD_MASK_SET_PMCD_4),
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PMCD_MASK_SET_L1_CACHE_1 = ((8 << PMCD_MASK_SET_DATA_SHIFT) | PMCD_MASK_SET_PMCD_4),
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PMCD_MASK_SET_L1_CACHE_2 = ((9 << PMCD_MASK_SET_DATA_SHIFT) | PMCD_MASK_SET_PMCD_4),
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PMCD_MASK_SET_L1_CACHE_3 = ((10 << PMCD_MASK_SET_DATA_SHIFT) | PMCD_MASK_SET_PMCD_4),
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PMCD_MASK_SET_L1_CACHE_4 = ((11 << PMCD_MASK_SET_DATA_SHIFT) | PMCD_MASK_SET_PMCD_4),
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PMCD_MASK_SET_L1_CACHE_5 = ((12 << PMCD_MASK_SET_DATA_SHIFT) | PMCD_MASK_SET_PMCD_4),
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} PMCD_SOURCE_MASK;
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//
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// Define the mapping between possible profile sources and the
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// CPU-specific settings for the IA64 specific Event Counters.
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//
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typedef struct _HALP_PROFILE_MAPPING {
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BOOLEAN Supported;
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ULONG Event;
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ULONG ProfileSource;
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ULONG EventMask;
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ULONGLONG Interval;
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ULONGLONG IntervalDef; // Default or Desired Interval
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ULONGLONG IntervalMax; // Maximum Interval
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ULONGLONG IntervalMin; // Maximum Interval
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UCHAR PrivilegeLevel; // Current Privilege Level
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UCHAR PrivilegeLevelDef; // Default or Desired Privilege Level
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UCHAR OverflowInterrupt; // Current Overflow Interrupt state
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UCHAR OverflowInterruptDef; // Default or Desired Overflow Interrupt state
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UCHAR PrivilegeEnable; // Current Privilege Enable state
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UCHAR PrivilegeEnableDef; // Default or Desired Privilege Enable state
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UCHAR UnitMask; // Current Event specific Unit Mask
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UCHAR UnitMaskDef; // Default or Desired Event specific Unit Mask
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UCHAR Threshold; // Current Threshold
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UCHAR ThresholdDef; // Default or Desired Threshold for multi-occurence events.
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UCHAR InstructionSetMask; // Current Instruction Set Mask
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UCHAR InstructionSetMaskDef; // Default or Desired Instruction Set Mask
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} HALP_PROFILE_MAPPING, *PHALP_PROFILE_MAPPING;
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/////////////
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//
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// XXTF - ToBeDone - 02/08/2000.
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// The following section should provide the IA64 PMC APIs.
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// These should be considered as inline versions of the Halp*ProfileCounter*()
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// functions. This will allow user application to use standardized APIs to
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// program the performance monitor counters.
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//
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// HalpSetProfileCounterConfiguration()
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// HalpSetProfileCounterPrivilegeLevelMask()
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typedef enum _PMC_PLM_MASK {
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PMC_PLM_NONE = 0x0,
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PMC_PLM_0 = 0x1,
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PMC_PLM_1 = 0x2,
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PMC_PLM_2 = 0x4,
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PMC_PLM_3 = 0x8,
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PMC_PLM_ALL = (PMC_PLM_3|PMC_PLM_2|PMC_PLM_1|PMC_PLM_0)
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} PMC_PLM_MASK;
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// HalpSetProfileCounterConfiguration()
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typedef enum _PMC_NAMESPACE {
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PMC_DISABLE_OVERFLOW_INTERRUPT = 0x0,
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PMC_ENABLE_OVERFLOW_INTERRUPT = 0x1,
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PMC_DISABLE_PRIVILEGE_MONITOR = 0x0,
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PMC_ENABLE_PRIVILEGE_MONITOR = 0x1,
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PMC_UNIT_MASK_DEFAULT = 0x0,
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PMC_UNIT_MASK_RSEFILLS = 0x1,
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PMC_UNIT_MASK_INTANDFP_OPS = 0x3, // Ex: Specific umask for speculation events.
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PMC_UNIT_MASK_ALLTLBMISSES = 0x3, // Ex: Specific umask for tlb events.
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PMC_UNIT_MASK_L1TLBMISSES = 0x1, // Ex: Specific umask for tlb events.
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PMC_UNIT_MASK_L2TLBMISSES = 0x2, // Ex: Specific umask for tlb events.
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PMC_UNIT_MASK_IFETCH_BYPASS = 0x2, // Ex: Specific umask for inst. fetch cancels
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PMC_UNIT_MASK_IFETCH_STFILLWB = 0x6, // Ex: Specific umask for inst. fetch cancels
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PMC_UNIT_MASK_IFETCH_DATAREAD = 0x7, // Ex: Specific umask for inst. fetch cancels
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PMC_UNIT_MASK_L3ACCESS_ANY = 0x9, // Ex: Specific umask for L3 accesses cancels
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PMC_UNIT_MASK_L2_DATA_RDWR = 0x3, // Ex: Specific umask for L2 data references
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PMC_UNIT_MASK_L2_DATA_READ = 0x1, // Ex: Specific umask for L2 data references
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PMC_UNIT_MASK_L2_DATA_WRITE = 0x2, // Ex: Specific umask for L2 data references
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PMC_UNIT_MASK_L2_DATA_BYPASS_L1DTOL2A = 0x0, // Ex: Specific umask for L2 bypasses
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PMC_UNIT_MASK_L2_DATA_BYPASS_L1WTOL2I = 0x1, // Ex: Specific umask for L2 bypasses
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PMC_UNIT_MASK_L3_DATA_BYPASS_L1DTOL2A = 0x2, // Ex: Specific umask for L2 bypasses
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PMC_UNIT_MASK_L2_INST_BYPASS_L1DTOL2A = 0x4, // Ex: Specific umask for L2 bypasses
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PMC_UNIT_MASK_L2_INST_BYPASS_L1WTOL2I = 0x5, // Ex: Specific umask for L2 bypasses
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PMC_UNIT_MASK_L3_INST_BYPASS_L1DTOL2A = 0x6, // Ex: Specific umask for L2 bypasses
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PMC_UNIT_MASK_EVENT_SELECTED_LOSET = 0x0,
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PMC_UNIT_MASK_EVENT_SELECTED_HISET = 0x8,
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PMC_UNIT_MASK_L2_INT_LOADS = 0x8, // Ex: Specific umask for L2 operation types
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PMC_UNIT_MASK_L2_FP_LOADS = 0x9, // Ex: Specific umask for L2 operation types
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PMC_UNIT_MASK_L2_RMW_STORES = 0xa, // Ex: Specific umask for L2 operation types
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PMC_UNIT_MASK_L2_NON_RMW_STORES = 0xb, // Ex: Specific umask for L2 operation types
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PMC_UNIT_MASK_L2_NONLOADS_NONSTORES = 0xc, // Ex: Specific umask for L2 operation types
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PMC_UNIT_MASK_L3_READS_HITS = 0xd, // Ex: Specific umask for L3 reads
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PMC_UNIT_MASK_L3_READS_MISSES = 0xe, // Ex: Specific umask for L3 reads
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PMC_UNIT_MASK_L3_READS_IFETCH_REFERENCES = 0x7, // Ex: Specific umask for L3 reads
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PMC_UNIT_MASK_L3_READS_IFETCH_HITS = 0x5, // Ex: Specific umask for L3 reads
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PMC_UNIT_MASK_L3_READS_IFETCH_MISSES = 0x6, // Ex: Specific umask for L3 reads
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PMC_UNIT_MASK_L3_READS_DATA_HITS = 0x9, // Ex: Specific umask for L3 reads
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PMC_UNIT_MASK_L3_READS_DATA_MISSES = 0xa, // Ex: Specific umask for L3 reads
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PMC_UNIT_MASK_L3_READS_DATA_REFERENCES = 0xb, // Ex: Specific umask for L3 reads
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PMC_UNIT_MASK_L3_WRITES_HITS = 0xd, // Ex: Specific umask for L3 reads
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PMC_UNIT_MASK_L3_WRITES_MISSES = 0xe, // Ex: Specific umask for L3 reads
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PMC_UNIT_MASK_L3_WRITES_DATA_REFERENCES = 0x7, // Ex: Specific umask for L3 reads
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PMC_UNIT_MASK_L3_WRITES_DATA_HITS = 0x5, // Ex: Specific umask for L3 reads
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PMC_UNIT_MASK_L3_WRITES_DATA_MISSES = 0x6, // Ex: Specific umask for L3 reads
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PMC_UNIT_MASK_L3_WRITEBACK_HITS = 0x9, // Ex: Specific umask for L3 reads
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PMC_UNIT_MASK_L3_WRITEBACK_MISSES = 0xa, // Ex: Specific umask for L3 reads
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PMC_UNIT_MASK_L3_WRITEBACK_REFERENCES = 0xb, // Ex: Specific umask for L3 reads
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PMC_UNIT_MASK_BUS_ANY = 0x3, // Ex: Specific umask for BUS transactions
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PMC_UNIT_MASK_BUS_BYSELF = 0x2, // Ex: Specific umask for BUS transactions
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PMC_UNIT_MASK_BUS_NONPRI_AGENT = 0x1, // Ex: Specific umask for BUS transactions
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PMC_UNIT_MASK_BUS_MEMORY_ALL = 0xc, // Ex: Specific umask for BUS transactions
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PMC_UNIT_MASK_BUS_MEMORY_128BYTE = 0x4, // Ex: Specific umask for BUS transactions
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PMC_UNIT_MASK_BUS_MEMORY_LTH_128BYTE = 0x8, // Ex: Specific umask for BUS transactions
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PMC_UNIT_MASK_BUS_MEMORY_READS_ALL = 0xc, // Ex: Specific umask for BUS reads
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PMC_UNIT_MASK_BUS_MEMORY_BIL = 0x0, // Ex: Specific umask for BUS reads
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PMC_UNIT_MASK_BUS_MEMORY_BRL = 0x4, // Ex: Specific umask for BUS reads
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PMC_UNIT_MASK_BUS_MEMORY_BRIL = 0x8, // Ex: Specific umask for BUS reads
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PMC_UNIT_MASK_BUS_WB_ALL = 0xf, // Ex: Specific umask for BUS writebacks
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PMC_UNIT_MASK_BUS_WB_BYSELF = 0xe, // Ex: Specific umask for BUS writebacks
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PMC_UNIT_MASK_BUS_WB_NONPRI_AGENT = 0xd, // Ex: Specific umask for BUS writebacks
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PMC_UNIT_MASK_BUS_WB_BURST_ALL = 0x7, // Ex: Specific umask for BUS writebacks
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PMC_UNIT_MASK_BUS_WB_BURST_BYSELF = 0x6, // Ex: Specific umask for BUS writebacks
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PMC_UNIT_MASK_BUS_WB_BURST_NONPRI_AGENT = 0x5, // Ex: Specific umask for BUS writebacks
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PMC_UNIT_MASK_BUS_WB_ZEROBYTE_ALL = 0x7, // Ex: Specific umask for BUS writebacks
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PMC_UNIT_MASK_BUS_WB_ZEROBYTE_BYSELF = 0x6, // Ex: Specific umask for BUS writebacks
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PMC_UNIT_MASK_BUS_SNOOPS_ALL = 0xf, // Ex: Specific umask for BUS writebacks
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PMC_UNIT_MASK_BUS_SNOOPS_BYSELF = 0xe, // Ex: Specific umask for BUS writebacks
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PMC_UNIT_MASK_BUS_SNOOPS_NONPRI_AGENT = 0xd, // Ex: Specific umask for BUS writebacks
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PMC_UNIT_MASK_RSE_LOADS = 0x1, // Ex: Specific umask for RSE accesses
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PMC_UNIT_MASK_RSE_STORES = 0x2, // Ex: Specific umask for RSE accesses
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PMC_UNIT_MASK_RSE_LOAD_UNDERFLOWS = 0x4, // Ex: Specific umask for RSE accesses
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PMC_UNIT_MASK_ALL = 0xf,
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PMC_THRESHOLD_DEFAULT = 0x0,
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} PMC_NAMESPACE;
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// HalpSetProfileCounterConfiguration()
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// HalpSetProfileCounterInstructionSetMask()
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typedef enum _PMC_INSTRUCTION_SET_MASK {
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PMC_ISM_ALL = 0x0,
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PMC_ISM_IA64 = 0x1,
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PMC_ISM_IA32 = 0x2,
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PMC_ISM_NONE = 0x3
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} PMC_INSTRUCTION_SET_MASK;
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//
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////////////
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/////////////
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//
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// The following section provides IA64 PMU Events Masks definitions.
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// Microarchitectural definitions are defined in processor specific header file.
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//
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//
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// BranchPathPrediction - Branch Path Mask
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//
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// not really a mask, more a specification value.
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//
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typedef enum _BRANCH_PATH_RESULT_MASK {
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MISPRED_NT = 0x0,
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MISPRED_TAKEN = 0x1,
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OKPRED_NT = 0x2,
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OKPRED_TAKEN = 0x3,
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} BRANCH_PATH_RESULT_MASK;
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//
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// BranchTakenDetail - Slot Unit Mask.
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//
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typedef enum _BRANCH_TAKEN_DETAIL_SLOT_MASK {
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INSTRUCTION_SLOT0 = 0x1,
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INSTRUCTION_SLOT1 = 0x2,
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INSTRUCTION_SLOT2 = 0x4,
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NOT_TAKEN_BRANCH = 0x8
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} BRANCH_TAKEN_DETAIL_SLOT_MASK;
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//
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// BranchMultiWayDetail - Prediction OutCome Mask
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//
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// not really a mask, more a specification value.
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//
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typedef enum _BRANCH_DETAIL_PREDICTION_OUTCOME_MASK {
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ALL_PREDICTIONS = 0x0,
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CORRECT_PREDICTION = 0x1,
|
|
WRONG_PATH = 0x2,
|
|
WRONG_TARGET = 0x3
|
|
} BRANCH_MWAY_DETAIL_PREDICTION_OUTCOME_MASK;
|
|
|
|
//
|
|
// BranchMultiWayDetail - Branch Path Mask
|
|
//
|
|
// not really a mask, more a specification value.
|
|
//
|
|
|
|
typedef enum _BRANCH_MWAY_DETAIL_BRANCH_PATH_MASK {
|
|
NOT_TAKEN = 0x0,
|
|
TAKEN = 0x1,
|
|
ALL_PATH = 0x2
|
|
} BRANCH_MWAY_DETAIL_BRANCH_PATH_MASK;
|
|
|
|
//
|
|
// INST_TYPE for:
|
|
//
|
|
// FailedSpeculativeCheckLoads
|
|
// AdvancedCheckLoads
|
|
// FailedAdvancedCheckLoads
|
|
// ALATOverflows
|
|
//
|
|
|
|
typedef enum _SPECULATION_EVENT_MASK {
|
|
NONE = 0x0,
|
|
INTEGER = 0x1,
|
|
FP = 0x2,
|
|
ALL = 0x3
|
|
} SPECULATION_EVENT_MASK;
|
|
|
|
//
|
|
// CpuCycles - Executing Instruction Set
|
|
//
|
|
|
|
typedef enum _CPU_CYCLES_MODE_MASK {
|
|
ALL_MODES = 0x0,
|
|
IA64_MODE = 0x1,
|
|
IA32_MODE = 0x2
|
|
} CPU_CYCLES_MODE_MASK;
|
|
|
|
//
|
|
////////////
|
|
|
|
|
|
#endif /* IA64PROF_H_INCLUDED */
|