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996 lines
33 KiB
996 lines
33 KiB
//###########################################################################
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//**
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//** Copyright (C) 1996-98 Intel Corporation. All rights reserved.
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//**
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//** The information and source code contained herein is the exclusive
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//** property of Intel Corporation and may not be disclosed, examined
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//** or reproduced in whole or in part without explicit written authorization
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//** from the company.
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//**
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//###########################################################################
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//-----------------------------------------------------------------------------
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// Version control information follows.
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//
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// $Header: I:/DEVPVCS/OSMCA/osmchk.s_v 2.1 05 Mar 1999 12:59:42 smariset $
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// $Log: I:/DEVPVCS/OSMCA/osmchk.s_v $
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//
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// Rev 2.0 Dec 11 1998 11:42:18 khaw
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//Post FW 0.5 release sync-up
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//
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// Rev 1.4 12 Oct 1998 14:05:20 smariset
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//gp fix up work around
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//
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///////////////////////////////////////////////////////////////////////////////
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//
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// Module Name: OSMCHK.ASM - Merced OS Machine Check Abort Dispatcher
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//
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// Description:
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// Merced OS Machine Check Abort Stub to OSMCA "C" frame work. If
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// we find a TLB related error, we cannot switch to virtual mode in
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// the OS. All TLB related errors will need system reboot after
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// storing the errors to a persistence storage media (HD or Flash).
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//
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// HalpOsMcaDispatch - Main
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//
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// Target Platform: Merced
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//
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// Reuse: None
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//
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////////////////////////////////////////////////////////////////////////////M//
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#include "ksia64.h"
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#include "fwglobal.h"
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GLOBAL_FUNCTION(HalpOsMcaDispatch)
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GLOBAL_FUNCTION(HalpMCAEnable)
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GLOBAL_FUNCTION(HalpMcaHandler)
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GLOBAL_FUNCTION(HalpAcquireMcaSpinLock)
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GLOBAL_FUNCTION(HalpReleaseMcaSpinLock)
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.text
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//++
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// Name: HalpOsMcaDispatch()
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//
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// Routine Description:
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//
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// This is the OS call back handler, which is only exported to the SAL for call back
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// during MCA errors. This handler will dispatch to the appropriate MCA procedure.
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//
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// Sets up virtual->physical address translation
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// 0x00100000->0x00100000 in dtr1/itr1 for OS_MCA.
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//
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// Arguments:
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//
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// None
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//
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// On entry:
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//
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// This function is called:
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// - in physical mode for uncorrected or correctable MCA events,
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// - RSE enforced in lazy mode,
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// - Processor resources:
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// PSR.dt = 0, PSR.it = 0, PSR.rt = 0 - Physical mode.
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// PSR.ic = 0, PSR.i = 0 - Interrupt resources collection and interrupt disabled.
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// PSR.mc = 1 - Machine Checks masked
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// PSR.mfl = 0 - low fp disabled.
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// GR1 : OS_MCA Global Pointer (GP) registered by OS: OS's GP.
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// GR2-7: Unspecified.
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// GR8 : Physical address of the PAL_PROC entrypoint.
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// GR9 : Physical address of the SAL_PROC entrypoint.
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// GR10 : Physical address value of the SAL Global Pointer: SAL's GP.
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// GR11 : Rendezvous state information, defined as:
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// 0 - Rendezvous of other processors was not required by
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// PAL_CHECK and as such was not done.
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// 1 - All other processors in the system were successfully
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// rendezvous using MC_RENDEZVOUS interrupt.
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// 2 - All other processors in the system were successfully
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// rendezvous using a combination of MC_RENDEZVOUS
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// interrupt and INIT.
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// -1 - Rendezvous of other processors was required by PAL
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// but was unsuccessful.
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// GR12 : Return address to a location within SAL_CHECK.
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// GR17 : Pointer to processor minimum state saved memory location.
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// GR18 : Processor state as defined below:
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// D0-D5: Reserved
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// D6-D31: As defined in PAL EAS
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// D60-D63: As defined in PAL EAS
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// D32-D47: Size in bytes of processor dynamic state
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// D48-D59: Reserved.
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// GR19 : Return address to a location within PAL_CHECK.
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// BR0 : Unspecified.
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//
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// Return State:
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//
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// Note : The OS_MCA procedure may or may not return to SAL_CHECK
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// in the case of uncorrected machine checks.
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// If it returns to SAL, the runtime convention requires that
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// it sets appropriate values in the Min-State area pointed
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// to by GR12 for continuing execution at the interrupted
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// context or at a new context.
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// Furthermore, the OS_MCA procedure must restore the
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// processor state to the same state as on entry except as:
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// GR1-7 : Unspecified.
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// GR8 : Return status
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// 0 [= SAL_STATUS_SUCCESS] - Error has been corrected
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// by OS_MCA.
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// -1 - Error has not been corrected by OS_MCA and
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// SAL must warm boot the system.
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// -2 - Error has not been corrected by OS_MCA and
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// SAL must cold boot the system.
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// -3 - Error has not been corrected by OS_MCA and
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// SAL must halt the system.
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// GR9 : Physical address value for SAL's GP.
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// GR10 : Context flag
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// 0 - Return will be to the same context.
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// 1 - Return will be to a new context.
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// GR11-21: Unspecified.
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// GR22 : Pointer to a structure containing new values of registers
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// in the Min-State Save area.
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// OS_MCA must supply this parameter even if it does not
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// change the register values in the Min-State Save areas.
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// GR23-31: Unspecified.
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// BR0 : Unspecified.
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// PSR.mc : May be either 0 or 1.
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//--
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HalpOsMcaDispatch::
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// aliases for known registers:
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rPalProcEntryPoint = r8
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rSalProcEntryPoint = r9
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rSalGlobalPointer = r10
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rRendezVousResult = r11
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rSalReturnAddress = r12
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rProcMinStateSavePtr = r17
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rProcStateParameter = r18
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rPalCheckReturnAddress = r19
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rEventResources = t22
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rPcrPhysicalAddress = t6
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//
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// - Flag the processor as "InOsMca":
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// KiPcr.InOsMca = 1
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//
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// - Update KiPcr.McaPTOM to point to TopOfMemory,
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// Memory after Processor Minimum State Save area.
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//
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// - Update processor McaResource.SalToOsHandOff
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//
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// - Update local rPcrMcaStateDump before calling osMcaProcStateDump.
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//
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mov rEventResources = PcOsMcaResourcePtr
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movl t21 = KiPcr
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;;
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tpa rPcrPhysicalAddress = t21 // Calculate physical address of PCR
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mov t19 = SerSalToOsHandOff
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mov t1 = 0x1
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;;
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add t0 = rPcrPhysicalAddress, rEventResources
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sub t21 = rPcrPhysicalAddress, t21
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add t16 = TOM, rProcMinStateSavePtr
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;;
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ld8 rEventResources = [t0], PcInOsMca-PcOsMcaResourcePtr
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mov t18 = SerPTOM
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add t20 = 0x8, t19
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;;
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xchg1 t1 = [t0], t1
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add rEventResources = rEventResources, t21 // Calculate the physical address of the OsMcaResources
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add t21 = 0x10, t19
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;;
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add t18 = rEventResources, t18
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add t19 = rEventResources, t19
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add t20 = rEventResources, t20
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add t21 = rEventResources, t21
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;;
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ld8 t17 = [t16]
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st8 [t19] = rPalProcEntryPoint, 0x18
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add t0 = SerStateDumpPhysical, rEventResources
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;;
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st8 [t18] = t17
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st8 [t20] = rSalProcEntryPoint, 0x18
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st8 [t21] = rSalGlobalPointer, 0x18
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;;
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st8 [t19] = rRendezVousResult
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st8 [t20] = rSalReturnAddress
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st8 [t21] = rProcMinStateSavePtr
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ld8 t0 = [t0] // McaStateDump
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;;
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//
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// Save in preserved registers:
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// - pointer to processor minimum state save area,
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// - processor state parameter
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// - PAL_CHECK return address.
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// s0 [=r4] <- r17,
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// s1 [=r5] <- r18,
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// s2 [=r6] <- r19
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//
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SaveRs(rProcMinStateSavePtr, rProcStateParameter, rPalCheckReturnAddress)
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//
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// Save register resources in myStateDump[].
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//
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br.dpnt osMcaProcStateDump
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;;
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osMcaDoneDump::
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//
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// If we have a TLB error, we cannot enable translation
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//
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tbit.nz.unc pt0,p0=s1, 60 // PSP.tc=60
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(pt0) br.dpnt ResetNow
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;;
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//
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// Initialize current sp and ar.bsp and ar.bspstore
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//
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// KiPcr.McaStackFrame[0] = ar.rsc
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// KiPcr.McaStackFrame[1] = ar.pfs
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// KiPcr.McaStackFrame[2] = ar.ifs
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// KiPcr.McaStackFrame[3] = ar.bspstore
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// KiPcr.McaStackFrame[4] = ar.rnat
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// ar.bspstore = t0 [=KiPcr.McaBspStore]
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// KiPcr.McaStackFrame[5] = ar.bsp - KiPcr.McaBspStore
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// [BUGBUG ?? : should be ar.bsptore=KiPcr.McaStackFrame[3]]
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// sp = KiPcr.McaStack
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//
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movl t21 = KiPcr + PcOsMcaResourcePtr
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;;
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tpa t0 = t21 // Calculate physical address of PCR OsMcaResourcePtr
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mov t1 = SerStackFrame
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;;
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sub t16 = SerBackStore, t21
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sub t1 = t1, t21
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;;
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add t16 = t0, t16
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add t1 = t0, t1
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ld8 rEventResources = [t0], PcInitialBStore - PcOsMcaResourcePtr
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;;
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add t16 = rEventResources, t16 // Calculate physical address of the new BSP
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mov t21 = t0 // t21 now points to InitialBStore in the PCR
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;;
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add t1 = rEventResources, t1 // Calculate the physical address of the Stack Frame
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ld8 t0 = [t16], SerStack - SerBackStore
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;;
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SwIntCxt( t4, t1, t0 )
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;;
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st8 [t21] = t0, PcInitialStack - PcInitialBStore // Save the InitialBStore in the PCR
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ld8 t1 = [t16], SerBackStoreLimit - SerStack // Get inital MCA stack
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;;
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st8 [t21] = t1, PcBStoreLimit - PcInitialStack
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ld8 t0 = [t16], SerStackLimit - SerBackStoreLimit
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;;
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add t1 = -STACK_SCRATCH_AREA, t1
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st8 [t21] = t0, PcStackLimit - PcBStoreLimit // Save BStore limit
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ld8 t18 = [t16]
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;;
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mov sp = t1
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st8 [t21] = t18
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;;
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EnableTranslation::
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// let us switch to virtual mode
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//
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// Need to do a "rfi" in order set "it" and "ed" bits in the PSR.
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//
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// Make sure interrupts are disabled and that we are running on bank 1.
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//
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rsm 1 << PSR_I
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bsw.1
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;;
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mov ar.rsc = r0 // put RSE in lazy mode and use kernel mode stores.
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//
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// psr mask prepration, warning we will have a problem with PMI here
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//
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movl t0 = MASK_IA64(PSR_BN,1) | MASK_IA64(PSR_IC,1) |MASK_IA64(PSR_DA,1) | MASK_IA64(PSR_IT,1) | MASK_IA64(PSR_RT,1) | MASK_IA64(PSR_DT,1) | MASK_IA64(PSR_MC,1);;
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mov t1 = psr;;
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or t0 = t0, t1
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movl t1 = VirtualSwitchDone;;
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mov cr.iip = t1
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mov cr.ipsr = t0;;
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rfi
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;;
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VirtualSwitchDone::
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// done with enabling address translation
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// call our handler
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movl t0 = HalpMcaHandler;;
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mov b6 = t0;;
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br.call.dpnt b0=b6
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;;
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DisableTranslation::
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// psr mask prepration
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rsm MASK_IA64(PSR_IC,1);;
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movl t0 = MASK_IA64(PSR_DA,1) | MASK_IA64(PSR_IT,1) | MASK_IA64(PSR_RT,1) | MASK_IA64(PSR_DT,1);;
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movl t1=0xffffffffffffffff;;
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xor t0=t0,t1;;
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mov t1=psr;;
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and t0=t0,t1
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movl t1=BeginOsMcaRestore;;
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tpa t1=t1;;
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mov cr.iip=t1;;
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mov cr.ipsr = t0;;
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rfi
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;;
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BeginOsMcaRestore::
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// restore the original stack frame here
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mov t16 = SerStackFrame
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movl t21 = KiPcr + PcOsMcaResourcePtr
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;;
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tpa t1 = t21 // Calculate physical address of PCR OsMcaResourcePtr
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sub t16 = t16, t21
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sub t0 = SerStateDumpPhysical, t21
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;;
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ld8 rEventResources = [t1]
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add t16 = t1, t16
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add t0 = t1, t0
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;;
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add t16 = rEventResources, t16 // Calculate the physical address of the Stack Frame
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add t0 = rEventResources, t0 // Calculate the physical address of the State Dump pointer.
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;;
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ld8 t0 = [t0];
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movl t4 = PSRmcMask
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;;
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RtnIntCxt( t4, t1, t16 ) // switch from interrupt context -> RSC mgmt.
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;;
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//
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// let us restore all the registers from our PSI structure
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//
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mov t6 = gp
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br.dpnt osMcaProcStateRestore
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;;
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osMcaDoneRestore::
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// Pal requires DFH of 0
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rsm 1 << PSR_DFH
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;;
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rsm 1 << PSR_MFL // just restoring to original state only
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;;
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srlz.d
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;;
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//
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// - Restore processor state from OsToSalHandOff.
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//
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// - Branch back to SALE_CHECK.
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mov t1 = PcOsMcaResourcePtr
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movl t21 = KiPcr
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;;
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tpa rPcrPhysicalAddress = t21 // Calculate physical address of PCR
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;;
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add t0 = rPcrPhysicalAddress, t1
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sub t21 = SerOsToSalHandOff, t21
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;;
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ld8 t1 = [t0], PcInOsMca-PcOsMcaResourcePtr
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add t21 = t21, rPcrPhysicalAddress
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;;
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add t1 = t1, t21 // Calculate the physical address of the OsMcaResources->SalToOSHandOff
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;;
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add t16 = 0x8, t1
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add t17 = 0x10, t1
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;;
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ld8 r8 = [t1], 0x18 // result of error handling
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ld8 r9 = [t16], 0x18 // physical SAL's GP value
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ld8 r22 = [t17] // new Processor Min-State Save Ptr
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;;
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ld8 t1 = [t1] // SAL return address
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ld8 r10 = [t16] // New Context Switch Flag
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xchg1 t0 = [t0], r0 // KiPcr.InOsMca = 0
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;;
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mov b0 = t1
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br.dpnt b0 // Return to SALE_CHECK
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;;
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StayInPhysicalMode::
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// we have to reboot the machine, assume the log is already there in NVM
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// OS can read the log next time when it comes around. Or OS can try to
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// run in physical mode as well.
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ResetNow::
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// do EFI system reset here...
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// Go to BugCheck (in physical mode).
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// Out to Port 80: Fatal TLB error
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//
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Thyself::
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br Thyself // loop for safety
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;;
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//EndMain//////////////////////////////////////////////////////////////////////
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//++
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// Name:
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// osMcaProcStateDump()
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//
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// Stub Description:
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//
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// This stub dumps the processor state during MCHK to a data area
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//
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// On Entry:
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//
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// t0 = rPcrMcaStateDump.
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//
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// Return Value:
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//
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// None.
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//
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//--
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osMcaProcStateDump::
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// Get and save GR0-31 from Proc. Min. State Save Area to SAL PSI
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// TF: ASSERT( t0 == rPcrMcaStateDump )
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//save BRs
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add t2=Inc8,t0 // duplicate t0 in t2
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add t4=2*Inc8,t0 // duplicate t0 in t2
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mov t1=b0
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mov t3=b1
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mov t5=b2;;
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st8 [t0]=t1,3*Inc8
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st8 [t2]=t3,3*Inc8
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st8 [t4]=t5,3*Inc8;;
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mov t1=b3
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mov t3=b4
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mov t5=b5;;
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st8 [t0]=t1,3*Inc8
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st8 [t2]=t3,3*Inc8
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st8 [t4]=t5,3*Inc8;;
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mov t1=b6
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mov t3=b7;;
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st8 [t0]=t1,2*Inc8
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st8 [t2]=t3,2*Inc8;;
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cSaveCRs::
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// save CRs
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add t2=Inc8,t0 // duplicate t0 in t2
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add t4=2*Inc8,t0 // duplicate t0 in t2
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mov t1=cr0 // cr.dcr
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mov t3=cr1 // cr.itm
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mov t5=cr2;; // cr.iva
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st8 [t0]=t1,8*Inc8
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st8 [t2]=t3,3*Inc8
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st8 [t4]=t5,3*Inc8;; // 48 byte increments
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mov t1=cr8;; // cr.pta
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st8 [t0]=t1,Inc8*8;; // 64 byte increments
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// Reading interruption registers when PSR.ic=1 causes an illegal operation fault
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mov t1=psr;;
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tbit.nz.unc pt0,p0=t1,PSRic;; // PSI Valid Log bit pos. test
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(pt0) st8 [t0]=r0;;
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(pt0) adds t0 = 0x30*Inc8, t0 // cr16->cr64 increment
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(pt0) br.dpnt SkipIntrRegs
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;;
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add t2=Inc8,t0 // duplicate t0 in t2
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add t4=2*Inc8,t0 // duplicate t0 in t4
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mov t1=cr16 // cr.ipsr
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mov t3=cr17 // cr.isr
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mov t5=r0;; // cr.ida => cr18
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st8 [t0]=t1,3*Inc8
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|
st8 [t2]=t3,3*Inc8
|
|
st8 [t4]=t5,3*Inc8;;
|
|
|
|
mov t1=cr19 // cr.iip
|
|
mov t3=cr20 // cr.ifa
|
|
mov t5=cr21;; // cr.iitr
|
|
st8 [t0]=t1,3*Inc8
|
|
st8 [t2]=t3,3*Inc8
|
|
st8 [t4]=t5,3*Inc8;;
|
|
|
|
mov t1=cr22 // cr.iipa
|
|
mov t3=cr23 // cr.ifs
|
|
mov t5=cr24;; // cr.iim
|
|
st8 [t0]=t1,3*Inc8
|
|
st8 [t2]=t3,3*Inc8
|
|
st8 [t4]=t5,3*Inc8;;
|
|
|
|
mov t1=cr25;; // cr.iha
|
|
st8 [t0]=t1;;
|
|
adds t0 = 0x27*Inc8, t0;; // cr25->cr64 byte increment
|
|
|
|
SkipIntrRegs::
|
|
mov t1=cr64;; // cr.lid
|
|
st8 [t0]=t1,Inc8 //
|
|
|
|
mov t1=cr65;; // cr.ivr
|
|
st8 [t0]=t1,Inc8
|
|
|
|
mov t1=cr66;; // cr.tpr
|
|
st8 [t0]=t1,Inc8
|
|
|
|
mov t1=r0;; // cr.eoi
|
|
st8 [t0]=t1,Inc8 //
|
|
|
|
mov t1=r0;; // cr.irr0
|
|
st8 [t0]=t1,Inc8
|
|
|
|
mov t1=r0;; // cr.irr1
|
|
st8 [t0]=t1,Inc8
|
|
|
|
mov t1=r0;; // cr.irr2
|
|
st8 [t0]=t1,Inc8
|
|
|
|
mov t1=r0;; // cr.irr3
|
|
st8 [t0]=t1,Inc8
|
|
|
|
mov t1=r0;; // cr.itv
|
|
st8 [t0]=t1,Inc8
|
|
|
|
mov t1=r0;; // cr.pmv
|
|
st8 [t0]=t1,Inc8
|
|
|
|
mov t1=r0;; // cr.cmcv
|
|
st8 [t0]=t1,6*Inc8
|
|
|
|
mov t1=r0;; // cr.lrr0
|
|
st8 [t0]=t1,Inc8
|
|
|
|
mov t1=r0;; // cr.lrr1
|
|
st8 [t0]=t1;;
|
|
adds t0 = 0x2f*Inc8, t0;; // cr81->ar [128]
|
|
|
|
cSaveARs::
|
|
// save ARs
|
|
add t2=Inc8,t0 // duplicate t0 in t2
|
|
add t4=2*Inc8,t0 // duplicate t0 in t4
|
|
|
|
mov t1=ar0 // ar.kr0
|
|
mov t3=ar1 // ar.kr1
|
|
mov t5=ar2;; // ar.kr2
|
|
st8 [t0]=t1,3*Inc8
|
|
st8 [t2]=t3,3*Inc8
|
|
st8 [t4]=t5,3*Inc8;;
|
|
|
|
mov t1=ar3 // ar.kr3
|
|
mov t3=ar4 // ar.kr4
|
|
mov t5=ar5;; // ar.kr5
|
|
st8 [t0]=t1,3*Inc8
|
|
st8 [t2]=t3,3*Inc8
|
|
st8 [t4]=t5,13*Inc8;; // ar5->ar18
|
|
|
|
mov t1=ar6 // ar.kr6
|
|
mov t3=ar7;; // ar.kr7
|
|
st8 [t0]=t1,10*Inc8
|
|
st8 [t2]=t3,10*Inc8;;
|
|
|
|
mov t1=ar16 // ar.rsc
|
|
mov t3=ar17 // ar.bsp
|
|
mov t5=ar18;; // ar.bspstore
|
|
st8 [t0]=t1,3*Inc8
|
|
st8 [t2]=t3,3*Inc8
|
|
st8 [t4]=t5,3*Inc8;;
|
|
|
|
mov t1=ar19;; // ar.rnat
|
|
st8 [t0]=t1,Inc8*13 // increment by 13x8 bytes
|
|
|
|
mov t1=ar32;; // ar.ccv
|
|
st8 [t0]=t1,Inc8*4
|
|
|
|
mov t1=ar36;; // ar.unat
|
|
st8 [t0]=t1,Inc8*4
|
|
|
|
mov t1=ar40;; // ar.fpsr
|
|
st8 [t0]=t1,Inc8*4
|
|
|
|
mov t1=ar44;; // ar.itc
|
|
st8 [t0]=t1,160 // 160
|
|
|
|
mov t1=ar64;; // ar.pfs
|
|
st8 [t0]=t1,Inc8
|
|
|
|
mov t1=ar65;; // ar.lc
|
|
st8 [t0]=t1,Inc8
|
|
|
|
mov t1=ar66;; // ar.ec
|
|
st8 [t0]=t1
|
|
adds t0=Inc8*62,t0 //padding
|
|
|
|
// save RRs
|
|
mov ar.lc=0x08-1
|
|
movl t2=0x00;;
|
|
|
|
cStRR::
|
|
mov t1=rr[t2];;
|
|
st8 [t0]=t1,Inc8
|
|
add t2=1,t2
|
|
br.cloop.dpnt cStRR
|
|
;;
|
|
|
|
// align memory addresses to 16 bytes
|
|
and t1=0x0f,t0;;
|
|
cmp.ne.unc pt0,p0=t1,r0;;
|
|
(pt0) add t0=Inc8,t0
|
|
|
|
cSaveFRs::
|
|
// just save FP for MCA restore only, "C" code will trash f6-f15
|
|
// save ar.NaT
|
|
mov t3=ar.unat;; // ar.unat
|
|
|
|
stf.spill [t0]=f6,Inc16;;
|
|
stf.spill [t0]=f7,Inc16;;
|
|
stf.spill [t0]=f8,Inc16;;
|
|
stf.spill [t0]=f9,Inc16;;
|
|
stf.spill [t0]=f10,Inc16;;
|
|
stf.spill [t0]=f11,Inc16;;
|
|
stf.spill [t0]=f12,Inc16;;
|
|
stf.spill [t0]=f13,Inc16;;
|
|
stf.spill [t0]=f14,Inc16;;
|
|
stf.spill [t0]=f15,Inc16;;
|
|
|
|
mov t2=ar.unat;;
|
|
st8 [t0]=t2,Inc8 // save User NaT bits for r16-r31
|
|
mov ar.unat=t3 // restore original unat
|
|
|
|
br.dpnt osMcaDoneDump
|
|
;;
|
|
|
|
//EndStub//////////////////////////////////////////////////////////////////////
|
|
|
|
|
|
//++
|
|
// Name:
|
|
// osMcaProcStateRestore()
|
|
//
|
|
// Stub Description:
|
|
//
|
|
// This is a stub to restore the saved processor state during MCHK
|
|
//
|
|
// On Entry:
|
|
//
|
|
// t0 = rPcrMcaStateDump.
|
|
//
|
|
// Return Value:
|
|
//
|
|
// None.
|
|
//--
|
|
|
|
osMcaProcStateRestore::
|
|
|
|
// TF: ASSERT( t0 == rPcrMcaStateDump )
|
|
|
|
restore_BRs::
|
|
add t2=Inc8,t0 // duplicate t0 in t2
|
|
add t4=2*Inc8,t0;; // duplicate t0 in t2
|
|
|
|
ld8 t1=[t0],3*Inc8
|
|
ld8 t3=[t2],3*Inc8
|
|
ld8 t5=[t4],3*Inc8;;
|
|
mov b0=t1
|
|
mov b1=t3
|
|
mov b2=t5;;
|
|
|
|
ld8 t1=[t0],3*Inc8
|
|
ld8 t3=[t2],3*Inc8
|
|
ld8 t5=[t4],3*Inc8;;
|
|
mov b3=t1
|
|
mov b4=t3
|
|
mov b5=t5;;
|
|
|
|
ld8 t1=[t0],2*Inc8
|
|
ld8 t3=[t2],2*Inc8;;
|
|
mov b6=t1
|
|
mov b7=t3;;
|
|
|
|
restore_CRs::
|
|
add t2=Inc8,t0 // duplicate t0 in t2
|
|
add t4=2*Inc8,t0;; // duplicate t0 in t2
|
|
|
|
ld8 t1=[t0],8*Inc8
|
|
ld8 t3=[t2],3*Inc8
|
|
ld8 t5=[t4],3*Inc8;; // 48 byte increments
|
|
mov cr0=t1 // cr.dcr
|
|
mov cr1=t3 // cr.itm
|
|
mov cr2=t5;; // cr.iva
|
|
|
|
ld8 t1=[t0],8*Inc8;; // 64 byte increments
|
|
// mov cr8=t1 // cr.pta
|
|
|
|
|
|
// if PSR.ic=1, reading interruption registers causes an illegal operation fault
|
|
mov t1=psr;;
|
|
tbit.nz.unc pt0,p0=t1,PSRic;; // PSI Valid Log bit pos. test
|
|
(pt0) st8 [t0]=r0,9*8+160 // increment by 160 byte inc.
|
|
(pt0) br.dpnt rSkipIntrRegs
|
|
;;
|
|
|
|
add t2=Inc8,t0 // duplicate t0 in t2
|
|
add t4=2*Inc8,t0;; // duplicate t0 in t2
|
|
|
|
ld8 t1=[t0],3*Inc8
|
|
ld8 t3=[t2],3*Inc8
|
|
ld8 t5=[t4],3*Inc8;;
|
|
mov cr16=t1 // cr.ipsr
|
|
mov cr17=t3 // cr.isr is read only
|
|
// mov cr18=t5;; // cr.ida
|
|
|
|
ld8 t1=[t0],3*Inc8
|
|
ld8 t3=[t2],3*Inc8
|
|
ld8 t5=[t4],3*Inc8;;
|
|
mov cr19=t1 // cr.iip
|
|
mov cr20=t3 // cr.idtr
|
|
mov cr21=t5;; // cr.iitr
|
|
|
|
ld8 t1=[t0],3*Inc8
|
|
ld8 t3=[t2],3*Inc8
|
|
ld8 t5=[t4],3*Inc8;;
|
|
mov cr22=t1 // cr.iipa
|
|
mov cr23=t3 // cr.ifs
|
|
mov cr24=t5 // cr.iim
|
|
|
|
ld8 t1=[t0],160;; // 160 byte increment
|
|
mov cr25=t1 // cr.iha
|
|
|
|
rSkipIntrRegs::
|
|
ld8 t1=[t0],168;; // another 168 byte inc.
|
|
|
|
ld8 t1=[t0],40;; // 40 byte increment
|
|
mov cr66=t1 // cr.lid
|
|
|
|
ld8 t1=[t0],Inc8;;
|
|
// mov cr71=t1 // cr.ivr is read only
|
|
ld8 t1=[t0],24;; // 24 byte increment
|
|
mov cr72=t1 // cr.tpr
|
|
|
|
ld8 t1=[t0],168;; // 168 byte inc.
|
|
// mov cr75=t1 // cr.eoi
|
|
|
|
ld8 t1=[t0],Inc16;; // 16 byte inc.
|
|
// mov cr96=t1 // cr.irr0 is read only
|
|
|
|
ld8 t1=[t0],Inc16;; // 16 byte inc.
|
|
// mov cr98=t1 // cr.irr1 is read only
|
|
|
|
ld8 t1=[t0],Inc16;; // 16 byte inc
|
|
// mov cr100=t1 // cr.irr2 is read only
|
|
|
|
ld8 t1=[t0],Inc16;; // 16b inc.
|
|
// mov cr102=t1 // cr.irr3 is read only
|
|
|
|
ld8 t1=[t0],Inc16;; // 16 byte inc.
|
|
// mov cr114=t1 // cr.itv
|
|
|
|
ld8 t1=[t0],Inc8;;
|
|
// mov cr116=t1 // cr.pmv
|
|
ld8 t1=[t0],Inc8;;
|
|
// mov cr117=t1 // cr.lrr0
|
|
ld8 t1=[t0],Inc8;;
|
|
// mov cr118=t1 // cr.lrr1
|
|
ld8 t1=[t0],Inc8*10;;
|
|
// mov cr119=t1 // cr.cmcv
|
|
|
|
restore_ARs::
|
|
add t2=Inc8,t0 // duplicate t0 in t2
|
|
add t4=2*Inc8,t0;; // duplicate t0 in t2
|
|
|
|
ld8 t1=[t0],3*Inc8
|
|
ld8 t3=[t2],3*Inc8
|
|
ld8 t5=[t4],3*Inc8;;
|
|
mov ar0=t1 // ar.kro
|
|
mov ar1=t3 // ar.kr1
|
|
mov ar2=t5;; // ar.kr2
|
|
|
|
ld8 t1=[t0],3*Inc8
|
|
ld8 t3=[t2],3*Inc8
|
|
ld8 t5=[t4],3*Inc8;;
|
|
mov ar3=t1 // ar.kr3
|
|
mov ar4=t3 // ar.kr4
|
|
mov ar5=t5;; // ar.kr5
|
|
|
|
ld8 t1=[t0],10*Inc8
|
|
ld8 t3=[t2],10*Inc8
|
|
ld8 t5=[t4],10*Inc8;;
|
|
mov ar6=t1 // ar.kr6
|
|
mov ar7=t3 // ar.kr7
|
|
// mov ar8=t4 // ar.kr8
|
|
;;
|
|
|
|
ld8 t1=[t0],3*Inc8
|
|
ld8 t3=[t2],3*Inc8
|
|
ld8 t5=[t4],3*Inc8;;
|
|
// mov ar16=t1 // ar.rsc
|
|
// mov ar17=t3 // ar.bsp is read only
|
|
mov ar18=t5;; // ar.bspstore
|
|
|
|
ld8 t1=[t0],Inc8*13;;
|
|
mov ar19=t1 // ar.rnat
|
|
|
|
ld8 t1=[t0],Inc8*4;;
|
|
mov ar32=t1 // ar.ccv
|
|
|
|
ld8 t1=[t0],Inc8*4;;
|
|
mov ar36=t1 // ar.unat
|
|
|
|
ld8 t1=[t0],Inc8*4;;
|
|
mov ar40=t1 // ar.fpsr
|
|
|
|
ld8 t1=[t0],160;; // 160
|
|
// mov ar44=t1 // ar.itc
|
|
|
|
ld8 t1=[t0],Inc8;;
|
|
mov ar64=t1 // ar.pfs
|
|
|
|
ld8 t1=[t0],Inc8;;
|
|
mov ar65=t1 // ar.lc
|
|
|
|
ld8 t1=[t0];;
|
|
mov ar66=t1 // ar.ec
|
|
adds t0=Inc8*62,t0;; // padding
|
|
|
|
restore_RRs::
|
|
mov t3=ar.lc
|
|
mov ar.lc=0x08-1
|
|
movl t2=0x00
|
|
cStRRr::
|
|
ld8 t1=[t0],Inc8;;
|
|
// mov rr[t2]=t1 // what are its access previledges?
|
|
add t2=1,t2
|
|
br.cloop.dpnt cStRRr
|
|
;;
|
|
mov ar.lc=t3
|
|
|
|
// align memory addresses to 16 bytes
|
|
and t1=0x0f,t0;;
|
|
cmp.ne.unc pt0,p0=t1,r0;;
|
|
(pt0) add t0=Inc8,t0;;
|
|
|
|
// restore FP's which might be trashed by the "C" code
|
|
mov t3=ar.unat
|
|
add t1=16*10,t0;; // to get to NaT of GR 16-31
|
|
ld8 t1=[t1];;
|
|
mov ar.unat=t1;; // first restore NaT
|
|
|
|
restore_FRs::
|
|
ldf.fill f6=[t0],Inc16;;
|
|
ldf.fill f7=[t0],Inc16;;
|
|
ldf.fill f8=[t0],Inc16;;
|
|
ldf.fill f9=[t0],Inc16;;
|
|
ldf.fill f10=[t0],Inc16;;
|
|
ldf.fill f11=[t0],Inc16;;
|
|
ldf.fill f12=[t0],Inc16;;
|
|
ldf.fill f13=[t0],Inc16;;
|
|
ldf.fill f14=[t0],Inc16;;
|
|
ldf.fill f15=[t0],Inc16;;
|
|
|
|
mov ar.unat=t3 // restore original NaT
|
|
|
|
br.dpnt osMcaDoneRestore
|
|
;;
|
|
|
|
//EndStub//////////////////////////////////////////////////////////////////////
|
|
|
|
//++
|
|
// VOID
|
|
// HalpAcquireMcaSpinLock (
|
|
// IN PKSPIN_LOCK SpinLock
|
|
// )
|
|
//
|
|
// Routine Description:
|
|
//
|
|
// This function acquires a MCA spin lock.
|
|
// This function does not modify the interrupt state or the IRQL.
|
|
//
|
|
// N.B: This function does *NOT* replace KiAcquireSpinLock but
|
|
// allows us to place it in a locked MCA specific section.
|
|
//
|
|
// Arguments:
|
|
//
|
|
// SpinLock (a0) - Supplies a pointer to a MCA spin lock.
|
|
//
|
|
// Return Value:
|
|
//
|
|
// None.
|
|
//
|
|
//--
|
|
|
|
.align 16
|
|
|
|
LEAF_ENTRY(HalpAcquireMcaSpinLock)
|
|
|
|
#if !defined(NT_UP)
|
|
|
|
ACQUIRE_SPINLOCK(a0,a0,Halpasl10)
|
|
|
|
br.ret.dptk brp
|
|
;;
|
|
|
|
#else
|
|
|
|
LEAF_RETURN
|
|
|
|
#endif // !defined(NT_UP)
|
|
|
|
LEAF_EXIT(HalpAcquireMcaSpinLock)
|
|
|
|
//EndProc//////////////////////////////////////////////////////////////////////
|
|
|
|
//++
|
|
// VOID
|
|
// HalpReleaseMcaSpinLock (
|
|
// IN PKSPIN_LOCK SpinLock
|
|
// )
|
|
//
|
|
// Routine Description:
|
|
//
|
|
// This function release a MCA spin lock.
|
|
// This function does not modify the interrupt state or the IRQL.
|
|
//
|
|
// N.B: This function does *NOT* replace KiReleaseSpinLock but
|
|
// allows us to place it in a locked MCA specific section.
|
|
//
|
|
// Arguments:
|
|
//
|
|
// SpinLock (a0) - Supplies a pointer to a MCA spin lock.
|
|
//
|
|
// Return Value:
|
|
//
|
|
// None.
|
|
//
|
|
//--
|
|
|
|
.align 16
|
|
|
|
LEAF_ENTRY(HalpReleaseMcaSpinLock)
|
|
|
|
#if !defined(NT_UP)
|
|
st8.rel [a0] = zero // set spin lock not owned
|
|
#endif
|
|
|
|
LEAF_RETURN
|
|
LEAF_EXIT(HalpReleaseMcaSpinLock)
|
|
|
|
//EndProc//////////////////////////////////////////////////////////////////////
|
|
|
|
|
|
//++
|
|
// Name:
|
|
// HalpMCAEnable()
|
|
//
|
|
// Routine Description:
|
|
//
|
|
// This procedure enables MCA resources that are not already enabled.
|
|
//
|
|
// Arguments:
|
|
//
|
|
// None
|
|
//
|
|
// Return value:
|
|
//
|
|
// None
|
|
//
|
|
//--
|
|
.align 16
|
|
.proc HalpMCAEnable
|
|
HalpMCAEnable::
|
|
NESTED_SETUP(0,2,0,0);;
|
|
|
|
// nothing right now...
|
|
|
|
NESTED_RETURN
|
|
.endp HalpMCAEnable
|
|
|
|
//EndProc//////////////////////////////////////////////////////////////////////
|