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587 lines
14 KiB
587 lines
14 KiB
/*++
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Copyright (c) 1997 Microsoft Corporation
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Module Name:
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ixslpsup.c
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Abstract:
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This file provides the code that saves and restores
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state for traditional motherboard devices when the
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system goes into a sleep state that removes power.
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This code is included in multiple HALs.
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Author:
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Jake Oshins (jakeo) May 6, 1997
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Revision History:
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--*/
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#include "halp.h"
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#include "ixsleep.h"
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#if (defined(APIC_HAL) || defined(ACPI_HAL))
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#include "apic.inc"
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#include "..\..\halmps\i386\pcmp_nt.inc"
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#if !defined(_AMD64_)
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VOID
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StartPx_RMStub(
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VOID
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);
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#endif
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#endif
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typedef struct _SAVE_CONTEXT_DPC_CONTEXT {
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PVOID SaveArea;
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volatile ULONG Complete;
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} SAVE_CONTEXT_DPC_CONTEXT, *PSAVE_CONTEXT_DPC_CONTEXT;
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VOID
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HalpSaveContextTargetProcessor (
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IN PKDPC Dpc,
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IN PVOID DeferredContext,
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IN PVOID SystemArgument1,
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IN PVOID SystemArgument2
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);
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#ifdef WANT_IRQ_ROUTING
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#include "ixpciir.h"
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#endif
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extern UCHAR HalpAsmDataMarker;
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extern PVOID HalpEisaControlBase;
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extern ULONG HalpIrqMiniportInitialized;
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PKPROCESSOR_STATE HalpHiberProcState;
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ULONG CurTiledCr3LowPart;
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PPHYSICAL_ADDRESS HalpTiledCr3Addresses;
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#ifdef ALLOC_PRAGMA
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#pragma alloc_text(PAGE, HaliLocateHiberRanges)
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#pragma alloc_text(PAGELK, HalpSavePicState)
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#pragma alloc_text(PAGELK, HalpSaveDmaControllerState)
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#pragma alloc_text(PAGELK, HalpSaveTimerState)
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#pragma alloc_text(PAGELK, HalpRestorePicState)
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#pragma alloc_text(PAGELK, HalpRestoreDmaControllerState)
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#pragma alloc_text(PAGELK, HalpRestoreTimerState)
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#pragma alloc_text(PAGELK, HalpBuildResumeStructures)
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#pragma alloc_text(PAGELK, HalpFreeResumeStructures)
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#pragma alloc_text(PAGELK, HalpSaveContextTargetProcessor)
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#endif
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#define EISA_CONTROL (PUCHAR)&((PEISA_CONTROL) HalpEisaControlBase)
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VOID
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HalpPowerStateCallback(
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IN PVOID CallbackContext,
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IN PVOID Argument1,
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IN PVOID Argument2
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)
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{
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ULONG action = PtrToUlong(Argument1);
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ULONG state = PtrToUlong(Argument2);
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if (action == PO_CB_SYSTEM_STATE_LOCK) {
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switch (state) {
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case 0:
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//
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// Lock down everything in the PAGELK code section. (We chose
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// HalpSaveDmaControllerState because it exists in every HAL.)
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//
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HalpSleepPageLock = MmLockPagableCodeSection((PVOID)HalpSaveDmaControllerState);
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#if (defined(APIC_HAL) || defined(ACPI_HAL)) && !defined(_AMD64_)
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HalpSleepPage16Lock = MmLockPagableCodeSection((PVOID) StartPx_RMStub );
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#endif
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#ifdef ACPI_HAL
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HalpMapNvsArea();
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#endif
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break;
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case 1: // unlock it all
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MmUnlockPagableImageSection(HalpSleepPageLock);
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#if (defined(APIC_HAL) || defined(ACPI_HAL)) && !defined(_AMD64_)
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MmUnlockPagableImageSection(HalpSleepPage16Lock);
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#endif
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#ifdef ACPI_HAL
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HalpFreeNvsBuffers();
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#endif
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}
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}
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return;
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}
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VOID
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HalpSavePicState(
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VOID
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)
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{
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HalpMotherboardState.PicState.MasterMask =
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READ_PORT_UCHAR(EISA_CONTROL->Interrupt1ControlPort1);
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HalpMotherboardState.PicState.SlaveMask =
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READ_PORT_UCHAR(EISA_CONTROL->Interrupt2ControlPort1);
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#if !defined(ACPI_HAL)
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#ifdef WANT_IRQ_ROUTING
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if(HalpIrqMiniportInitialized)
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{
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ULONG elcrMask = 0;
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PciirqmpGetTrigger(&elcrMask);
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HalpMotherboardState.PicState.MasterEdgeLevelControl = (UCHAR)((elcrMask >> 8) & 0xFF);
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HalpMotherboardState.PicState.SlaveEdgeLevelControl = (UCHAR)(elcrMask & 0xFF);
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}
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else
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{
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#endif
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if (HalpBusType == MACHINE_TYPE_EISA) {
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#endif
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HalpMotherboardState.PicState.MasterEdgeLevelControl =
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READ_PORT_UCHAR(EISA_CONTROL->Interrupt1EdgeLevel);
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HalpMotherboardState.PicState.SlaveEdgeLevelControl =
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READ_PORT_UCHAR(EISA_CONTROL->Interrupt2EdgeLevel);
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#if !defined(ACPI_HAL)
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}
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#ifdef WANT_IRQ_ROUTING
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}
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#endif
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#endif
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}
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VOID
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HalpRestorePicState(
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VOID
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)
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{
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ULONG flags;
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flags = HalpDisableInterrupts();
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HalpInitializePICs(FALSE);
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WRITE_PORT_UCHAR(EISA_CONTROL->Interrupt1ControlPort1,
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HalpMotherboardState.PicState.MasterMask);
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WRITE_PORT_UCHAR(EISA_CONTROL->Interrupt2ControlPort1,
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HalpMotherboardState.PicState.SlaveMask);
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//
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// For halx86, the PCI interrupt vector programming
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// is static, so this code can just restore everything.
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//
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HalpRestorePicEdgeLevelRegister();
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HalpRestoreInterrupts(flags);
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}
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VOID
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HalpRestorePicEdgeLevelRegister(
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VOID
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)
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{
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#if !defined(ACPI_HAL)
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#ifdef WANT_IRQ_ROUTING
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if(HalpIrqMiniportInitialized)
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{
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PLINK_NODE linkNode;
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PLINK_STATE temp;
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ULONG elcrMask = (HalpMotherboardState.PicState.MasterEdgeLevelControl << 8) |
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HalpMotherboardState.PicState.SlaveEdgeLevelControl;
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PciirqmpSetTrigger(elcrMask);
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//
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// Reprogram all links.
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//
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for ( linkNode = HalpPciIrqRoutingInfo.LinkNodeHead;
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linkNode;
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linkNode = linkNode->Next)
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{
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//
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// Swap the possible with the allocation.
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//
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temp = linkNode->Allocation;
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linkNode->Allocation = linkNode->PossibleAllocation;
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linkNode->PossibleAllocation = temp;
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HalpCommitLink(linkNode);
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}
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}
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else
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{
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#endif
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if (HalpBusType == MACHINE_TYPE_EISA) {
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#endif
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WRITE_PORT_UCHAR(EISA_CONTROL->Interrupt1EdgeLevel,
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HalpMotherboardState.PicState.MasterEdgeLevelControl);
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WRITE_PORT_UCHAR(EISA_CONTROL->Interrupt2EdgeLevel,
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HalpMotherboardState.PicState.SlaveEdgeLevelControl);
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#if !defined(ACPI_HAL)
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}
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#ifdef WANT_IRQ_ROUTING
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}
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#endif
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#endif
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}
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VOID
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HalpSaveDmaControllerState(
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VOID
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)
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{
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}
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VOID
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HalpRestoreDmaControllerState(
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VOID
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)
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/*++
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Routine Description:
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This function puts the DMA controller back into the
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same state it was in before the machine went to sleep.
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Arguments:
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None.
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Notes:
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Normally, the DMA controller structures would be guarded
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by spinlocks. But this function is called with interrupts
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turned off and all but one processor spinning.
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--*/
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{
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UCHAR i;
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WRITE_PORT_UCHAR(EISA_CONTROL->Dma1BasePort.AllMask,0xF);
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WRITE_PORT_UCHAR(EISA_CONTROL->Dma2BasePort.AllMask,0xE);
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HalpIoDelay();
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//
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//Reset the DMA command registers
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//
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#if defined(NEC_98)
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WRITE_PORT_UCHAR(EISA_CONTROL->Dma1BasePort.DmaStatus,0x40);
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WRITE_PORT_UCHAR(EISA_CONTROL->Dma2BasePort.DmaStatus,0x40);
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#else
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WRITE_PORT_UCHAR(EISA_CONTROL->Dma1BasePort.DmaStatus,0);
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WRITE_PORT_UCHAR(EISA_CONTROL->Dma2BasePort.DmaStatus,0);
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#endif
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HalpIoDelay();
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for (i = 0; i < (EISA_DMA_CHANNELS / 2); i++) {
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//
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// Check to see if the array contains a value for this channel.
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//
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if (HalpDmaChannelState[i].ChannelProgrammed) {
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WRITE_PORT_UCHAR(EISA_CONTROL->Dma1BasePort.Mode,
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HalpDmaChannelState[i].ChannelMode);
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if (HalpEisaDma) {
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WRITE_PORT_UCHAR(EISA_CONTROL->Dma1ExtendedModePort,
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HalpDmaChannelState[i].ChannelExtendedMode);
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}
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WRITE_PORT_UCHAR(EISA_CONTROL->Dma1BasePort.SingleMask,
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HalpDmaChannelState[i].ChannelMask);
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HalpIoDelay();
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}
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}
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for (i = (EISA_DMA_CHANNELS / 2); i < EISA_DMA_CHANNELS; i++) {
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//
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// Check to see if the array contains a value for this channel.
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//
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if (HalpDmaChannelState[i].ChannelProgrammed) {
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WRITE_PORT_UCHAR(EISA_CONTROL->Dma2BasePort.Mode,
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HalpDmaChannelState[i].ChannelMode);
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if (HalpEisaDma) {
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WRITE_PORT_UCHAR(EISA_CONTROL->Dma2ExtendedModePort,
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HalpDmaChannelState[i].ChannelExtendedMode);
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}
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WRITE_PORT_UCHAR(EISA_CONTROL->Dma2BasePort.SingleMask,
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HalpDmaChannelState[i].ChannelMask);
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HalpIoDelay();
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}
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}
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}
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VOID
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HalpSaveTimerState(
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VOID
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)
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{
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}
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VOID
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HalpRestoreTimerState(
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VOID
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)
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{
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HalpInitializeClock();
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}
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VOID
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HaliLocateHiberRanges (
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IN PVOID MemoryMap
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)
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{
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//
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// Mark the hal's data section as needed to be cloned
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//
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PoSetHiberRange (
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MemoryMap,
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PO_MEM_CLONE,
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(PVOID) &HalpFeatureBits,
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0,
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'dlah'
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);
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#if defined(_HALPAE_)
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//
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// Mark DMA buffers as not needing to be saved.
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//
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if (MasterAdapter24.MapBufferSize != 0) {
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PoSetHiberRange( MemoryMap,
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PO_MEM_DISCARD | PO_MEM_PAGE_ADDRESS,
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(PVOID)(ULONG_PTR)(MasterAdapter24.MapBufferPhysicalAddress.LowPart >>
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PAGE_SHIFT),
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MasterAdapter24.MapBufferSize >> PAGE_SHIFT,
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'mlah' );
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}
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if (MasterAdapter32.MapBufferSize != 0) {
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PoSetHiberRange( MemoryMap,
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PO_MEM_DISCARD | PO_MEM_PAGE_ADDRESS,
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(PVOID)(ULONG_PTR)(MasterAdapter32.MapBufferPhysicalAddress.LowPart >>
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PAGE_SHIFT),
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MasterAdapter32.MapBufferSize >> PAGE_SHIFT,
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'mlah' );
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}
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#else
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//
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// Mark DMA buffer has not needing saved
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//
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if (HalpMapBufferSize) {
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PoSetHiberRange (
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MemoryMap,
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PO_MEM_DISCARD | PO_MEM_PAGE_ADDRESS,
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(PVOID) (HalpMapBufferPhysicalAddress.LowPart >> PAGE_SHIFT),
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HalpMapBufferSize >> PAGE_SHIFT,
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'mlah'
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);
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}
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#endif
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}
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NTSTATUS
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HalpBuildResumeStructures(
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VOID
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)
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{
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KAFFINITY CurrentAffinity, ActiveProcessors;
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ULONG ProcNum, Processor, NumberProcessors = 1;
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KDPC Dpc;
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SAVE_CONTEXT_DPC_CONTEXT Context;
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ASSERT(KeGetCurrentIrql() == DISPATCH_LEVEL);
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#if defined(APIC_HAL)
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//
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// If KeActiveProcessors() were callable at
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// DISPATCH_LEVEL, I would use that.
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//
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NumberProcessors = HalpMpInfoTable.NtProcessors;
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#endif
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ActiveProcessors = (1 << NumberProcessors) - 1;
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#if defined(APIC_HAL) || defined(ACPI_HAL)
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//
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// Allocate space to save processor context for other processors
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//
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HalpTiledCr3Addresses = NULL;
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HalpHiberProcState =
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ExAllocatePoolWithTag(NonPagedPool,
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(NumberProcessors * sizeof(KPROCESSOR_STATE)),
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HAL_POOL_TAG);
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if (!HalpHiberProcState) {
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goto BuildResumeStructuresError;
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}
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RtlZeroMemory(HalpHiberProcState,
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NumberProcessors * sizeof(KPROCESSOR_STATE));
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//
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// Allocate space for tiled CR3 for all processors
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//
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HalpTiledCr3Addresses =
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ExAllocatePoolWithTag(NonPagedPool,
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(NumberProcessors * sizeof(PHYSICAL_ADDRESS)),
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HAL_POOL_TAG);
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if (!HalpTiledCr3Addresses) {
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goto BuildResumeStructuresError;
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}
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RtlZeroMemory(HalpTiledCr3Addresses,
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(NumberProcessors * sizeof(PHYSICAL_ADDRESS)));
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//
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// Get IDT and GDT for all processors except BSP,
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// map and save tiled CR3
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//
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KeInitializeDpc (&Dpc, HalpSaveContextTargetProcessor, &Context);
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KeSetImportanceDpc (&Dpc, HighImportance);
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ProcNum = 0;
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CurrentAffinity = 1;
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Processor = 0;
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while (ActiveProcessors) {
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if (ActiveProcessors & CurrentAffinity) {
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ActiveProcessors &= ~CurrentAffinity;
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RtlZeroMemory(&Context, sizeof(Context));
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Context.SaveArea = &(HalpHiberProcState[ProcNum]);
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if (Processor == CurrentPrcb(KeGetPcr())->Number) {
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//
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// We're running on this processor. Just call
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// the DPC routine from here.
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HalpSaveContextTargetProcessor(&Dpc, &Context, NULL, NULL);
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} else {
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//
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// Issue DPC to target processor
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//
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KeSetTargetProcessorDpc (&Dpc, (CCHAR) Processor);
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KeInsertQueueDpc (&Dpc, NULL, NULL);
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//
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// Wait for DPC to be complete.
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//
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while (Context.Complete == FALSE);
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}
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ProcNum++;
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}
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Processor++;
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CurrentAffinity <<= 1;
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}
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for (ProcNum = 0; ProcNum < NumberProcessors; ProcNum++) {
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HalpTiledCr3Addresses[ProcNum].LowPart =
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HalpBuildTiledCR3Ex(&(HalpHiberProcState[ProcNum]),ProcNum);
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}
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#endif
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return STATUS_SUCCESS;
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#if defined(APIC_HAL) || defined(ACPI_HAL)
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BuildResumeStructuresError:
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if (HalpHiberProcState) ExFreePool(HalpHiberProcState);
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if (HalpTiledCr3Addresses) ExFreePool(HalpTiledCr3Addresses);
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return STATUS_UNSUCCESSFUL;
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#endif
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}
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NTSTATUS
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HalpFreeResumeStructures(
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VOID
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)
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{
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ULONG ProcNum, NumberProcessors = 1;
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#if defined(APIC_HAL)
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NumberProcessors = HalpMpInfoTable.NtProcessors;
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#endif
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#if defined(APIC_HAL) || defined(ACPI_HAL)
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if (HalpHiberProcState) {
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ExFreePool(HalpHiberProcState);
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HalpHiberProcState = NULL;
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}
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if (HalpTiledCr3Addresses) {
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ExFreePool(HalpTiledCr3Addresses);
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HalpTiledCr3Addresses = NULL;
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}
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for (ProcNum = 0; ProcNum < NumberProcessors; ProcNum++) {
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HalpFreeTiledCR3Ex(ProcNum);
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}
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#endif
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return STATUS_SUCCESS;
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}
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VOID
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HalpSaveContextTargetProcessor (
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IN PKDPC Dpc,
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IN PVOID DeferredContext,
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IN PVOID SystemArgument1,
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IN PVOID SystemArgument2
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)
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{
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PSAVE_CONTEXT_DPC_CONTEXT Context = (PSAVE_CONTEXT_DPC_CONTEXT)DeferredContext;
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KeSaveStateForHibernate(Context->SaveArea);
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InterlockedIncrement(&Context->Complete);
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}
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