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435 lines
7.8 KiB
435 lines
7.8 KiB
/*++
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Copyright (c) 1997-2000 Microsoft Corporation
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Module Name:
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pat.c
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Abstract:
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This module implements interfaces that set the Page Attribute
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Table. These entry points only exist on i386 machines.
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Author:
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Shivnandan Kaushik (Intel Corp.)
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Environment:
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Kernel mode only.
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Revision History:
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--*/
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#include "ki.h"
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#include "pat.h"
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//
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// Use lockstep mechanism from mtrr code.
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//
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#include "mtrr.h"
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#if DBG
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#define DBGMSG(a) DbgPrint(a)
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#else
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#define DBGMSG(a)
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#endif
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//
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// Structure used for PAT initialization
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//
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typedef struct _NEW_PAT {
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PAT Attributes;
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//
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// IPI context to coordinate concurrent PAT update
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//
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PROCESSOR_LOCKSTEP Synchronize;
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} NEW_PAT, *PNEW_PAT;
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// Prototypes
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VOID
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KeRestorePAT (
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VOID
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);
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VOID
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KiInitializePAT (
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VOID
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);
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VOID
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KiLoadPAT (
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IN PNEW_PAT Context
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);
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VOID
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KiLoadPATTarget (
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IN PKIPI_CONTEXT SignalDone,
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IN PVOID Context,
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IN PVOID Parameter2,
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IN PVOID Parameter3
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);
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#if DBG
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VOID
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KiDumpPAT (
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PUCHAR DebugString,
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PAT Attributes
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);
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#endif
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#ifdef ALLOC_PRAGMA
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#pragma alloc_text(PAGELK,KiInitializePAT)
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#pragma alloc_text(PAGELK,KiLoadPAT)
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#pragma alloc_text(PAGELK,KiLoadPATTarget)
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#endif
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VOID
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KeRestorePAT (
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VOID
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)
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/*++
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Routine Description:
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Reinitialize the Page Attribute Table (PAT) on all processors.
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N.B. The caller must have the PAGELK code locked
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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if (KeFeatureBits & KF_PAT) {
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KiInitializePAT();
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}
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}
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VOID
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KiInitializePAT (
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VOID
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)
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/*++
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Routine Description:
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Initialize the Page Attribute Table (PAT) on all processors. PAT
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is setup to provide WB, WC, STRONG_UC and WEAK_UC as the memory
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types such that mm macros for enabling/disabling/querying caching
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(MI_DISABLE_CACHING, MI_ENABLE_CACHING and MI_IS_CACHING_ENABLED)
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are unaffected.
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PAT_Entry PAT Index PCD PWT Memory Type
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0 0 0 0 WB
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1 0 0 1 WC *
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2 0 1 0 WEAK_UC
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3 0 1 1 STRONG_UC
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4 1 0 0 WB
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5 1 0 1 WC *
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6 1 1 0 WEAK_UC
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7 1 1 1 STRONG_UC
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N.B. The caller must have the PAGELK code locked and ensure that the
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PAT feature is supported.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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PAT PatAttributes;
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KIRQL OldIrql;
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PKPRCB Prcb;
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NEW_PAT NewPAT;
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#if !defined(NT_UP)
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KIRQL NewIrql;
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KAFFINITY TargetProcessors;
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#endif
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ASSERT ((KeFeatureBits & KF_PAT) != 0);
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//
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// Initialize the PAT
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//
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PatAttributes.hw.Pat[0] = PAT_TYPE_WB;
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PatAttributes.hw.Pat[1] = PAT_TYPE_USWC;
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PatAttributes.hw.Pat[2] = PAT_TYPE_WEAK_UC;
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PatAttributes.hw.Pat[3] = PAT_TYPE_STRONG_UC;
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PatAttributes.hw.Pat[4] = PAT_TYPE_WB;
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PatAttributes.hw.Pat[5] = PAT_TYPE_USWC;
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PatAttributes.hw.Pat[6] = PAT_TYPE_WEAK_UC;
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PatAttributes.hw.Pat[7] = PAT_TYPE_STRONG_UC;
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//
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// Synchronize with other IPI functions which may stall
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//
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KeAcquireSpinLock (&KiReverseStallIpiLock, &OldIrql);
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Prcb = KeGetCurrentPrcb();
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NewPAT.Attributes = PatAttributes;
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NewPAT.Synchronize.TargetCount = 0;
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NewPAT.Synchronize.TargetPhase = &Prcb->ReverseStall;
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NewPAT.Synchronize.Processor = Prcb->Number;
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#if !defined(NT_UP)
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//
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// Collect all the (other) processors
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//
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TargetProcessors = KeActiveProcessors & ~Prcb->SetMember;
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if (TargetProcessors != 0) {
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KiIpiSendSynchronousPacket (
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Prcb,
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TargetProcessors,
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KiLoadPATTarget,
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(PVOID) (&NewPAT),
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NULL,
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NULL
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);
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//
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// Wait for all processors to be collected
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//
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KiIpiStallOnPacketTargets(TargetProcessors);
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//
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// All processors are now waiting. Raise to high level to
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// ensure this processor doesn't enter the debugger due to
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// some interrupt service routine.
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//
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KeRaiseIrql (HIGH_LEVEL, &NewIrql);
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//
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// There's no reason for any debug events now, so signal
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// the other processors that they can all begin the PAT update
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//
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Prcb->ReverseStall += 1;
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}
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#endif
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//
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// Update PAT
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//
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KiLoadPAT(&NewPAT);
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//
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// Release lock and lower to initial irql
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//
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KeReleaseSpinLock (&KiReverseStallIpiLock, OldIrql);
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MmEnablePAT();
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return;
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}
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VOID
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KiLoadPATTarget (
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IN PKIPI_CONTEXT SignalDone,
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IN PVOID NewPAT,
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IN PVOID Parameter2,
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IN PVOID Parameter3
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)
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/*++
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Routine Description:
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Synchronize with target processors prior to PAT modification.
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Arguments:
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Context - Context which includes the PAT to load
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Return Value:
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None
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--*/
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{
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PNEW_PAT Context;
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UNREFERENCED_PARAMETER (Parameter2);
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UNREFERENCED_PARAMETER (Parameter3);
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Context = (PNEW_PAT) NewPAT;
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//
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// Wait for all processors to be ready
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//
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KiIpiSignalPacketDoneAndStall(SignalDone,
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Context->Synchronize.TargetPhase);
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//
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// Update PAT
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//
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KiLoadPAT (Context);
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}
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VOID
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KiLoadPAT (
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IN PNEW_PAT Context
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)
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/*++
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Routine Description:
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This function loads the PAT to all processors.
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Arguments:
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Context - Context which includes new PAT to load
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Return Value:
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PAT on all processors programmed to new values
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--*/
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{
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BOOLEAN Enable;
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ULONG HldCr0, HldCr4;
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//
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// Disable interrupts
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//
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Enable = KeDisableInterrupts();
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//
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// Synchronize all processors
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//
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KiLockStepExecution (&Context->Synchronize);
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_asm {
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;
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; Get current CR0
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;
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mov eax, cr0
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mov HldCr0, eax
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;
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; Disable caching & line fill
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;
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and eax, not CR0_NW
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or eax, CR0_CD
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mov cr0, eax
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;
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; Flush caches
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;
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;
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; wbinvd
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;
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_emit 0Fh
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_emit 09h
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;
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; Get current cr4
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;
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_emit 0Fh
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_emit 20h
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_emit 0E0h ; mov eax, cr4
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mov HldCr4, eax
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;
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; Disable global page
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;
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and eax, not CR4_PGE
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_emit 0Fh
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_emit 22h
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_emit 0E0h ; mov cr4, eax
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;
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; Flush TLB
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;
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mov eax, cr3
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mov cr3, eax
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}
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//
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// Load new PAT
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//
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WRMSR (PAT_MSR, Context->Attributes.QuadPart);
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_asm {
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;
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; Flush caches.
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;
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;
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; wbinvd
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;
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_emit 0Fh
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_emit 09h
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;
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; Flush TLBs
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;
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mov eax, cr3
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mov cr3, eax
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}
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_asm {
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;
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; Restore CR4 (global page enable)
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;
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mov eax, HldCr4
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_emit 0Fh
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_emit 22h
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_emit 0E0h ; mov cr4, eax
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;
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; Restore CR0 (cache enable)
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;
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mov eax, HldCr0
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mov cr0, eax
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}
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//
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// Wait for all processors to reach the same place,
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// restore interrupts and return.
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//
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KiLockStepExecution (&Context->Synchronize);
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KeEnableInterrupts (Enable);
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}
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