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676 lines
33 KiB
676 lines
33 KiB
/******************************Module*Header*******************************\
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*
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* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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* !! !!
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* !! WARNING: NOT DDK SAMPLE CODE !!
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* !! !!
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* !! This source code is provided for completeness only and should not be !!
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* !! used as sample code for display driver development. Only those sources !!
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* !! marked as sample code for a given driver component should be used for !!
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* !! development purposes. !!
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* !! !!
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* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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*
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* Module Name: tvp3026.h
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*
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* Content: This module contains the definitions for the TI TVP3026 RAMDAC.
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*
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* Copyright (c) 1994-1999 3Dlabs Inc. Ltd. All rights reserved.
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* Copyright (c) 1995-2003 Microsoft Corporation. All rights reserved.
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\*****************************************************************************/
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#define ADbgpf VideoDebugPrint
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//
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// TI TVP3026 RAMDAC definitions
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// This set of registers resides at &(pCtrlRegs->ExternalVideo)
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//
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typedef struct _tvp3026_regs {
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volatile RAMDAC_REG pciAddrWr; // 0x00 - palette/cursor RAM write address, Index Register
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volatile RAMDAC_REG palData; // 0x01 - palette RAM data
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volatile RAMDAC_REG pixelMask; // 0x02 - pixel read mask
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volatile RAMDAC_REG pcAddrRd; // 0x03 - palette/cursor RAM read address
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volatile RAMDAC_REG curAddrWr; // 0x04 - cursor/overscan color write address
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volatile RAMDAC_REG curData; // 0x05 - cursor/overscan color data
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volatile RAMDAC_REG Reserverd1; // 0x06 - reserved
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volatile RAMDAC_REG curAddrRd; // 0x07 - cursor/overscan color read address
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volatile RAMDAC_REG Reserverd2; // 0x08 - reserved
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volatile RAMDAC_REG curCtl; // 0x09 - direct cursor control
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volatile RAMDAC_REG indexData; // 0x0A - indexed data
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volatile RAMDAC_REG curRAMData; // 0x0B - cursor RAM data
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volatile RAMDAC_REG cursorXLow; // 0x0C - cursor position X low byte
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volatile RAMDAC_REG cursorXHigh; // 0x0D - cursor position X high byte
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volatile RAMDAC_REG cursorYLow; // 0x0E - cursor position Y low byte
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volatile RAMDAC_REG cursorYHigh; // 0x0F - cursor position Y high byte
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} TVP3026RAMDAC, *pTVP3026RAMDAC;
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// macro declared by any function wishing to use the TI TVP3026 RAMDAC . MUST be declared
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// after GLINT_DECL.
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//
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#if MINIVDD
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#define TVP3026_DECL \
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pTVP3026RAMDAC pTVP3026Regs = (pTVP3026RAMDAC)&(pDev->pRegisters->Glint.ExtVCReg)
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#else
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#define TVP3026_DECL \
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pTVP3026RAMDAC pTVP3026Regs = (pTVP3026RAMDAC)&(pRegisters->Glint.ExtVCReg)
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#endif
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// use the following macros as the address to pass to the
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// VideoPortWriteRegisterUlong function
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//
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// Palette Access
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#define __TVP3026_PAL_WR_ADDR ((PULONG)&(pTVP3026Regs->pciAddrWr.reg))
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#define __TVP3026_PAL_RD_ADDR ((PULONG)&(pTVP3026Regs->palAddrRd.reg))
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#define __TVP3026_PAL_DATA ((volatile PULONG)&(pTVP3026Regs->palData.reg))
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// Pixel mask
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#define __TVP3026_PIXEL_MASK ((PULONG)&(pTVP3026Regs->pixelMask.reg))
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// Access to the indexed registers
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#define __TVP3026_INDEX_ADDR ((PULONG)&(pTVP3026Regs->pciAddrWr.reg))
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#define __TVP3026_INDEX_DATA ((PULONG)&(pTVP3026Regs->indexData.reg))
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// Access to the Cursor
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#define __TVP3026_CUR_RAM_WR_ADDR ((PULONG)&(pTVP3026Regs->pciAddrWr.reg))
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#define __TVP3026_CUR_RAM_RD_ADDR ((PULONG)&(pTVP3026Regs->palAddrRd.reg))
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#define __TVP3026_CUR_RAM_DATA ((PULONG)&(pTVP3026Regs->curRAMData.reg))
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#define __TVP3026_CUR_WR_ADDR ((PULONG)&(pTVP3026Regs->curAddrWr.reg))
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#define __TVP3026_CUR_RD_ADDR ((PULONG)&(pTVP3026Regs->curAddrRd.reg))
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#define __TVP3026_CUR_DATA ((PULONG)&(pTVP3026Regs->curData.reg))
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#define __TVP3026_CUR_CTL ((PULONG)&(pTVP3026Regs->curCtl.reg))
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// Access to the overscan color
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#define __TVP3026_OVRC_WR_ADDR ((PULONG)&(pTVP3026Regs->curAddrWr.reg))
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#define __TVP3026_OVRC_RD_ADDR ((PULONG)&(pTVP3026Regs->curAddrRd.reg))
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#define __TVP3026_OVRC_DATA ((PULONG)&(pTVP3026Regs->curData.reg))
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// Cursor position control
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#define __TVP3026_CUR_X_LSB ((PULONG)&(pTVP3026Regs->cursorXLow.reg))
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#define __TVP3026_CUR_X_MSB ((PULONG)&(pTVP3026Regs->cursorXHigh.reg))
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#define __TVP3026_CUR_Y_LSB ((PULONG)&(pTVP3026Regs->cursorYLow.reg))
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#define __TVP3026_CUR_Y_MSB ((PULONG)&(pTVP3026Regs->cursorYHigh.reg))
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// ----------------------Values for some direct registers-----------------------
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/********************************************************************************/
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/* DIRECT REGISTER - CURSOR AND OVERSCAN COLOR */
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/********************************************************************************/
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// ** TVP3026_OVRC_WR_ADDR
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// ** TVP3026_OVRC_RD_ADDR
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// ** TVP3026_CUR_WR_ADDR
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// ** TVP3026_CUR_RD_ADDR
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// Default - undefined
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#define TVP3026_OVERSCAN_COLOR 0x00
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#define TVP3026_CURSOR_COLOR0 0x01
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#define TVP3026_CURSOR_COLOR1 0x02
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#define TVP3026_CURSOR_COLOR2 0x03
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/********************************************************************************/
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/* DIRECT REGISTER - CURSOR CONTROL */
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/********************************************************************************/
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// ** TVP3026_CUR_CTL
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// Default - 0x00
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#define TVP3026_CURSOR_OFF 0x00 // Cursor off
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#define TVP3026_CURSOR_COLOR 0x01 // 2-bits select color
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#define TVP3026_CURSOR_XGA 0x02 // 2-bits select XOR
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#define TVP3026_CURSOR_XWIN 0x03 // 2-bits select transparency/color
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/********************************************************************************/
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/* DIRECT REGISTER - CURSOR POSITION CONTROL */
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/********************************************************************************/
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// ** TVP3026_CUR_X_LSB
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// ** TVP3026_CUR_X_MSB
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// ** TVP3026_CUR_Y_LSB
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// ** TVP3026_CUR_Y_MSB
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// Default - undefined
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// Values written into those registers represent the BOTTOM-RIGHT corner
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// of the cursor. If 0 is in X or Y position - the cursor is off the screen
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// Only 12 bits are used, giving the range from 0 to 4095 ( 0x0000 - 0x0FFF)
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// The size of the cursor is (64,64) (0x40, 0x40)
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#define TVP3026_CURSOR_OFFSCREEN 0x00 // Cursor offscreen
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// ------------------------Indirect indexed registers map--------------------------
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/********************************************************************************/
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/* INDIRECT REGISTER - SILICON REVISION */
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/********************************************************************************/
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#define __TVP3026_SILICON_REVISION 0x01 // Chip revision:
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// bits 4-7 - major number, 0-3 - minor number
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// TVP3026_REVISION_LEVEL
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#define TVP3026_REVISION_LEVEL 0x01 // predefined
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// TVP3030_REVISION_LEVEL
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#define TVP3030_REVISION_LEVEL 0x00 // predefined
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/********************************************************************************/
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/* INDIRECT REGISTER - CHIP ID */
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/********************************************************************************/
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#define __TVP3026_CHIP_ID 0x3F //
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// Default - 0x26
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#define TVP3026_ID_CODE 0x26 // predefined
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#define TVP3030_ID_CODE 0x30 // predefined
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/********************************************************************************/
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/* INDIRECT REGISTER - CURSOR CONTROL */
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/********************************************************************************/
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#define __TVP3026_CURSOR_CONTROL 0x06 // Indirect cursor control -
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// Default - 0x00
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#define TVP3026_CURSOR_USE_DIRECT_CCR (1 << 7)// Enable Direct Cursor Control Register
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#define TVP3026_CURSOR_USE_INDEX_CCR (0 << 7)// Disable Direct Cursor Control Register
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#define TVP3026_CURSOR_INTERLACE_ODD (1 << 6)// Detect odd field as 1
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#define TVP3026_CURSOR_INTERLACE_EVEN (0 << 6)// Detect even field as 1
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#define TVP3026_CURSOR_INTERLACE_ON (1 << 5)// Enable interlaced cursor
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#define TVP3026_CURSOR_INTERLACE_OFF (0 << 5)// Disable interlaced cursor
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#define TVP3026_CURSOR_VBLANK_4096 (1 << 4)// Blank is detected after 4096
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#define TVP3026_CURSOR_VBLANK_2048 (0 << 4)// or 2048 dot clocks
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#define TVP3026_CURSOR_RAM_ADDRESS(x) (((x) & 0x03) << 2)// High bits of cursor RAM address
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#define TVP3026_CURSOR_RAM_MASK ((0x03) << 2) // Mask for high bits of cursor RAM address
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// CURSOR_OFF 0x00 // Cursor off
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// CURSOR_COLOR 0x01 // 2-bits select color
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// CURSOR_XGA 0x02 // 2-bits select XOR
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// CURSOR_XWIN 0x03 // 2-bits select transparency/color
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/********************************************************************************/
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/* INDIRECT REGISTER - LATCH CONTROL */
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/********************************************************************************/
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#define __TVP3026_LATCH_CONTROL 0x0F // Latch control register -
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// Default - 0x06
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#define TVP3026_LATCH_ALL_MODES 0x06 // All modes except packed-24
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#define TVP3026_LATCH_4_3 0x07 // 4:3 or 8:3 packed-24
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#define TVP3026_LATCH_5_2 0x20 // 5:2 packed-24
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#define TVP3026_LATCH_5_4_1 0x1F // 5:4 packed-24 x1 horz zoom
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#define TVP3026_LATCH_5_4_2 0x1E // 5:4 packed-24 x2 horz zoom
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#define TVP3026_LATCH_5_4_4 0x1C // 5:4 packed-24 x4 horz zoom
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#define TVP3026_LATCH_5_4_8 0x18 // 5:4 packed-24 x8 horz zoom
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/********************************************************************************/
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/* INDIRECT REGISTER - TRUE COLOR CONTROL */
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/********************************************************************************/
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#define __TVP3026_TRUE_COLOR 0x18 // True Color control
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// Default - 0x80
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/********************************************************************************/
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/* INDIRECT REGISTER - MULTIPLEX CONTROL */
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/********************************************************************************/
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#define __TVP3026_MULTIPLEX_CONTROL 0x19 // Multiplex control
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// Default - 0x98
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/********************************************************************************/
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/* INDIRECT REGISTER - CLOCK SELECTION */
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/********************************************************************************/
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#define __TVP3026_CLOCK 0x1A //
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// Default - 0x07
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#define TVP3026_SCLK_ENABLE (1 << 7)// Enable SCLK output
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#define TVP3026_SCLK_DISABLE (0 << 7)// Disable SCLK output
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#define TVP3026_VCLK_ZERO (7 << 4)// VCLK forced to Logical "0"
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#define TVP3026_VCLK_DOTCLOCK (0 << 4)// VCLK is equal to Dot clock
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#define TVP3026_VCLK_DOTCLOCK_DIV2 (1 << 4)// VCLK is equal to Dot clock/2
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#define TVP3026_VCLK_DOTCLOCK_DIV4 (2 << 4)// VCLK is equal to Dot clock/4
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#define TVP3026_VCLK_DOTCLOCK_DIV8 (3 << 4)// VCLK is equal to Dot clock/8
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#define TVP3026_VCLK_DOTCLOCK_DIV16 (4 << 4)// VCLK is equal to Dot clock/16
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#define TVP3026_VCLK_DOTCLOCK_DIV32 (5 << 4)// VCLK is equal to Dot clock/32
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#define TVP3026_VCLK_DOTCLOCK_DIV64 (6 << 4)// VCLK is equal to Dot clock/64
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#define TVP3026_CLK_CLK0 (0 << 0)// Select CLK0 as clock source
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#define TVP3026_CLK_CLK1 (1 << 0)// Select CLK1 as clock source
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#define TVP3026_CLK_CLK2_TTL (2 << 0)// Select CLK2 as clock source
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#define TVP3026_CLK_CLK2N_TTL (3 << 0)// Select /CLK2 as clock source
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#define TVP3026_CLK_CLK2_ECL (4 << 0)// Select CLK2 and /CLK2 as ECL clock source
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#define TVP3026_CLK_PIXEL_PLL (5 << 0)// Select Pixel Clock PLL as clock source
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#define TVP3026_CLK_DISABLE (6 << 0)// Disable clock source / Power-save mode
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#define TVP3026_CLK_CLK0_VGA (7 << 0)// Select CLK0 as clock source with VGA latching
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/********************************************************************************/
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/* INDIRECT REGISTER - PALETTE PAGE */
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/********************************************************************************/
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#define __TVP3026_PALETTE_PAGE 0x1C //
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// Default - 0x00
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/********************************************************************************/
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/* INDIRECT REGISTER - GENERAL CONTROL */
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/********************************************************************************/
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#define __TVP3026_GENERAL_CONTROL 0x1D //
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// Default - 0x00
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#define TVP3026_OVERSCAN_ENABLE (1 << 6)// Enable overscan coloring
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#define TVP3026_OVERSCAN_DISABLE (0 << 6)// Disable overscan coloring
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#define TVP3026_SYNC_ENABLE (1 << 5)// Enable SYNC signal on IOG
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#define TVP3026_SYNC_DISABLE (0 << 5)// Disable SYNC signal on IOG
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#define TVP3026_PEDESTAL_ON (1 << 4)// Enable 7.5 IRE blanking pedestal
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#define TVP3026_PEDESTAL_OFF (0 << 4)// Disable blanking pedestal
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#define TVP3026_BIG_ENDIAN (1 << 3)// Big Endian format on pixel bus
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#define TVP3026_LITTLE_ENDIAN (0 << 3)// Little Endian format on pixel bus
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#define TVP3026_VSYNC_INVERT (1 << 1)// Invert VSYNC signal on VSYNCOUT
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#define TVP3026_VSYNC_NORMAL (0 << 1)// Do not invert VSYNC signal on VSYNCOUT
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#define TVP3026_HSYNC_INVERT (1 << 0)// Invert HSYNC signal on HSYNCOUT
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#define TVP3026_HSYNC_NORMAL (0 << 0)// Do not invert HSYNC signal on HSYNCOUT
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/********************************************************************************/
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/* INDIRECT REGISTER - MISC CONTROL */
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/********************************************************************************/
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#define __TVP3026_MISC_CONTROL 0x1E //
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// Default - 0x00
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#define TVP3026_PSEL_INVERT (1 << 5)// PSEL == 1 - Pseudo/True Color
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#define TVP3026_PSEL_NORMAL (0 << 5)// PSEL == 1 - Direct Color
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#define TVP3026_PSEL_ENABLE (1 << 4)// PSEL controls Color Switching
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#define TVP3026_PSEL_DISABLE (0 << 4)// PSEL is disabled
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#define TVP3026_DAC_8BIT (1 << 3)// DAC is in 8-bit mode
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#define TVP3026_DAC_6BIT (0 << 3)// DAC is in 6-bit mode
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#define TVP3026_DAC_6BITPIN_DISABLE (1 << 2)// Disable 6/8 pin and use bit 3 of this register
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#define TVP3026_DAC_6BITPIN_ENABLE (0 << 2)// Use 6/8 pin and ignore bit 3 of this register
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#define TVP3026_DAC_POWER_ON (0 << 0)// Turn DAC Power on
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#define TVP3026_DAC_POWER_OFF (1 << 0)// Turn DAC Power off
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/********************************************************************************/
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/* INDIRECT REGISTER - GP I/O CONTROL */
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/********************************************************************************/
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#define __TVP3026_GP_CONTROL 0x2A //
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// Default - 0x00
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/********************************************************************************/
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/* INDIRECT REGISTER - GP I/O DATA */
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/********************************************************************************/
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#define __TVP3026_GP_DATA 0x2B //
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// Default - undefined
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/********************************************************************************/
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/* INDIRECT REGISTER - PLL ADDRESS */
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/********************************************************************************/
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#define __TVP3026_PLL_ADDRESS 0x2C //
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// Default - undefined
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#define TVP3026_PIXEL_CLOCK_START 0xFC// Start Pixel Clock Programming
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#define TVP3026_MCLK_START 0xF3// Start MCLK Programming
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#define TVP3026_LOOP_CLOCK_START 0xCF// Start Loop Clock Programming
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/********************************************************************************/
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/* INDIRECT REGISTER - PLL PIXEL DATA */
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/********************************************************************************/
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#define __TVP3026_PLL_PIX_DATA 0x2D //
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// Default - undefined
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/********************************************************************************/
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/* INDIRECT REGISTER - PLL MEMORY DATA */
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/********************************************************************************/
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#define __TVP3026_PLL_MEM_DATA 0x2E //
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// Default - undefined
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/********************************************************************************/
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/* INDIRECT REGISTER - PLL LOOP DATA */
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/********************************************************************************/
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#define __TVP3026_PLL_LOOP_DATA 0x2F //
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// Default - undefined
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/********************************************************************************/
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/* INDIRECT REGISTER - COLOR KEY OVERLAY LOW */
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/********************************************************************************/
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#define __TVP3026_CCOVR_LOW 0x30 //
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// Default - undefined
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/********************************************************************************/
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/* INDIRECT REGISTER - COLOR KEY OVERLAY HIGH */
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/********************************************************************************/
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#define __TVP3026_CCOVR_HIGH 0x31 //
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// Default - undefined
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/********************************************************************************/
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/* INDIRECT REGISTER - COLOR KEY RED LOW */
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/********************************************************************************/
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#define __TVP3026_CCRED_LOW 0x32 //
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// Default - undefined
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/********************************************************************************/
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/* INDIRECT REGISTER - COLOR KEY RED HIGH */
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/********************************************************************************/
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#define __TVP3026_CCRED_HIGH 0x33 //
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// Default - undefined
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/********************************************************************************/
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/* INDIRECT REGISTER - COLOR KEY GREEN LOW */
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/********************************************************************************/
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#define __TVP3026_CCGREEN_LOW 0x34 //
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// Default - undefined
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/********************************************************************************/
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/* INDIRECT REGISTER - COLOR KEY RED HIGH */
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/********************************************************************************/
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#define __TVP3026_CCGREEN_HIGH 0x35 //
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// Default - undefined
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/********************************************************************************/
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/* INDIRECT REGISTER - COLOR KEY BLUE LOW */
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/********************************************************************************/
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#define __TVP3026_CCBLUE_LOW 0x36 //
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// Default - undefined
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/********************************************************************************/
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/* INDIRECT REGISTER - COLOR KEY BLUE HIGH */
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/********************************************************************************/
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#define __TVP3026_CCBLUE_HIGH 0x37 //
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// Default - undefined
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/********************************************************************************/
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/* INDIRECT REGISTER - COLOR KEY CONTROL */
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/********************************************************************************/
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#define __TVP3026_CC_CONTROL 0x38 //
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// Default - 0x00
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/********************************************************************************/
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/* INDIRECT REGISTER - MCLK/LOOP CONTROL */
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/********************************************************************************/
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#define __TVP3026_MCLK_CONTROL 0x39 //
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// Default - 0x18
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#define TVP3026_RCLK_LOOP (1 << 5)// RCLK is made from LCLK - all other modes
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#define TVP3026_RCLK_PIXEL (0 << 5)// RCLK is clocked by Pixel Clock (VGA Mode)
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#define TVP3026_MCLK_PLL (1 << 4)// MCLK from PLL - normal mode
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#define TVP3026_MCLK_DOT (0 << 4)// MCLK from dot clock - during freq. change
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#define TVP3026_MCLK_STROBE_HIGH (1 << 3)// Strobe high for bit 4
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#define TVP3026_MCLK_STROBE_LOW (0 << 3)// Strobe low for bit 4
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#define TVP3026_LOOP_DIVIDE2 (0 << 0)// Divide Loop clock by 2
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#define TVP3026_LOOP_DIVIDE4 (1 << 0)// Divide Loop clock by 4
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#define TVP3026_LOOP_DIVIDE6 (2 << 0)// Divide Loop clock by 6
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#define TVP3026_LOOP_DIVIDE8 (3 << 0)// Divide Loop clock by 8
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#define TVP3026_LOOP_DIVIDE10 (4 << 0)// Divide Loop clock by 10
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#define TVP3026_LOOP_DIVIDE12 (5 << 0)// Divide Loop clock by 12
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#define TVP3026_LOOP_DIVIDE14 (6 << 0)// Divide Loop clock by 14
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#define TVP3026_LOOP_DIVIDE16 (7 << 0)// Divide Loop clock by 16
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/********************************************************************************/
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/* INDIRECT REGISTER - SENSE TEST */
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/********************************************************************************/
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#define __TVP3026_SENSE_TEST 0x3A //
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// Default - 0x00
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/********************************************************************************/
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/* INDIRECT REGISTER - TEST MODE DATA */
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/********************************************************************************/
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#define __TVP3026_TEST_MODE 0x3B //
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// Default - undefined
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/********************************************************************************/
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/* INDIRECT REGISTER - CRC REMAINDER LSB */
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/********************************************************************************/
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#define __TVP3026_CRC_LSB 0x3C //
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// Default - undefined
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/********************************************************************************/
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/* INDIRECT REGISTER - CRC REMAINDER MSB */
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/********************************************************************************/
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#define __TVP3026_CRC_MSB 0x3D //
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// Default - undefined
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/********************************************************************************/
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/* INDIRECT REGISTER - CRC BITS SELECT */
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/********************************************************************************/
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#define __TVP3026_CRC_SELECT 0x3E //
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// Default - undefined
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/********************************************************************************/
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/* INDIRECT REGISTER - SOFTWARE RESET */
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/********************************************************************************/
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#define __TVP3026_SOFT_RESET 0xFF //
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// Default - undefined
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//
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// On rev 1 chips we need to SYNC with GLINT while accessing the RAMDAC. This
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// is because accesses to the RAMDAC can be corrupted by localbuffer
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// activity. Put this macro before accesses that can co-exist with GLINT
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// 3D activity, Must have initialized glintInfo before using this.
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//
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#define TVP3026_SYNC_WITH_GLINT \
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{ \
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if (GLInfo.wRenderChipRev == GLINT300SX_REV1) \
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SYNC_WITH_GLINT; \
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}
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/*
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// We never need a delay between each write to the 3026. The only way to guarantee
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// that the write has completed used to be to read from a GLINT control register.
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// Reading forces any posted writes to be flushed out. PPC needs 2 reads
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// to give us enough time.
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//#define TVP3026_DELAY \
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//{ \
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// volatile LONG __junk; \
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// __junk = pDev->pRegisters->Glint.FBModeSel; \
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//}
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//#else
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*/
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#define TVP3026_DELAY
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// macro to load a given data value into an internal TVP3026 register.
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//
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#define TVP3026_WRITE_CURRENT_INDEX TVP3026_SET_INDEX_REG
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#define TVP3026_SET_INDEX_REG(index) \
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{ \
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VideoPortWriteRegisterUlong(__TVP3026_INDEX_ADDR, (ULONG)((index) & 0xff)); \
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TVP3026_DELAY; \
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}
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#define TVP3026_READ_CURRENT_INDEX(data) \
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{ \
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data = VideoPortReadRegisterUlong(__TVP3026_INDEX_ADDR) & 0xff; \
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TVP3026_DELAY; \
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}
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#define TVP3026_WRITE_INDEX_REG(index, data) \
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{ \
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TVP3026_SET_INDEX_REG(index); \
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ADbgpf(("*(0x%X) <-- 0x%X\n", __TVP3026_INDEX_DATA, (data) & 0xff)); \
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VideoPortWriteRegisterUlong(__TVP3026_INDEX_DATA, (ULONG)((data) & 0xff)); \
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TVP3026_DELAY; \
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}
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#define TVP3026_READ_INDEX_REG(index, data) \
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{ \
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TVP3026_SET_INDEX_REG(index); \
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data = VideoPortReadRegisterUlong(__TVP3026_INDEX_DATA) & 0xff; \
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TVP3026_DELAY; \
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ADbgpf(("0x%X <-- *(0x%X)\n", data, __TVP3026_INDEX_DATA)); \
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}
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// macros to write a given RGB triplet into cursors 0, 1 and 2
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#define TVP3026_SET_CURSOR_COLOR0(red, green, blue) \
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{ \
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VideoPortWriteRegisterUlong(__TVP3026_CUR_WR_ADDR, (ULONG)(TVP3026_CURSOR_COLOR0)); \
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TVP3026_DELAY; \
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VideoPortWriteRegisterUlong(__TVP3026_CUR_DATA, (ULONG)(red)); \
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TVP3026_DELAY; \
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VideoPortWriteRegisterUlong(__TVP3026_CUR_DATA, (ULONG)(green)); \
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TVP3026_DELAY; \
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VideoPortWriteRegisterUlong(__TVP3026_CUR_DATA, (ULONG)(blue)); \
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TVP3026_DELAY; \
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}
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#define TVP3026_SET_CURSOR_COLOR1(red, green, blue) \
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{ \
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VideoPortWriteRegisterUlong(__TVP3026_CUR_WR_ADDR, (ULONG)(TVP3026_CURSOR_COLOR1)); \
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TVP3026_DELAY; \
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VideoPortWriteRegisterUlong(__TVP3026_CUR_DATA, (ULONG)(red)); \
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TVP3026_DELAY; \
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VideoPortWriteRegisterUlong(__TVP3026_CUR_DATA, (ULONG)(green)); \
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TVP3026_DELAY; \
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VideoPortWriteRegisterUlong(__TVP3026_CUR_DATA, (ULONG)(blue)); \
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TVP3026_DELAY; \
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}
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#define TVP3026_SET_CURSOR_COLOR2(red, green, blue) \
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{ \
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VideoPortWriteRegisterUlong(__TVP3026_CUR_WR_ADDR, (ULONG)(TVP3026_CURSOR_COLOR2)); \
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TVP3026_DELAY; \
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VideoPortWriteRegisterUlong(__TVP3026_CUR_DATA, (ULONG)(red)); \
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TVP3026_DELAY; \
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VideoPortWriteRegisterUlong(__TVP3026_CUR_DATA, (ULONG)(green)); \
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TVP3026_DELAY; \
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VideoPortWriteRegisterUlong(__TVP3026_CUR_DATA, (ULONG)(blue)); \
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TVP3026_DELAY; \
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}
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#define TVP3026_SET_OVERSCAN_COLOR(red, green, blue) \
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{ \
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VideoPortWriteRegisterUlong(__TVP3026_OVRC_WR_ADDR, (ULONG)(TVP3026_OVERSCAN_COLOR)); \
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TVP3026_DELAY; \
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VideoPortWriteRegisterUlong(__TVP3026_OVRC_DATA, (ULONG)(red)); \
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TVP3026_DELAY; \
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VideoPortWriteRegisterUlong(__TVP3026_OVRC_DATA, (ULONG)(green)); \
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TVP3026_DELAY; \
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VideoPortWriteRegisterUlong(__TVP3026_OVRC_DATA, (ULONG)(blue)); \
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TVP3026_DELAY; \
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}
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// macros to load a given RGB triple into the TVP3026 palette. Send the starting
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// index and then send RGB triples. Auto-increment is turned on.
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// Use TVP3026_PALETTE_START and multiple TVP3026_LOAD_PALETTE calls to load
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// a contiguous set of entries. Use TVP3026_LOAD_PALETTE_INDEX to load a set
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// of sparse entries.
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//
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#define TVP3026_PALETTE_START_WR(index) \
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{ \
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VideoPortWriteRegisterUlong(__TVP3026_PAL_WR_ADDR, (ULONG)(index)); \
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TVP3026_DELAY; \
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}
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#define TVP3026_PALETTE_START_RD(index) \
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{ \
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VideoPortWriteRegisterUlong(__TVP3026_PAL_RD_ADDR, (ULONG)(index)); \
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TVP3026_DELAY; \
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}
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#define TVP3026_LOAD_PALETTE(red, green, blue) \
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{ \
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VideoPortWriteRegisterUlong(__TVP3026_PAL_DATA, (ULONG)(red)); \
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TVP3026_DELAY; \
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VideoPortWriteRegisterUlong(__TVP3026_PAL_DATA, (ULONG)(green)); \
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TVP3026_DELAY; \
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VideoPortWriteRegisterUlong(__TVP3026_PAL_DATA, (ULONG)(blue)); \
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TVP3026_DELAY; \
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}
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#define TVP3026_LOAD_PALETTE_INDEX(index, red, green, blue) \
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{ \
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VideoPortWriteRegisterUlong(__TVP3026_PAL_WR_ADDR, (ULONG)(index)); \
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TVP3026_DELAY; \
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VideoPortWriteRegisterUlong(__TVP3026_PAL_DATA, (ULONG)(red)); \
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TVP3026_DELAY; \
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VideoPortWriteRegisterUlong(__TVP3026_PAL_DATA, (ULONG)(green)); \
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TVP3026_DELAY; \
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VideoPortWriteRegisterUlong(__TVP3026_PAL_DATA, (ULONG)(blue)); \
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TVP3026_DELAY; \
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}
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// macro to read back a given RGB triple from the TVP3026 palette. Use after
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// a call to TVP3026_PALETTE_START_RD
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//
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#define TVP3026_READ_PALETTE(red, green, blue) \
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{ \
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red = VideoPortReadRegisterUlong(__TVP3026_PAL_DATA) & 0xff; \
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TVP3026_DELAY; \
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green = VideoPortReadRegisterUlong(__TVP3026_PAL_DATA) & 0xff; \
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TVP3026_DELAY; \
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blue = VideoPortReadRegisterUlong(__TVP3026_PAL_DATA) & 0xff; \
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TVP3026_DELAY; \
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}
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// macros to set/get the pixel read mask. The mask is 8 bits wide and gets
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// replicated across all bytes that make up a pixel.
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//
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#define TVP3026_SET_PIXEL_READMASK(mask) \
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{ \
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VideoPortWriteRegisterUlong(__TVP3026_PIXEL_MASK, (ULONG)(mask)); \
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TVP3026_DELAY; \
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}
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#define TVP3026_READ_PIXEL_READMASK(mask) \
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{ \
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mask = VideoPortReadRegisterUlong(__TVP3026_PIXEL_MASK) & 0xff; \
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}
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// macros to load values into the cursor array
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//
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#define TVP3026_CURSOR_ARRAY_START(offset) \
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{ \
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volatile LONG __temp; \
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TVP3026_READ_INDEX_REG(__TVP3026_CURSOR_CONTROL, __temp); \
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__temp &= ~TVP3026_CURSOR_RAM_MASK ; \
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__temp |= TVP3026_CURSOR_RAM_ADDRESS((offset)>> 8) ; \
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TVP3026_WRITE_INDEX_REG(__TVP3026_CURSOR_CONTROL, __temp); \
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VideoPortWriteRegisterUlong(__TVP3026_CUR_RAM_WR_ADDR, (ULONG)((offset)& 0xff)); \
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TVP3026_DELAY; \
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}
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#define TVP3026_LOAD_CURSOR_ARRAY(data) \
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{ \
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VideoPortWriteRegisterUlong(__TVP3026_CUR_RAM_DATA, (ULONG)(data)); \
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TVP3026_DELAY; \
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}
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#define TVP3026_READ_CURSOR_ARRAY(data) \
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{ \
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data = VideoPortReadRegisterUlong(__TVP3026_CUR_RAM_DATA) & 0xff; \
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TVP3026_DELAY; \
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}
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#define TVP3026_LOAD_CURSOR_CTRL(data) \
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{ \
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VideoPortWriteRegisterUlong(__TVP3026_CUR_CTL, (ULONG)(data)); \
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TVP3026_DELAY; \
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}
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// macro to move the cursor
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//
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#define TVP3026_MOVE_CURSOR(x, y) \
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{ \
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VideoPortWriteRegisterUlong(__TVP3026_CUR_X_LSB, (ULONG)((x) & 0xff)); \
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TVP3026_DELAY; \
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VideoPortWriteRegisterUlong(__TVP3026_CUR_X_MSB, (ULONG)((x) >> 8)); \
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TVP3026_DELAY; \
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VideoPortWriteRegisterUlong(__TVP3026_CUR_Y_LSB, (ULONG)((y) & 0xff)); \
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TVP3026_DELAY; \
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VideoPortWriteRegisterUlong(__TVP3026_CUR_Y_MSB, (ULONG)((y) >> 8)); \
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TVP3026_DELAY; \
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}
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// macro to change the cursor hotspot
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//
|
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#define TVP3026_CURSOR_HOTSPOT(x, y) \
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{ \
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TVP3026_DELAY; \
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}
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#define TVP3026_IS_FOUND(bFound) \
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{\
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volatile LONG __revLevel; \
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volatile LONG __productID; \
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volatile LONG __oldValue; \
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__oldValue = VideoPortReadRegisterUlong(__TVP3026_INDEX_ADDR);\
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TVP3026_DELAY; \
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TVP3026_READ_INDEX_REG (__TVP3026_SILICON_REVISION, __revLevel);\
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TVP3026_READ_INDEX_REG (__TVP3026_CHIP_ID, __productID); \
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bFound = ( (__revLevel >= TVP3026_REVISION_LEVEL) && \
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(__productID == TVP3026_ID_CODE)) ? TRUE : FALSE ; \
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VideoPortWriteRegisterUlong(__TVP3026_INDEX_ADDR, __oldValue ); \
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TVP3026_DELAY; \
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}
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