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304 lines
11 KiB
304 lines
11 KiB
title "Cirrus Logic ASM routines"
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;
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;ONE_64K_BANK equ 1
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TWO_32K_BANKS equ 1
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;++
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;
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; Copyright (c) 1992 Microsoft Corporation
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;
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; Module Name:
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;
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; vgahard.asm
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;
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; Abstract:
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;
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; This module implements the banding code for the Cirrus Logic 6410,6420
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; and 542x VGA's.
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;
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; Environment:
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;
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; Kernel mode only.
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;
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; Revision History:
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;
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;
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;--
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.386p
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.xlist
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include callconv.inc
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.list
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;----------------------------------------------------------------------------
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;
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; Cirrus Logic banking control ports.
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;
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GRAPHICS_ADDRESS_PORT equ 03ceh ;banking control here
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CL6420_BANKING_INDEX_PORT_A equ 0eh ;banking index register A is GR0E
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CL6420_BANKING_INDEX_PORT_B equ 0fh ;banking index register B is GR0F
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CL542x_BANKING_INDEX_PORT_A equ 09h ;banking index register A is GR09
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CL542x_BANKING_INDEX_PORT_B equ 0ah ;banking index register B is GR0A
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SEQ_ADDRESS_PORT equ 03C4h ;Sequencer Address register
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IND_MEMORY_MODE equ 04h ;Memory Mode reg. index in Sequencer
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CHAIN4_MASK equ 08h ;Chain4 bit in Memory Mode register
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;----------------------------------------------------------------------------
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;_TEXT SEGMENT DWORD USE32 PUBLIC 'CODE'
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; ASSUME CS:FLAT, DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING
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_TEXT SEGMENT DWORD PUBLIC 'CODE'
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ASSUME DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING
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;
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; Bank switching code. This is a 1-64K-read/1-64K-write bank adapter
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; (VideoBanked1R1W).
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;
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; Input:
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; EAX = desired read bank mapping
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; EDX = desired write bank mapping
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;
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; Note: values must be correct, with no stray bits set; no error
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; checking is performed.
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;
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public _CL64xxBankSwitchStart
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public _CL64xxBankSwitchEnd
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public _CL64xxPlanarHCBankSwitchStart
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public _CL64xxPlanarHCBankSwitchEnd
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public _CL64xxEnablePlanarHCStart
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public _CL64xxEnablePlanarHCEnd
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public _CL64xxDisablePlanarHCStart
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public _CL64xxDisablePlanarHCEnd
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public _CL542xBankSwitchStart
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public _CL542xBankSwitchEnd
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public _CL542xPlanarHCBankSwitchStart
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public _CL542xPlanarHCBankSwitchEnd
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public _CL542xEnablePlanarHCStart
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public _CL542xEnablePlanarHCEnd
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public _CL542xDisablePlanarHCStart
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public _CL542xDisablePlanarHCEnd
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public _CL543xBankSwitchStart
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public _CL543xBankSwitchEnd
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public _CL543xPlanarHCBankSwitchStart
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public _CL543xPlanarHCBankSwitchEnd
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align 4
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;----------------------------------------------------------------------------
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_CL64xxBankSwitchStart proc ;start of bank switch code
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_CL64xxPlanarHCBankSwitchStart: ;start of planar HC bank switch code,
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; which is the same code as normal
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; bank switching
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shl eax,3 ;shift them to bits 7-4
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shl edx,3 ;shift them to bits 7-4
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;!!!! NOTE: The October 1992 release NT VGA driver assumes that the Graphics
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; index is not changed by the bank switch code. We save it on the
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; stack (and save the write bank value in the high order of edx)
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; and restore it at the end of the routine. If the NT VGA driver
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; changes so that it is the index need not be preserved, this code
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; could be simplified (and speeded up!)
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rol edx,16 ; save write value
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mov ah,al
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mov dx,GRAPHICS_ADDRESS_PORT ;banking control port
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in al,dx ; save graphics index
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push eax
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mov al,CL6420_BANKING_INDEX_PORT_A
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out dx,ax ;select the READ bank
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rol edx,16
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mov ah,dl
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mov al,CL6420_BANKING_INDEX_PORT_B
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mov dx,GRAPHICS_ADDRESS_PORT ;banking control port
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out dx,ax ;select the WRITE bank
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pop eax
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out dx,al
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ret
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_CL64xxBankSwitchEnd:
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_CL64xxPlanarHCBankSwitchEnd:
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align 4
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_CL64xxEnablePlanarHCStart:
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mov dx,SEQ_ADDRESS_PORT
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in al,dx
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push eax ;preserve the state of the Seq Address
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mov al,IND_MEMORY_MODE
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out dx,al ;point to the Memory Mode register
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inc edx
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in al,dx ;get the state of the Memory Mode reg
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and al,NOT CHAIN4_MASK ;turn off Chain4 to make memory planar
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out dx,al
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dec edx
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pop eax
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out dx,al ;restore the original Seq Address
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ERA1_INDEX equ 0A1h
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mov dx,GRAPHICS_ADDRESS_PORT
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in al,dx
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push eax ;preserve the Graphics Index
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mov al,ERA1_INDEX
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out dx,al ;point to ERA1
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inc edx
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in al,dx ; get ERA1
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and al,not 30h ; turn off the shift bits
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out dx,al
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dec edx
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pop eax
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out dx,al ;restore the original Graphics Index
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ret
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_CL64xxEnablePlanarHCEnd:
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align 4
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_CL64xxDisablePlanarHCStart:
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mov dx,SEQ_ADDRESS_PORT
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in al,dx
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push eax ;preserve the state of the Seq Address
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mov al,IND_MEMORY_MODE
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out dx,al ;point to the Memory Mode register
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inc edx
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in al,dx ;get the state of the Memory Mode reg
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or al,CHAIN4_MASK ;turn on Chain4 to make memory linear
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out dx,al
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dec edx
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pop eax
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out dx,al ;restore the original Seq Address
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mov dx,GRAPHICS_ADDRESS_PORT
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in al,dx
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push eax ;preserve the Graphics Index
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mov al,ERA1_INDEX
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out dx,al ;point to ERA1
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inc edx
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in al,dx ; get ERA1
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and al,not 30h
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or al,20h
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out dx,al
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dec edx
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pop eax
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out dx,al ;restore the original Graphics Index
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ret
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_CL64xxDisablePlanarHCEnd:
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_CL64xxBankSwitchStart endp
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_CL542xBankSwitchStart proc ;start of bank switch code
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_CL542xPlanarHCBankSwitchStart: ;start of planar HC bank switch code,
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; which is the same code as normal
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; bank switching
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shl eax,3 ;shift them to bits 7-4
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shl edx,3 ;shift them to bits 7-4
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;!!!! NOTE: The October 1992 release NT VGA driver assumes that the Graphics
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; index is not changed by the bank switch code. We save it on the
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; stack (and save the write bank value in the high order of edx)
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; and restore it at the end of the routine. If the NT VGA driver
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; changes so that it is the index need not be preserved, this code
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; could be simplified (and speeded up!)
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rol edx,16 ; save write value
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mov ah,al
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mov dx,GRAPHICS_ADDRESS_PORT ;banking control port
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in al,dx
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push eax
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mov al,CL542x_BANKING_INDEX_PORT_A
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out dx,ax ;select the READ bank
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rol edx,16 ; restore write value
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mov ah,dl
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mov al,CL542x_BANKING_INDEX_PORT_B
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mov dx,GRAPHICS_ADDRESS_PORT ;banking control port
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out dx,ax ;select the WRITE bank
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pop eax
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out dx,al
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ret
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_CL542xBankSwitchEnd:
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_CL542xPlanarHCBankSwitchEnd:
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align 4
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_CL542xEnablePlanarHCStart:
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mov dx,SEQ_ADDRESS_PORT
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in al,dx
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push eax ;preserve the state of the Seq Address
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mov al,IND_MEMORY_MODE
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out dx,al ;point to the Memory Mode register
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inc edx
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in al,dx ;get the state of the Memory Mode reg
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and al,NOT CHAIN4_MASK ;turn off Chain4 to make memory planar
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out dx,al
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dec edx
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pop eax
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out dx,al ;restore the original Seq Address
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ret
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_CL542xEnablePlanarHCEnd:
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align 4
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_CL542xDisablePlanarHCStart:
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mov dx,SEQ_ADDRESS_PORT
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in al,dx
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push eax ;preserve the state of the Seq Address
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mov al,IND_MEMORY_MODE
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out dx,al ;point to the Memory Mode register
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inc edx
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in al,dx ;get the state of the Memory Mode reg
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or al,CHAIN4_MASK ;turn on Chain4 to make memory linear
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out dx,al
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dec edx
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pop eax
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out dx,al ;restore the original Seq Address
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ret
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_CL542xDisablePlanarHCEnd:
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_CL542xBankSwitchStart endp
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;
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; 543x banking assumes 16k granularity to allow up to 4-meg modes
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;
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_CL543xBankSwitchStart proc ;start of bank switch code
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_CL543xPlanarHCBankSwitchStart: ;start of planar HC bank switch code,
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; which is the same code as normal
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; bank switching
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shl eax,1 ;shift them to bits 4-1
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shl edx,1 ;shift them to bits 4-1
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;!!!! NOTE: The October 1992 release NT VGA driver assumes that the Graphics
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; index is not changed by the bank switch code. We save it on the
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; stack (and save the write bank value in the high order of edx)
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; and restore it at the end of the routine. If the NT VGA driver
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; changes so that it is the index need not be preserved, this code
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; could be simplified (and speeded up!)
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rol edx,16 ; save write value
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mov ah,al
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mov dx,GRAPHICS_ADDRESS_PORT ;banking control port
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in al,dx
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push eax
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mov al,CL542x_BANKING_INDEX_PORT_A
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out dx,ax ;select the READ bank
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rol edx,16 ; restore write value
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mov ah,dl
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mov al,CL542x_BANKING_INDEX_PORT_B
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mov dx,GRAPHICS_ADDRESS_PORT ;banking control port
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out dx,ax ;select the WRITE bank
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pop eax
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out dx,al
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ret
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_CL543xBankSwitchEnd:
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_CL543xPlanarHCBankSwitchEnd:
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_CL543xBankSwitchStart endp
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_TEXT ends
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end
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