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178 lines
4.0 KiB
178 lines
4.0 KiB
/*++
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Copyright (c) 2002 Microsoft Corporation
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Module Name:
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hammernb.h
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Abstract:
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Definitions used to relocate physical memory on Hammer MP machines.
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Author:
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Forrest Foltz (forrestf) 07/18/2002
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Environment:
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Kernel mode only.
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Revision History:
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--*/
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#if !defined(_HAMMERNB_H_)
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#define _HAMMERNB_H_
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#include "pci.h"
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//
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// Structures and definitions used to manipulate the variable MTRR ranges
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//
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#define MTRR_MSR_CAPABILITIES 0x0fe
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#define MTRR_MSR_DEFAULT 0x2ff
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#define MTRR_MSR_VARIABLE_BASE 0x200
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#define MTRR_MSR_VARIABLE_MASK (MTRR_MSR_VARIABLE_BASE+1)
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#define _40_MASK (((ULONG64)1 << 41) - 1)
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typedef union _MTRR_VARIABLE_BASE {
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struct {
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ULONG64 Type:8;
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ULONG64 Reserved0:4;
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ULONG64 Base:40;
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};
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ULONG64 QuadPart;
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} MTRR_VARIABLE_BASE, *PMTRR_VARIABLE_BASE;
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typedef union _MTRR_VARIABLE_MASK {
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struct {
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ULONG64 Reserved1:11;
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ULONG64 Valid:1;
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ULONG64 Mask:40;
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};
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ULONG64 QuadPart;
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} MTRR_VARIABLE_MASK, *PMTRR_VARIABLE_MASK;
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typedef union _MTRR_CAPABILITIES {
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struct {
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ULONG64 Vcnt:8;
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ULONG64 Fix:1;
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ULONG64 Reserved:1;
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ULONG64 WC:1;
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};
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ULONG64 QuadPart;
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} MTRR_CAPABILITIES, *PMTRR_CAPABILITIES;
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//
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// Structures and definitions used to manipulate the northbridge physical
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// memory map and MMIO map
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//
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#define MSR_SYSCFG 0xc0010010
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#define MSR_TOP_MEM 0xc001001a
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#define MSR_TOP_MEM_2 0xc001001d
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#define SYSCFG_MTRRTOM2EN ((ULONG64)1 << 21)
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#define MSR_TOP_MEM_MASK (((1UI64 << (39-23+1))-1) << 23)
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//
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// Northbridge devices start here
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//
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#define NB_DEVICE_BASE 0x18
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typedef struct _AMD_NB_DRAM_MAP {
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ULONG ReadEnable : 1;
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ULONG WriteEnable : 1;
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ULONG Reserved1 : 6;
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ULONG InterleaveEnable : 3;
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ULONG Reserved2 : 5;
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ULONG Base : 16;
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ULONG DestinationNode : 3;
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ULONG Reserved3 : 5;
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ULONG InterleaveSelect : 3;
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ULONG Reserved4 : 5;
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ULONG Limit : 16;
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} AMD_NB_DRAM_MAP, *PAMD_NB_DRAM_MAP;
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typedef struct _AMD_NB_MMIO_MAP {
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ULONG ReadEnable : 1;
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ULONG WriteEnable : 1;
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ULONG CpuDisable : 1;
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ULONG Lock : 1;
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ULONG Reserved1 : 4;
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ULONG Base : 24;
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ULONG DstNode : 3;
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ULONG Reserved2 : 1;
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ULONG DstLink : 2;
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ULONG Reserved3 : 1;
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ULONG NonPosted : 1;
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ULONG Limit : 24;
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} AMD_NB_MMIO_MAP, *PAMD_NB_MMIO_MAP;
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typedef struct _AMD_NB_FUNC1_CONFIG {
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USHORT VendorID;
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USHORT DeviceID;
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USHORT Command;
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USHORT Status;
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UCHAR RevisionID;
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UCHAR ProgramInterface;
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UCHAR SubClassCode;
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UCHAR BaseClassCode;
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UCHAR Reserved1[0x34];
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AMD_NB_DRAM_MAP DRAMMap[8];
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AMD_NB_MMIO_MAP MMIOMap[8];
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} AMD_NB_FUNC1_CONFIG, *PAMD_NB_FUNC1_CONFIG;
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C_ASSERT(FIELD_OFFSET(AMD_NB_FUNC1_CONFIG,DRAMMap) == 0x40);
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C_ASSERT(FIELD_OFFSET(AMD_NB_FUNC1_CONFIG,MMIOMap) == 0x80);
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BOOLEAN
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__inline
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BlAmd64ValidateBridgeDevice (
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IN PAMD_NB_FUNC1_CONFIG NodeConfig
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)
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/*++
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Routine Description:
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This routine verifies that the supplied PCI device configuration
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represents a Hammer northbridge address map function.
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Arguments:
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NodeConfig - Supplies a pointer to the configuration data read
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from a possible Hammer northbridge address map function.
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Return Value:
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Returns TRUE if the configuration data matches that of a Hammer northbridge
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address map function, FALSE otherwise.
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--*/
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{
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if (NodeConfig->VendorID == 0x1022 &&
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NodeConfig->DeviceID == 0x1101 &&
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NodeConfig->ProgramInterface == 0x00 &&
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NodeConfig->SubClassCode == PCI_SUBCLASS_BR_HOST &&
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NodeConfig->BaseClassCode == PCI_CLASS_BRIDGE_DEV) {
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return TRUE;
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} else {
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return FALSE;
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}
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}
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#endif // _HAMMERNB_H_
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