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1017 lines
22 KiB
1017 lines
22 KiB
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/*++
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Module Name:
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flush.c
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Abstract:
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This module implements IA64 machine dependent kernel functions to flush
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the data and instruction caches and to flush I/O buffers.
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Author:
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07-Mar-1996
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Bernard Lint
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M. Jayakumar ([email protected])
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Environment:
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Kernel mode only.
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Revision History:
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--*/
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#include "ki.h"
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#include "kxia64.h"
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//
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// PROBE_VISIBILITY_PAL_SUPPORT flag is one time write (RESET) only and multiple time read
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// only flag. It is used to check to see if the processor needs PAL_SUPPORT for VISIBILITY // in prefetches. Once the check is made, this flag optimizes such that further checks are // eliminated.
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//
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ULONG ProbePalVisibilitySupport=1;
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ULONG NeedPalVisibilitySupport=1;
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extern KSPIN_LOCK KiCacheFlushLock;
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//
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// Define forward referenced prototyes.
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//
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VOID
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KiSweepDcacheTarget (
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IN PULONG SignalDone,
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IN PVOID Parameter1,
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IN PVOID Parameter2,
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IN PVOID Parameter3
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);
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VOID
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KiSweepIcacheTarget (
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IN PULONG SignalDone,
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IN PVOID Parameter1,
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IN PVOID Parameter2,
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IN PVOID Parameter3
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);
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VOID
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KiFlushIoBuffersTarget (
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IN PKIPI_CONTEXT SignalDone,
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IN PVOID Mdl,
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IN PVOID ReadOperation,
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IN PVOID DmaOperation
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);
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VOID
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KiSyncCacheTarget(
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IN PKIPI_CONTEXT SignalDone,
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IN PVOID Parameter1,
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IN PVOID Parameter2,
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IN PVOID Parameter3
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);
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ULONG_PTR
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KiSyncMC_DrainTarget(
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);
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ULONG_PTR
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KiSyncMC_Drain(
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IN BOOLEAN AllProcessors,
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IN PVOID BaseAddress,
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IN ULONG Length
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);
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ULONG_PTR
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KiSyncPrefetchVisibleTarget(
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);
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ULONG_PTR
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KiSyncPrefetchVisible (
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IN BOOLEAN AllProcessors,
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IN PVOID BaseAddress,
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IN ULONG Length
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);
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VOID
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KiSyncCacheTarget (
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IN PKIPI_CONTEXT SignalDone,
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IN PVOID Parameter1,
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IN PVOID Parameter2,
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IN PVOID Parameter3
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)
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/*++
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Routine Description:
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This function synchronizes the I-fetch pipeline. Typically this routine will be
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executed by every processor in the system in response to an IPI after the cache
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is flushed. Each processor executing RFI while leaving the IPI produces the
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serialization effect that is required after isync to make sure that further
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instruction prefetches wait till the ISYNC completes.
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Arguements:
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SignalDone Supplies a pointer to a variable that is cleared when the
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requested operation has been performed.
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Parameter1 - Parameter3 - Not used.
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Return Value:
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Nothing.
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--*/
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{
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UNREFERENCED_PARAMETER (Parameter1);
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UNREFERENCED_PARAMETER (Parameter2);
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UNREFERENCED_PARAMETER (Parameter3);
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#if !defined(NT_UP)
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__synci();
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KiIpiSignalPacketDone(SignalDone);
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#else
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UNREFERENCED_PARAMETER (SignalDone);
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#endif
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return;
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}
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VOID
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KeSweepIcache (
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IN BOOLEAN AllProcessors
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)
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/*++
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Routine Description:
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This function flushes the instruction cache on all processors that are
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currently running threads which are children of the current process or
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flushes the instruction cache on all processors in the host configuration.
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N.B. Although PowerPC maintains cache coherency across processors, we
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use the flash invalidate function (h/w) for I-Cache sweeps which doesn't
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maintain coherency so we still do the MP I-Cache flush in s/w. plj.
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Arguments:
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AllProcessors - Supplies a boolean value that determines which instruction
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caches are flushed.
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Return Value:
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None.
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--*/
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{
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#if !defined(NT_UP)
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KIRQL OldIrql;
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KAFFINITY TargetProcessors;
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#endif
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UNREFERENCED_PARAMETER (AllProcessors);
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ASSERT(KeGetCurrentIrql() <= DISPATCH_LEVEL);
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#if !defined(NT_UP)
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//
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// Acquire cache flush spinlock
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// Cache flush is not MP safe yet
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//
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KeAcquireSpinLock(&KiCacheFlushLock, &OldIrql);
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#endif
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HalSweepIcache();
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#if !defined(NT_UP)
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//
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// Compute the set of target processors and send the sweep parameters
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// to the target processors, if any, for execution.
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//
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TargetProcessors = KeActiveProcessors & PCR->NotMember;
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if (TargetProcessors != 0) {
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KiIpiSendPacket(TargetProcessors,
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KiSweepIcacheTarget,
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NULL,
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NULL,
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NULL);
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}
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//
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// Wait until all target processors have finished sweeping their
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// instruction caches.
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//
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if (TargetProcessors != 0) {
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KiIpiStallOnPacketTargets(TargetProcessors);
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}
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//
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// Lower IRQL to its previous level and return.
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//
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KeReleaseSpinLock(&KiCacheFlushLock, OldIrql);
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#endif
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return;
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}
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#undef KeSweepCurrentIcache
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VOID
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KeSweepCurrentIcache(
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)
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/*++
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Routine Description:
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This function makes the instruction cache coherent with the data
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cache. It is generally called by the debugger.
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Arguments:
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None.
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Return Value:
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None.
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Note:
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This routine only works correct if it is called on the same processor
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that made the modification to the instruction memeory
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This routine can be called at high IRQL.
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--*/
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{
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HalSweepIcache();
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}
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VOID
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KiSweepIcacheTarget (
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IN PULONG SignalDone,
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IN PVOID Parameter1,
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IN PVOID Parameter2,
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IN PVOID Parameter3
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)
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/*++
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Routine Description:
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This is the target function for sweeping the instruction cache on
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target processors.
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Arguments:
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SignalDone Supplies a pointer to a variable that is cleared when the
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requested operation has been performed.
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Parameter1 - Parameter3 - Not used.
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Return Value:
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None.
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--*/
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{
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UNREFERENCED_PARAMETER (Parameter1);
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UNREFERENCED_PARAMETER (Parameter2);
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UNREFERENCED_PARAMETER (Parameter3);
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//
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// Sweep the instruction cache on the current processor and clear
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// the sweep instruction cache packet address to signal the source
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// to continue.
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//
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#if !defined(NT_UP)
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HalSweepIcache();
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KiIpiSignalPacketDone(SignalDone);
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#else
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UNREFERENCED_PARAMETER (SignalDone);
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#endif
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return;
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}
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VOID
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KeSweepDcache (
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IN BOOLEAN AllProcessors
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)
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/*++
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Routine Description:
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This function flushes the data cache on all processors that are currently
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running threads which are children of the current process or flushes the
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data cache on all processors in the host configuration.
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N.B. PowerPC maintains cache coherency across processors however
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in this routine, the range of addresses being flushed is unknown
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so we must still broadcast the request to the other processors.
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Arguments:
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AllProcessors - Supplies a boolean value that determines which data
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caches are flushed.
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Return Value:
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None.
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--*/
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{
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#if !defined(NT_UP)
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KIRQL OldIrql;
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KAFFINITY TargetProcessors;
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#endif
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UNREFERENCED_PARAMETER (AllProcessors);
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ASSERT(KeGetCurrentIrql() <= DISPATCH_LEVEL);
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#if !defined(NT_UP)
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//
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// Acquire cache flush spinlock
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// Cache flush is not MP safe yet
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//
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KeAcquireSpinLock(&KiCacheFlushLock, &OldIrql);
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#endif
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HalSweepDcache();
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#if !defined(NT_UP)
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//
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// Compute the set of target processors and send the sweep parameters
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// to the target processors, if any, for execution.
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//
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TargetProcessors = KeActiveProcessors & PCR->NotMember;
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if (TargetProcessors != 0) {
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KiIpiSendPacket(TargetProcessors,
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KiSweepDcacheTarget,
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NULL,
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NULL,
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NULL);
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}
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//
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// Wait until all target processors have finished sweeping their
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// data caches.
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//
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if (TargetProcessors != 0) {
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KiIpiStallOnPacketTargets(TargetProcessors);
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}
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//
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// Lower IRQL to its previous level and return.
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//
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KeReleaseSpinLock(&KiCacheFlushLock, OldIrql);
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#endif
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return;
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}
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VOID
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KiSweepDcacheTarget (
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IN PULONG SignalDone,
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IN PVOID Parameter1,
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IN PVOID Parameter2,
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IN PVOID Parameter3
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)
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/*++
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Routine Description:
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This is the target function for sweeping the data cache on target
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processors.
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Arguments:
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SignalDone Supplies a pointer to a variable that is cleared when the
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requested operation has been performed.
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Parameter1 - Parameter3 - Not used.
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Return Value:
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None.
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--*/
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{
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UNREFERENCED_PARAMETER (Parameter1);
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UNREFERENCED_PARAMETER (Parameter2);
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UNREFERENCED_PARAMETER (Parameter3);
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//
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// Sweep the data cache on the current processor and clear the sweep
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// data cache packet address to signal the source to continue.
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//
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#if !defined(NT_UP)
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HalSweepDcache();
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KiIpiSignalPacketDone(SignalDone);
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#else
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UNREFERENCED_PARAMETER (SignalDone);
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#endif
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return;
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}
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ULONG_PTR
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KiSyncMC_DrainTarget(
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)
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/*++
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Routine Description:
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This is the target function for issuing PAL_MC_DRAIN to drain
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prefetches, demand references and pending fc cache line evictions on the
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target CPU it executes.
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Argument:
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None
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Return Value:
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Returns the status from the function HalCallPal
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--*/
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{
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ULONG_PTR Status;
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//
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// Call HalCallPal to drain.
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//
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Status = HalCallPal(PAL_MC_DRAIN,
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0,
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0,
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0,
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0,
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0,
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0,
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0);
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ASSERT(Status == PAL_STATUS_SUCCESS);
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return Status;
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}
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VOID
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KeSweepCacheRange (
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IN BOOLEAN AllProcessors,
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IN PVOID BaseAddress,
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IN ULONG Length
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)
|
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/*++
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Routine Description:
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This function is used to flush a range of virtual addresses from both the
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instruction and data cache on all processors in the system.
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Irrespective of the length of the range, it should not call SweepIcache
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or SweepDcache. This is because SweepDcache will only sweep D cache and
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not the I cache and Vice versa. Since the caller of KeSweepCacheRange assumes
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both the caches are being swept, one cannot call SweepIcache or SweepDcache
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in trying to optimize.
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|
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Arguments:
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AllProcessors - Not used
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BaseAddress - Supplies a pointer to the base of the range that is flushed.
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Length - Supplies the length of the range that is flushed if the base
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address is specified.
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Return Value:
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None.
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--*/
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{
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UNREFERENCED_PARAMETER (AllProcessors);
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//
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// We will not raise IRQL to synchronization level so that we can allow
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// a context switch in between Flush Cache. FC need not run in the same processor
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// throughout. It can be context switched. So no binding is done to any processor.
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//
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//
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HalSweepCacheRange(BaseAddress,Length);
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//
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// Synchronize the Instruction Prefetch pipe in the local processor.
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//
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__synci();
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__isrlz();
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//
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// Wait until all target processors have finished sweeping the their
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// data cache.
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//
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return;
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}
|
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|
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VOID
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KeSweepIcacheRange (
|
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IN BOOLEAN AllProcessors,
|
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IN PVOID BaseAddress,
|
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IN SIZE_T Length
|
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)
|
|
|
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/*++
|
|
|
|
Routine Description:
|
|
|
|
This function is used to flush a range of virtual addresses from the
|
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primary instruction cache on all processors in the host configuration.
|
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If the length of the range is greater than the size of the
|
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instruction cache, then one can call HalSweepIcache which calls
|
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SAL to flush the entire cache. Since SAL does not take care of MP
|
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flushing, HalSweepIcache has to use IPI mechanism to execute SAL
|
|
flush from each processor. We need to weight the overhead of all these
|
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versus using HalSweepIcacheRange and avoiding IPI mechanism since
|
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HalSweepIcacheRange uses fc instruction and fc instruction takes care of MP.
|
|
|
|
Arguments:
|
|
|
|
AllProcessors - Not used
|
|
|
|
BaseAddress - Supplies a pointer to the base of the range that is flushed.
|
|
|
|
Length - Supplies the length of the range that is flushed if the base
|
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address is specified.
|
|
|
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Return Value:
|
|
|
|
None.
|
|
|
|
Note: For performance reason, we may update KeSweepIcacheRange to do the following:
|
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if the range asked to sweep is very large, we may call KeSweepIcache to flush
|
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the full cache.
|
|
|
|
|
|
|
|
--*/
|
|
|
|
{
|
|
|
|
UNREFERENCED_PARAMETER (AllProcessors);
|
|
|
|
//
|
|
// We will not raise IRQL to synchronization level so that we can allow
|
|
// a context switch in between Flush Cache. FC need not run in the same processor
|
|
// throughout. It can be context switched. So no binding is done to any processor.
|
|
//
|
|
//
|
|
|
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HalSweepIcacheRange(BaseAddress,Length);
|
|
|
|
//
|
|
// Synchronize the Instruction Prefetch pipe in the local processor.
|
|
//
|
|
|
|
__synci();
|
|
__isrlz();
|
|
|
|
return;
|
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|
|
|
|
}
|
|
|
|
VOID
|
|
KeSweepCurrentIcacheRange (
|
|
IN PVOID BaseAddress,
|
|
IN SIZE_T Length
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function is used to flush a range of virtual addresses from the
|
|
primary instruction cache on the current processor.
|
|
|
|
This is used by the kernel debugger for flushing the i-cache after
|
|
modifying memory in case the instruction stream is changed.
|
|
|
|
To avoid calling SAL during phase 0 we use "fc" instead of the SAL cache
|
|
flush call.
|
|
|
|
Arguments:
|
|
|
|
BaseAddress - Supplies a pointer to the base of the range that is flushed.
|
|
|
|
Length - Supplies the length of the range that is flushed if the base
|
|
address is specified.
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
--*/
|
|
|
|
{
|
|
KIRQL OldIrql;
|
|
|
|
KeRaiseIrql(HIGH_LEVEL, &OldIrql);
|
|
|
|
HalSweepIcacheRange(BaseAddress,Length);
|
|
|
|
//
|
|
// Synchronize the Instruction Prefetch pipe in the local processor.
|
|
//
|
|
|
|
__synci();
|
|
__isrlz();
|
|
|
|
KeLowerIrql(OldIrql);
|
|
|
|
return;
|
|
}
|
|
|
|
|
|
|
|
VOID
|
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KeSweepDcacheRange (
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IN BOOLEAN AllProcessors,
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IN PVOID BaseAddress,
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IN ULONG Length
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)
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/*++
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Routine Description:
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This function is used to flush a range of virtual addresses from the
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primary data cache on all processors in the host configuration.
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If the length of the range is greater than the size of the
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data cache, then one can call HalSweepDcache which calls
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SAL to flush the entire cache. Since SAL does not take care of MP
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flushing, HalSweepDcache has to use IPI mechanism to execute SAL
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flush from each processor. We need to weight the overhead of all these
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versus using HalSweepDcacheRange and avoiding IPI mechanism since
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HalSweepDcacheRange uses fc instruction and fc instruction takes care of MP.
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Arguments:
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AllProcessors - Not used
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BaseAddress - Supplies a pointer to the base of the range that is flushed.
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Length - Supplies the length of the range that is flushed if the base
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address is specified.
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Return Value:
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None.
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Note: For performance reason, we may update KeSweepDcacheRange to do the following:
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if the range asked to sweep is very large, we may call KeSweepDcache to flush
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the full cache.
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--*/
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{
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UNREFERENCED_PARAMETER (AllProcessors);
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//
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// We will not raise IRQL to synchronization level so that we can allow
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// a context switch in between Flush Cache. FC need not run in the same processor
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// throughout. It can be context switched. So no binding is done to any processor.
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//
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//
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HalSweepDcacheRange(BaseAddress,Length);
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//
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// Synchronize the Instruction Prefetch pipe in the local processor.
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//
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__synci();
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__isrlz();
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return;
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}
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ULONG_PTR
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KiSyncMC_Drain (
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IN BOOLEAN AllProcessors,
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IN PVOID BaseAddress,
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IN ULONG Length
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)
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/*++
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Routine Description:
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KiSyncMC_Drain issues PAL_MC_DRAIN to drain either prefetches, demand references
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or pending fc cache line evictions to all the processors in the system.
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DrainTypePointer points to the variable, DrainType, which determines the type of
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drain to be performed. This is typically used when changing the memory attribute
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from WB to UC.
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Arguments:
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AllProcessors - All processors in the system.
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BaseAddress - Supplies a pointer to the base of the range that is to be drained.
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Length - Supplies the length of the range that is drained for the base
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address specified.
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Return Value:
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Note: This is used when changing attributes of WB pages to UC pages.
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--*/
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{
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ULONG_PTR Status;
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UNREFERENCED_PARAMETER (AllProcessors);
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UNREFERENCED_PARAMETER (BaseAddress);
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UNREFERENCED_PARAMETER (Length);
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//
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// KeIpiGenericCall returns ULONG_PTR as the function value of the specified function
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//
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Status = (KeIpiGenericCall (
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(PKIPI_BROADCAST_WORKER)KiSyncMC_DrainTarget,
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(ULONG_PTR)NULL)
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);
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ASSERT(Status == PAL_STATUS_SUCCESS);
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return Status;
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}
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ULONG_PTR
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KiSyncPrefetchVisibleTarget(
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)
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/*++
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Routine Description:
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This is the target function for issuing PAL_PREFETCH VISIBILITY
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on the target CPU it executes.
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Argument:
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Not used.
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Return Value:
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Returns the status from the function HalCallPal
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--*/
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{
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ULONG_PTR Status;
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//
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// Call HalCallPal to drain.
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//
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Status = HalCallPal(PAL_PREFETCH_VISIBILITY,
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0,
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0,
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0,
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0,
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0,
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0,
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0);
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ASSERT(Status != PAL_STATUS_ERROR);
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return Status;
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}
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ULONG_PTR
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KiSyncPrefetchVisible (
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IN BOOLEAN AllProcessors,
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IN PVOID BaseAddress,
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IN ULONG Length
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)
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/*++
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Routine Description:
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KiSyncPrefetchVisible issues PAL_PREFETCH_VISIBILITY to cause the processor to make
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all pending prefetches visible to subsequent fc instructions; or does nothing, on
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processor implementations which does not require PAL support for disabling prefetch
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in the architectural sequence. On processors that require PAL support for this
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sequence, the actions performed by this procedure may include any or all
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of the following (or none, as long as the processor guarantees that
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prefetches that were issued prior to this call are not resident in the
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processor's caches after the architected sequence is complete.
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This is typically used when changing the memory attribute from WB to UC.
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Arguments:
|
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AllProcessors - All processors in the system.
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BaseAddress - Supplies a pointer to the base of the range that is to be drained.
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Length - Supplies the length of the range that is drained for the base
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address specified.
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Return Value:
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Status of the PAL CALL
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0 Success
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1 Call not needed
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-3 Error returned
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Note: This is used when changing attributes of WB pages to UC pages.
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--*/
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{
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ULONG_PTR Status;
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UNREFERENCED_PARAMETER (AllProcessors);
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UNREFERENCED_PARAMETER (BaseAddress);
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UNREFERENCED_PARAMETER (Length);
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switch (ProbePalVisibilitySupport) {
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case 0:
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if (NeedPalVisibilitySupport == 0)
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Status = PAL_STATUS_SUPPORT_NOT_NEEDED;
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else {
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Status = (KeIpiGenericCall (
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(PKIPI_BROADCAST_WORKER)KiSyncPrefetchVisibleTarget,
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(ULONG_PTR)NULL)
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);
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}
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break;
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case 1:
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Status = KiSyncPrefetchVisibleTarget();
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ASSERT(Status != PAL_STATUS_ERROR);
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ProbePalVisibilitySupport = 0;
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if (Status == PAL_STATUS_SUPPORT_NOT_NEEDED) {
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NeedPalVisibilitySupport = 0;
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Status = PAL_STATUS_SUPPORT_NOT_NEEDED;
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} else {
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Status = (KeIpiGenericCall (
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(PKIPI_BROADCAST_WORKER)KiSyncPrefetchVisibleTarget,
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(ULONG_PTR)NULL)
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);
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}
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break;
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default:
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Status = (ULONG_PTR) PAL_STATUS_ERROR;
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break;
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}
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ASSERT(Status != PAL_STATUS_ERROR);
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return Status;
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}
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VOID
|
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KeSweepCacheRangeWithDrain (
|
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IN BOOLEAN AllProcessors,
|
|
IN PVOID BaseAddress,
|
|
IN ULONG Length
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function is used to drain prefetches,demand references followed by flushing
|
|
the cache followed by draining pending fc cache line evictions to a specified range
|
|
address in all processors in the system.
|
|
|
|
|
|
Arguments:
|
|
|
|
AllProcessors - All processors in the system.
|
|
|
|
BaseAddress - Supplies a pointer to the base of the range that is flushed and drained.
|
|
|
|
Length - Supplies the length of the range that is flushed and drained for the base
|
|
address is specified.
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
Note: This is used when changing attributes of WB pages to UC pages.
|
|
|
|
--*/
|
|
|
|
{
|
|
ULONG_PTR Status;
|
|
|
|
Status = KiSyncPrefetchVisible(
|
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AllProcessors,
|
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BaseAddress,
|
|
Length
|
|
);
|
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|
|
ASSERT(Status != PAL_STATUS_ERROR);
|
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|
|
KeSweepCacheRange (
|
|
AllProcessors,
|
|
BaseAddress,
|
|
Length
|
|
);
|
|
|
|
Status = KiSyncMC_Drain (
|
|
AllProcessors,
|
|
BaseAddress,
|
|
Length
|
|
);
|
|
|
|
ASSERT(Status == PAL_STATUS_SUCCESS);
|
|
|
|
return;
|
|
|
|
|
|
}
|
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|