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681 lines
23 KiB
681 lines
23 KiB
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#if !defined(SPD_CARD_H)
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#define SPD_CARD_H
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#if DBG
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#define SERDIAG1 ((ULONG)0x00000001)
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#define SERDIAG2 ((ULONG)0x00000002)
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#define SERDIAG3 ((ULONG)0x00000004)
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#define SERDIAG4 ((ULONG)0x00000008)
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#define SERDIAG5 ((ULONG)0x00000010)
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#define SERIRPPATH ((ULONG)0x00000020)
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#define SERWARNING ((ULONG)0x00000100)
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#define SERINFO ((ULONG)0x00000200)
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#define SERFLOW ((ULONG)0x00000400)
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#define SERERRORS ((ULONG)0x00000800)
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#define SERBUGCHECK ((ULONG)0x00001000)
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// -- OXSER Diag 3 --
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// Additional debug levels
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#define PCIINFO ((ULONG)0x00002000)
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#define XTLINFO ((ULONG)0x00004000)
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#define ISRINFO ((ULONG)0x00008000)
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#define TXINFO ((ULONG)0x00010000)
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#define RXINFO ((ULONG)0x00020000)
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#define LSINFO ((ULONG)0x00040000)
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#define MSINFO ((ULONG)0x00080000)
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#define KICKINFO ((ULONG)0x00100000)
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#define FIFOINFO ((ULONG)0x00200000)
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#define CLOSE_STATS ((ULONG)0x00400000)
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#define BAUDINFO ((ULONG)0x00800000)
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extern ULONG SpxDebugLevel;
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#define SerialDump(LEVEL,STRING) \
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do { \
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ULONG _level = (LEVEL); \
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if (SpxDebugLevel & _level) { \
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DbgPrint STRING; \
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} \
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if (_level == SERBUGCHECK) { \
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ASSERT(FALSE); \
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} \
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} while (0)
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#else
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#define SerialDump(LEVEL,STRING) do {NOTHING;} while (0)
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#endif
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// For the above directory, the serial port will
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// use the following name as the suffix of the serial
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// ports for that directory. It will also append
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// a number onto the end of the name. That number
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// will start at 1.
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#define DEFAULT_SERIAL_NAME L"COM"
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// This define gives the default NT name for
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// for serial ports detected by the firmware.
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// This name will be appended to Device prefix
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// with a number following it. The number is
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// incremented each time encounter a serial
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// port detected by the firmware. Note that
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// on a system with multiple busses, this means
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// that the first port on a bus is not necessarily
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// \Device\Serial0.
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//
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#define DEFAULT_NT_SUFFIX L"Serial"
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// Default xon/xoff characters.
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#define SERIAL_DEF_XON 0x11
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#define SERIAL_DEF_XOFF 0x13
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// Reasons that recption may be held up.
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#define SERIAL_RX_DTR ((ULONG)0x01)
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#define SERIAL_RX_XOFF ((ULONG)0x02)
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#define SERIAL_RX_RTS ((ULONG)0x04)
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#define SERIAL_RX_DSR ((ULONG)0x08)
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// Reasons that transmission may be held up.
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#define SERIAL_TX_CTS ((ULONG)0x01)
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#define SERIAL_TX_DSR ((ULONG)0x02)
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#define SERIAL_TX_DCD ((ULONG)0x04)
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#define SERIAL_TX_XOFF ((ULONG)0x08)
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#define SERIAL_TX_BREAK ((ULONG)0x10)
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//////////////////////////////////////////////////////////////////////////////////////////
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// SPEED Port Device Extenstion.
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// Information specific to SPEED Ports.
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//////////////////////////////////////////////////////////////////////////////////////////
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typedef struct _PORT_DEVICE_EXTENSION
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{
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COMMON_PORT_DEVICE_EXTENSION; // Common Card Device Extension
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ULONG SysPortNumber; // System port number
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// Timing variables...
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LARGE_INTEGER IntervalTime; // Read interval time
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LARGE_INTEGER ShortIntervalAmount; // Short tread interval time
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LARGE_INTEGER LongIntervalAmount; // Long read interval time
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LARGE_INTEGER CutOverAmount; // Used to determine short/long interval time
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LARGE_INTEGER LastReadTime; // System time of last read
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PLARGE_INTEGER IntervalTimeToUse; // Interval timing delta time delay
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// Queued IRP lists...
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LIST_ENTRY ReadQueue; // Head of read IRP list, protected by cancel spinlock
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LIST_ENTRY WriteQueue; // Head of write IRP list, protected by cancel spinlock
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LIST_ENTRY MaskQueue; // Head of set/wait mask IRP list, protected by cancel spinlock
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LIST_ENTRY PurgeQueue; // Head of purge IRP list, protected by cancel spinlock
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// Current IRPs...
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PIRP CurrentReadIrp; // Pointer to current read IRP
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PIRP CurrentWriteIrp; // Pointer to current write IRP
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PIRP CurrentMaskIrp; // Pointer to current mask IRP
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PIRP CurrentPurgeIrp; // Pointer to current purge IRP
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PIRP CurrentWaitIrp; // Pointer to current wait IRP
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PIRP CurrentImmediateIrp; // Pointer to current send immediate IRP
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PIRP CurrentXoffIrp; // Pointer to current XOFF_COUNTER IRP
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// Write IRP variables...
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ULONG WriteLength; // Write character count in current write IRP
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PUCHAR WriteCurrentChar; // Pointer to write character in current write IRP
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// Read IRP variables...
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PUCHAR InterruptReadBuffer; // Read buffer current pointer in current read IRP
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PUCHAR ReadBufferBase; // Read buffer base pointer in current read IRP
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ULONG CharsInInterruptBuffer; // Characters read into read buffer
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// KSPIN_LOCK BufferLock; // Spinlock protecting "CharsInInterruptBuffer"
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PUCHAR CurrentCharSlot; // Pointer at space to store new read data
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PUCHAR LastCharSlot; // Last valid position in read buffer
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PUCHAR FirstReadableChar; // First read character in read buffer
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ULONG BufferSize; // Read buffer size
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ULONG BufferSizePt8; // 80% read buffer size
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ULONG NumberNeededForRead; // Number of characters requested in current read IRP
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// Mask IRP variables...
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ULONG IsrWaitMask; // Wait mask in current wait IRP
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ULONG HistoryMask; // History of masked events
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ULONG *IrpMaskLocation; // Pointer to mask location
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// Serial port configuration...
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// ULONG CurrentBaud; // Current baud rate
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ULONG SupportedBauds; // Bitmask defining supported baud rates
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SERIAL_HANDFLOW HandFlow; // Current handshaking and flow control settings
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UCHAR LineControl; // Current parity,databits,stopbits
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SERIAL_CHARS SpecialChars; // Current Special error/replacement characters
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SERIAL_TIMEOUTS Timeouts; // Read and write timeouts
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UCHAR ValidDataMask; // Read data mask
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UCHAR EscapeChar; // Escape character used with line/modem status strings
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// BOOLEAN InsertEscChar; // Indicates of EscapeChar should be inserted
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// Serial port status...
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LONG CountSinceXoff; // Nun chars read since XOFF counter started
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ULONG CountOfTryingToLowerRTS;// Count of processes trying to lower RTS
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BOOLEAN TransmitImmediate; // Indicates of transmit immediate is pending
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BOOLEAN EmptiedTransmit; // Indicates transmit empty
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UCHAR ImmediateChar; // Character to be transmitted immediately
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ULONG TXHolding; // Reasons for transmit blocked
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ULONG RXHolding; // Reasons for receive blocked
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ULONG ErrorWord; // Error conditions
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ULONG TotalCharsQueued; // Total number of queued characters in all write IRPs
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LONG CountOnLastRead; // Number of chars read last time interval timer DPC ran
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ULONG ReadByIsr; // Number of characters read during ISR
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KSPIN_LOCK ControlLock; // Used to protect certain fields
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// Deferred procedure calls...
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KDPC CompleteWriteDpc; // DPC used to complete write IRPs
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KDPC CompleteReadDpc; // DPC used to complete read IRPs
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KDPC TotalReadTimeoutDpc; // DPC used to handle read total timeout
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KDPC IntervalReadTimeoutDpc; // DPC used to handle read interval timeout
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KDPC TotalWriteTimeoutDpc; // DPC used to handle write total timeout
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KDPC CommErrorDpc; // DPC used to handle cancel on error
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KDPC CommWaitDpc; // DPC used to handle waking IRPs waiting on an event
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KDPC CompleteImmediateDpc; // DPC used to handle transmitting an immediate character
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KDPC TotalImmediateTimeoutDpc; // DPC used to handle immediate char timeout
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KDPC XoffCountTimeoutDpc; // DPC used to handle XOFF_COUNT timeout
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KDPC XoffCountCompleteDpc; // DPC used to complete XOFF_COUNT IRP
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KDPC StartTimerLowerRTSDpc; // DPC used to check for RTS lowering
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KDPC PerhapsLowerRTSDpc; // DPC used to check for RTS lowering
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// Timers...
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KTIMER ReadRequestTotalTimer; // Timer used to handle total read request timeout
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KTIMER ReadRequestIntervalTimer; // Timer used to handle interval read timeout
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KTIMER WriteRequestTotalTimer; // Timer used to handle total write request timeout
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KTIMER ImmediateTotalTimer; // Timer used to handle send immediate timeout
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KTIMER XoffCountTimer; // Timer used to handle XOFF_COUNT timeout
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KTIMER LowerRTSTimer; // Timer used to handle lower RTS timing
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PUART_LIB pUartLib; // Uart library finctions.
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PUART_OBJECT pUart;
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UART_CONFIG UartConfig;
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BOOLEAN DTR_Set;
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BOOLEAN RTS_Set;
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SET_BUFFER_SIZES BufferSizes;
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DWORD MaxTxFIFOSize; // Max Tx FIFO Size.
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DWORD MaxRxFIFOSize; // Max Rx FIFO Size.
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DWORD TxFIFOSize; // Tx FIFO Size.
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DWORD RxFIFOSize; // Rx FIFO Size.
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DWORD TxFIFOTrigLevel; // Tx FIFO Trigger Level.
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DWORD RxFIFOTrigLevel; // Rx FIFO Trigger Level.
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DWORD HiFlowCtrlThreshold; // High Flow Control Threshold.
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DWORD LoFlowCtrlThreshold; // Low Flow Control Threshold.
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#ifdef WMI_SUPPORT
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SPX_SPEED_WMI_FIFO_PROP SpeedWmiFifoProp;
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#endif
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BYTE ImmediateIndex;
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// This holds the isr that should be called from our own
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// dispatching isr for "cards" that are trying to share the
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// same interrupt.
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PKSERVICE_ROUTINE TopLevelOurIsr;
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// This holds the context that should be used when we
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// call the above service routine.
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PVOID TopLevelOurIsrContext;
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// This links together all of the different "cards" that are
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// trying to share the same interrupt of a non-mca machine.
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LIST_ENTRY TopLevelSharers;
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// This circular doubly linked list links together all
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// devices that are using the same interrupt object.
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// NOTE: This does not mean that they are using the
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// same interrupt "dispatching" routine.
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LIST_ENTRY CommonInterruptObject;
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// For reporting resource usage, we keep around the physical
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// address we got from the registry.
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PHYSICAL_ADDRESS OriginalController;
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// For reporting resource usage, we keep around the physical
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// address we got from the registry.
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PHYSICAL_ADDRESS OriginalInterruptStatus;
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// This points to the object directory that we will place
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// a symbolic link to our device name.
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UNICODE_STRING ObjectDirectory;
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// This points to the device name for this device
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// sans device prefix.
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UNICODE_STRING NtNameForPort;
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// After initialization of the driver is complete, this
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// will either be NULL or point to the routine that the
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// kernel will call when an interrupt occurs.
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// If the pointer is null then this is part of a list
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// of ports that are sharing an interrupt and this isn't
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// the first port that we configured for this interrupt.
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// If the pointer is non-null then this routine has some
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// kind of structure that will "eventually" get us into
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// the real serial isr with a pointer to this device extension.
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// NOTE: On an MCA bus (except for multiport cards) this
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// is always a pointer to the "real" serial isr.
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PKSERVICE_ROUTINE OurIsr;
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// This will generally point right to this device extension.
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//
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// However, when the port that this device extension is
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// "managing" was the first port initialized on a chain
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// of ports that were trying to share an interrupt, this
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// will point to a structure that will enable dispatching
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// to any port on the chain of sharers of this interrupt.
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PVOID OurIsrContext;
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// The base address for the set of device registers
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// of the serial port.
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PUCHAR Controller;
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// The base address for interrupt status register.
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// This is only defined in the root extension.
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PUCHAR InterruptStatus;
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// Points to the interrupt object for used by this device.
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PKINTERRUPT Interrupt;
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// Pointer to the lock variable returned for this extension when
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// locking down the driver
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PVOID LockPtr;
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// This value holds the span (in units of bytes) of the register
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// set controlling this port. This is constant over the life
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// of the port.
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ULONG SpanOfController;
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// This value holds the span (in units of bytes) of the interrupt
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// status register associated with this port. This is constant
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// over the life of the port.
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ULONG SpanOfInterruptStatus;
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// Hold the clock rate input to the serial part.
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ULONG ClockRate;
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// The number of characters to push out if a fifo is present.
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ULONG TxFifoAmount;
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// Set to indicate that it is ok to share interrupts within the device.
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ULONG PermitShare;
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// Set at intialization to indicate that on the current
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// architecture we need to unmap the base register address
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// when we unload the driver.
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BOOLEAN UnMapRegisters;
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// Set at intialization to indicate that on the current
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// architecture we need to unmap the interrupt status address
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// when we unload the driver.
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BOOLEAN UnMapStatus;
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// This is only accessed at interrupt level. It keeps track
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// of whether the holding register is empty.
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BOOLEAN HoldingEmpty;
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// This simply indicates that the port associated with this
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// extension is part of a multiport card.
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BOOLEAN PortOnAMultiportCard;
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// We keep the following values around so that we can connect
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// to the interrupt and report resources after the configuration
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// record is gone.
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ULONG Vector;
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KIRQL Irql;
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ULONG OriginalVector;
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ULONG OriginalIrql;
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KINTERRUPT_MODE InterruptMode;
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KAFFINITY ProcessorAffinity;
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ULONG AddressSpace;
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ULONG BusNumber;
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INTERFACE_TYPE InterfaceType;
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// These two booleans are used to indicate to the isr transmit
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// code that it should send the xon or xoff character. They are
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// only accessed at open and at interrupt level.
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BOOLEAN SendXonChar;
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BOOLEAN SendXoffChar;
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// This boolean will be true if a 16550 is present *and* enabled.
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BOOLEAN FifoPresent;
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// -- OXSER Mod 12 --
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// The Jensen does not interest us and all references to it have been
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// removed
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// This denotes that this particular port is an on the motherboard
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// port for the Jensen hardware. On these ports the OUT2 bit
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// which is used to enable/disable interrupts is always hight.
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// BOOLEAN Jensen;
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// This is the water mark that the rxfifo should be
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// set to when the fifo is turned on. This is not the actual
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// value, but the encoded value that goes into the register.
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UCHAR RxFifoTrigger;
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// Says whether this device can share interrupts with devices
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// other than serial devices.
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BOOLEAN InterruptShareable;
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} PORT_DEVICE_EXTENSION, *PPORT_DEVICE_EXTENSION;
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// PORT_DEVICE_EXTENSION.CountOnLastRead definitions...
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#define SERIAL_COMPLETE_READ_CANCEL ((LONG)-1)
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#define SERIAL_COMPLETE_READ_TOTAL ((LONG)-2)
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#define SERIAL_COMPLETE_READ_COMPLETE ((LONG)-3)
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// PORT_DEVICE_EXTENSION.LineControl definitions...
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#define SERIAL_5_DATA ((UCHAR)0x00)
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#define SERIAL_6_DATA ((UCHAR)0x01)
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#define SERIAL_7_DATA ((UCHAR)0x02)
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#define SERIAL_8_DATA ((UCHAR)0x03)
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#define SERIAL_DATA_MASK ((UCHAR)0x03)
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#define SERIAL_1_STOP ((UCHAR)0x00)
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#define SERIAL_1_5_STOP ((UCHAR)0x04) // Only valid for 5 data bits
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#define SERIAL_2_STOP ((UCHAR)0x04) // Not valid for 5 data bits
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#define SERIAL_STOP_MASK ((UCHAR)0x04)
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#define SERIAL_NONE_PARITY ((UCHAR)0x00)
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#define SERIAL_ODD_PARITY ((UCHAR)0x08)
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#define SERIAL_EVEN_PARITY ((UCHAR)0x18)
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#define SERIAL_MARK_PARITY ((UCHAR)0x28)
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#define SERIAL_SPACE_PARITY ((UCHAR)0x38)
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#define SERIAL_PARITY_MASK ((UCHAR)0x38)
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#define SERIAL_LCR_BREAK 0x40
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// PORT_DEVICE_EXTENSION.SpecialChars default xon/xoff characters...
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#define SERIAL_DEF_XON 0x11
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#define SERIAL_DEF_XOFF 0x13
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// PORT_DEVICE_EXTENSION.TXHolding definitions...
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#define SERIAL_TX_CTS ((ULONG)0x01)
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#define SERIAL_TX_DSR ((ULONG)0x02)
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#define SERIAL_TX_DCD ((ULONG)0x04)
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#define SERIAL_TX_XOFF ((ULONG)0x08)
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#define SERIAL_TX_BREAK ((ULONG)0x10)
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// PORT_DEVICE_EXTENSION.RXHolding definitions...
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#define SERIAL_RX_DTR ((ULONG)0x01)
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#define SERIAL_RX_XOFF ((ULONG)0x02)
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#define SERIAL_RX_RTS ((ULONG)0x04)
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#define SERIAL_RX_DSR ((ULONG)0x08)
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#define SERIAL_RX_FULL ((ULONG)0x10) // VIV: If Io8 Rx queue is full.
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// PORT_DEVICE_EXTENSION.LastStatus definitions...
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#define SERIAL_LSR_DR 0x01
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#define SERIAL_LSR_OE 0x02
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#define SERIAL_LSR_PE 0x04
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#define SERIAL_LSR_FE 0x08
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#define SERIAL_LSR_BI 0x10
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// 16550 Modem Control Register definitions...
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#define SERIAL_MCR_DTR 0x01
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#define SERIAL_MCR_RTS 0x02
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// 16550 Modem Status Register definitions...
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#define SERIAL_MSR_DCTS 0x01
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#define SERIAL_MSR_DDSR 0x02
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#define SERIAL_MSR_TERI 0x04
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#define SERIAL_MSR_DDCD 0x08
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#define SERIAL_MSR_CTS 0x10
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#define SERIAL_MSR_DSR 0x20
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#define SERIAL_MSR_RI 0x40
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#define SERIAL_MSR_DCD 0x80
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// These masks define the interrupts that can be enabled or disabled.
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//
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// This interrupt is used to notify that there is new incomming
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// data available. The SERIAL_RDA interrupt is enabled by this bit.
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#define SERIAL_IER_RDA 0x01
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// This interrupt is used to notify that there is space available
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// in the transmitter for another character. The SERIAL_THR
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// interrupt is enabled by this bit.
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#define SERIAL_IER_THR 0x02
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// This interrupt is used to notify that some sort of error occured
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// with the incomming data. The SERIAL_RLS interrupt is enabled by
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// this bit.
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#define SERIAL_IER_RLS 0x04
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// This interrupt is used to notify that some sort of change has
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// taken place in the modem control line. The SERIAL_MS interrupt is
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// enabled by this bit.
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#define SERIAL_IER_MS 0x08
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// These masks define the values of the interrupt identification
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// register. The low bit must be clear in the interrupt identification
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// register for any of these interrupts to be valid. The interrupts
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// are defined in priority order, with the highest value being most
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// important. See above for a description of what each interrupt
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// implies.
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#define SERIAL_IIR_RLS 0x06
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#define SERIAL_IIR_RDA 0x04
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#define SERIAL_IIR_CTI 0x0c
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#define SERIAL_IIR_THR 0x02
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#define SERIAL_IIR_MS 0x00
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// This bit mask get the value of the high two bits of the
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// interrupt id register. If this is a 16550 class chip
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// these bits will be a one if the fifo's are enbled, otherwise
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// they will always be zero.
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#define SERIAL_IIR_FIFOS_ENABLED 0xc0
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// If the low bit is logic one in the interrupt identification register
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// this implies that *NO* interrupts are pending on the device.
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#define SERIAL_IIR_NO_INTERRUPT_PENDING 0x01
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// These masks define access to the fifo control register.
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// Enabling this bit in the fifo control register will turn
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// on the fifos. If the fifos are enabled then the high two
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// bits of the interrupt id register will be set to one. Note
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// that this only occurs on a 16550 class chip. If the high
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// two bits in the interrupt id register are not one then
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// we know we have a lower model chip.
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#define SERIAL_FCR_ENABLE ((UCHAR)0x01)
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#define SERIAL_FCR_RCVR_RESET ((UCHAR)0x02)
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#define SERIAL_FCR_TXMT_RESET ((UCHAR)0x04)
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// This set of values define the high water marks (when the
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// interrupts trip) for the receive fifo.
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#define SERIAL_1_BYTE_HIGH_WATER ((UCHAR)0x00)
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#define SERIAL_4_BYTE_HIGH_WATER ((UCHAR)0x40)
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#define SERIAL_8_BYTE_HIGH_WATER ((UCHAR)0x80)
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#define SERIAL_14_BYTE_HIGH_WATER ((UCHAR)0xc0)
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// This defines the bit used to control the definition of the "first"
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// two registers for the 8250. These registers are the input/output
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// register and the interrupt enable register. When the DLAB bit is
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// enabled these registers become the least significant and most
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// significant bytes of the divisor value.
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#define SERIAL_LCR_DLAB 0x80
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// This bit is used for general purpose output.
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#define SERIAL_MCR_OUT1 0x04
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// This bit is used for general purpose output.
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#define SERIAL_MCR_OUT2 0x08
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// This bit controls the loopback testing mode of the device. Basically
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// the outputs are connected to the inputs (and vice versa).
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#define SERIAL_MCR_LOOP 0x10
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// This is the transmit holding register empty indicator. It is set
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// to indicate that the hardware is ready to accept another character
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// for transmission. This bit is cleared whenever a character is
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// written to the transmit holding register.
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#define SERIAL_LSR_THRE 0x20
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// This bit is the transmitter empty indicator. It is set whenever the
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// transmit holding buffer is empty and the transmit shift register
|
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// (a non-software accessable register that is used to actually put
|
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// the data out on the wire) is empty. Basically this means that all
|
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// data has been sent. It is cleared whenever the transmit holding or
|
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// the shift registers contain data.
|
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#define SERIAL_LSR_TEMT 0x40
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// This bit indicates that there is at least one error in the fifo.
|
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// The bit will not be turned off until there are no more errors
|
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// in the fifo.
|
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#define SERIAL_LSR_FIFOERR 0x80
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//
|
|
// This should be more than enough space to hold then
|
|
// numeric suffix of the device name.
|
|
//
|
|
#define DEVICE_NAME_DELTA 20
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//
|
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// Up to 16 Ports Per card. However for sixteen
|
|
// port cards the interrupt status register must be
|
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// the indexing kind rather then the bitmask kind.
|
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//
|
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#define SERIAL_MAX_PORTS_INDEXED (16)
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#define SERIAL_MAX_PORTS_NONINDEXED (8)
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//////////////////////////////////////////////////////////////////////////////////////////
|
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// SPEED Card Device Extenstion.
|
|
// Information specific to SPEED cards.
|
|
//////////////////////////////////////////////////////////////////////////////////////////
|
|
typedef struct _CARD_DEVICE_EXTENSION
|
|
{
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|
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COMMON_CARD_DEVICE_EXTENSION; // Common Card Device Extension
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|
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ULONG CrystalFrequency; // Frequency of onboard crystal
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|
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PHYSICAL_ADDRESS PCIConfigRegisters;
|
|
ULONG SpanOfPCIConfigRegisters;
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|
PUCHAR LocalConfigRegisters;
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PUCHAR InterruptStatus;
|
|
PPORT_DEVICE_EXTENSION Extensions[SERIAL_MAX_PORTS_INDEXED];
|
|
ULONG MaskInverted;
|
|
UCHAR UsablePortMask;
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|
ULONG UARTOffset;
|
|
ULONG UARTRegStride;
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|
|
// First UART in the list to be serviced next by the ISR.
|
|
PUART_OBJECT pFirstUart;
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|
|
UART_LIB UartLib; // Uart library finctions.
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|
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ULONG CardOptions;
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|
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} CARD_DEVICE_EXTENSION, *PCARD_DEVICE_EXTENSION;
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#endif // End of SPD_CARD.H
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