Source code of Windows XP (NT5)
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400 lines
16 KiB

  1. /*++
  2. Copyright (c) 1997-2000 Microsoft Corporation
  3. Module Name:
  4. data.c
  5. Abstract:
  6. Data definitions for discardable/pageable data
  7. Author:
  8. Ravisankar Pudipeddi (ravisp) - 1 Feb 1997
  9. Neil Sandlin (neilsa) June 1 1999
  10. Environment:
  11. Kernel mode
  12. Revision History :
  13. --*/
  14. #include "pch.h"
  15. #ifdef ALLOC_DATA_PRAGMA
  16. #pragma data_seg ("INIT")
  17. #endif
  18. //
  19. // Beginning of Init Data
  20. //
  21. //
  22. // Global registry values (in pcmcia\\parameters)
  23. //
  24. #define PCMCIA_REGISTRY_INTERRUPT_MASK_VALUE L"ForcedInterruptMask"
  25. #define PCMCIA_REGISTRY_INTERRUPT_FILTER_VALUE L"FilterInterruptMask"
  26. #define PCMCIA_REGISTRY_ATTRIBUTE_MEMORY_LO_VALUE L"AttributeMemoryLow"
  27. #define PCMCIA_REGISTRY_ATTRIBUTE_MEMORY_HI_VALUE L"AttributeMemoryHigh"
  28. #define PCMCIA_REGISTRY_ATTRIBUTE_MEMORY_SIZE_VALUE L"AttributeMemorySize"
  29. #define PCMCIA_REGISTRY_SOUNDS_ENABLED_VALUE L"SoundsEnabled"
  30. #define PCMCIA_REGISTRY_POWER_POLICY_VALUE L"PowerPolicy"
  31. #define PCMCIA_REGISTRY_FORCE_CTLR_DEVICE_WAKE L"ForceControllerDeviceWake"
  32. #define PCMCIA_REGISTRY_IO_HIGH_VALUE L"IoHigh"
  33. #define PCMCIA_REGISTRY_IO_LOW_VALUE L"IoLow"
  34. #define PCMCIA_REGISTRY_READY_DELAY_ITER_VALUE L"ReadyDelayIter"
  35. #define PCMCIA_REGISTRY_READY_STALL_VALUE L"ReadyStall"
  36. #define PCMCIA_REGISTRY_USE_POLLED_CSC_VALUE L"ForcePolledMode"
  37. #define PCMCIA_REGISTRY_CBMODEM_DELAY_VALUE L"CBModemReadyDelay"
  38. #define PCMCIA_REGISTRY_PCIC_MEMORY_WINDOW_DELAY L"PcicMemoryWindowDelay"
  39. #define PCMCIA_REGISTRY_PCIC_RESET_WIDTH_DELAY L"PcicResetWidthDelay"
  40. #define PCMCIA_REGISTRY_PCIC_RESET_SETUP_DELAY L"PcicResetSetupDelay"
  41. #define PCMCIA_REGISTRY_CB_RESET_WIDTH_DELAY L"CBResetWidthDelay"
  42. #define PCMCIA_REGISTRY_CB_RESET_SETUP_DELAY L"CBResetSetupDelay"
  43. #define PCMCIA_REGISTRY_CONTROLLER_POWERUP_DELAY L"ControllerPowerUpDelay"
  44. #define PCMCIA_REGISTRY_DISABLE_ISA_PCI_ROUTING L"DisableIsaToPciRouting"
  45. #define PCMCIA_REGISTRY_DEFAULT_ROUTE_R2_TO_ISA L"DefaultRouteToIsa"
  46. #define PCMCIA_REGISTRY_DISABLE_ACPI_NAMESPACE_CHK L"DisableAcpiNameSpaceCheck"
  47. #define PCMCIA_REGISTRY_IRQ_ROUTE_PCI_CTLR L"IrqRouteToPciController"
  48. #define PCMCIA_REGISTRY_IRQ_ROUTE_ISA_CTLR L"IrqRouteToIsaController"
  49. #define PCMCIA_REGISTRY_IRQ_ROUTE_PCI_LOC L"IrqRouteToPciLocation"
  50. #define PCMCIA_REGISTRY_IRQ_ROUTE_ISA_LOC L"IrqRouteToIsaLocation"
  51. #define PCMCIA_REGISTRY_REPORT_MTD0002_AS_ERROR L"ReportMTD0002AsError"
  52. #define PCMCIA_REGISTRY_DEBUG_MASK L"DebugMask"
  53. #define PCMCIA_REGISTRY_EVENT_DPC_DELAY L"EventDpcDelay"
  54. //
  55. // Table which defines global registry settings
  56. //
  57. // RegistryName Internal Variable Default Value
  58. // ------------ ----------------- -------------
  59. GLOBAL_REGISTRY_INFORMATION GlobalRegistryInfo[] = {
  60. #if DBG
  61. PCMCIA_REGISTRY_DEBUG_MASK, &PcmciaDebugMask, 1,
  62. #endif
  63. PCMCIA_REGISTRY_INTERRUPT_MASK_VALUE, &globalOverrideIrqMask, 0,
  64. PCMCIA_REGISTRY_INTERRUPT_FILTER_VALUE, &globalFilterIrqMask, 0,
  65. PCMCIA_REGISTRY_ATTRIBUTE_MEMORY_LO_VALUE, &globalAttributeMemoryLow, PCMCIA_DEFAULT_ATTRIBUTE_MEMORY_LOW,
  66. PCMCIA_REGISTRY_ATTRIBUTE_MEMORY_HI_VALUE, &globalAttributeMemoryHigh, PCMCIA_DEFAULT_ATTRIBUTE_MEMORY_HIGH,
  67. PCMCIA_REGISTRY_ATTRIBUTE_MEMORY_SIZE_VALUE, &globalAttributeMemorySize, 0,
  68. PCMCIA_REGISTRY_SOUNDS_ENABLED_VALUE, &initSoundsEnabled, 1,
  69. PCMCIA_REGISTRY_POWER_POLICY_VALUE, &PcmciaPowerPolicy, 1,
  70. PCMCIA_REGISTRY_FORCE_CTLR_DEVICE_WAKE, &PcmciaControllerDeviceWake, 0,
  71. PCMCIA_REGISTRY_IO_HIGH_VALUE, &globalIoHigh, PCMCIA_DEFAULT_IO_HIGH,
  72. PCMCIA_REGISTRY_IO_LOW_VALUE, &globalIoLow, PCMCIA_DEFAULT_IO_LOW,
  73. PCMCIA_REGISTRY_READY_DELAY_ITER_VALUE, &globalReadyDelayIter, PCMCIA_DEFAULT_READY_DELAY_ITER,
  74. PCMCIA_REGISTRY_READY_STALL_VALUE, &globalReadyStall, PCMCIA_DEFAULT_READY_STALL,
  75. PCMCIA_REGISTRY_USE_POLLED_CSC_VALUE, &initUsePolledCsc, 0,
  76. PCMCIA_REGISTRY_DISABLE_ISA_PCI_ROUTING, &pcmciaDisableIsaPciRouting, 0,
  77. PCMCIA_REGISTRY_ISA_IRQ_RESCAN_COMPLETE, &pcmciaIsaIrqRescanComplete, 0,
  78. PCMCIA_REGISTRY_IRQ_ROUTE_PCI_CTLR, &pcmciaIrqRouteToPciController, 0,
  79. PCMCIA_REGISTRY_IRQ_ROUTE_ISA_CTLR, &pcmciaIrqRouteToIsaController, 0,
  80. PCMCIA_REGISTRY_IRQ_ROUTE_PCI_LOC, &pcmciaIrqRouteToPciLocation, 0,
  81. PCMCIA_REGISTRY_IRQ_ROUTE_ISA_LOC, &pcmciaIrqRouteToIsaLocation, 0,
  82. PCMCIA_REGISTRY_DISABLE_ACPI_NAMESPACE_CHK, &initDisableAcpiNameSpaceCheck, 0,
  83. PCMCIA_REGISTRY_DEFAULT_ROUTE_R2_TO_ISA, &initDefaultRouteR2ToIsa, 0,
  84. PCMCIA_REGISTRY_CBMODEM_DELAY_VALUE, &CBModemReadyDelay, PCMCIA_DEFAULT_CB_MODEM_READY_DELAY,
  85. PCMCIA_REGISTRY_PCIC_MEMORY_WINDOW_DELAY, &PcicMemoryWindowDelay, PCMCIA_DEFAULT_PCIC_MEMORY_WINDOW_DELAY,
  86. PCMCIA_REGISTRY_PCIC_RESET_WIDTH_DELAY, &PcicResetWidthDelay, PCMCIA_DEFAULT_PCIC_RESET_WIDTH_DELAY,
  87. PCMCIA_REGISTRY_PCIC_RESET_SETUP_DELAY, &PcicResetSetupDelay, PCMCIA_DEFAULT_PCIC_RESET_SETUP_DELAY,
  88. PCMCIA_REGISTRY_CB_RESET_WIDTH_DELAY, &CBResetWidthDelay, PCMCIA_DEFAULT_CB_RESET_WIDTH_DELAY,
  89. PCMCIA_REGISTRY_CB_RESET_SETUP_DELAY, &CBResetSetupDelay, PCMCIA_DEFAULT_CB_RESET_SETUP_DELAY,
  90. PCMCIA_REGISTRY_CONTROLLER_POWERUP_DELAY, &ControllerPowerUpDelay, PCMCIA_DEFAULT_CONTROLLER_POWERUP_DELAY,
  91. PCMCIA_REGISTRY_EVENT_DPC_DELAY, &EventDpcDelay, PCMCIA_DEFAULT_EVENT_DPC_DELAY,
  92. PCMCIA_REGISTRY_REPORT_MTD0002_AS_ERROR, &pcmciaReportMTD0002AsError, 1
  93. };
  94. ULONG GlobalInfoCount = sizeof(GlobalRegistryInfo) / sizeof(GLOBAL_REGISTRY_INFORMATION);
  95. ULONG initSoundsEnabled;
  96. ULONG initUsePolledCsc;
  97. ULONG initDisableAcpiNameSpaceCheck;
  98. ULONG initDefaultRouteR2ToIsa;
  99. //
  100. // end of Init Data
  101. //
  102. #ifdef ALLOC_DATA_PRAGMA
  103. #pragma data_seg ()
  104. #endif
  105. #ifdef ALLOC_DATA_PRAGMA
  106. #pragma data_seg()
  107. #endif
  108. //
  109. // Non-Paged global variables
  110. //
  111. //
  112. // List of FDOs managed by this driver
  113. //
  114. PDEVICE_OBJECT FdoList;
  115. //
  116. // GLobal Flags
  117. //
  118. ULONG PcmciaGlobalFlags = 0;
  119. //
  120. // Event used by PcmciaWait
  121. //
  122. KEVENT PcmciaDelayTimerEvent;
  123. //
  124. // Objects used by PcmciaPlayTone
  125. //
  126. PPCMCIA_SOUND_EVENT PcmciaToneList;
  127. KTIMER PcmciaToneTimer;
  128. KDPC PcmciaToneDpc;
  129. KSPIN_LOCK PcmciaToneLock;
  130. KSPIN_LOCK PcmciaGlobalLock;
  131. PPCMCIA_NTDETECT_DATA pNtDetectDataList = NULL;
  132. ULONG PcicStallPower = PWRON_DELAY;
  133. //
  134. // Various values set by PcmciaLoadGlobalRegistryValues
  135. //
  136. ULONG PcicMemoryWindowDelay;
  137. ULONG PcicResetWidthDelay;
  138. ULONG PcicResetSetupDelay;
  139. ULONG CBResetWidthDelay;
  140. ULONG CBResetSetupDelay;
  141. ULONG CBModemReadyDelay;
  142. ULONG ControllerPowerUpDelay;
  143. ULONG EventDpcDelay;
  144. ULONG PcmciaPowerPolicy;
  145. LONG PcmciaControllerDeviceWake;
  146. ULONG globalOverrideIrqMask;
  147. ULONG globalFilterIrqMask;
  148. ULONG globalIoLow;
  149. ULONG globalIoHigh;
  150. ULONG globalReadyDelayIter;
  151. ULONG globalReadyStall;
  152. ULONG globalAttributeMemoryLow;
  153. ULONG globalAttributeMemoryHigh;
  154. ULONG globalAttributeMemorySize;
  155. ULONG pcmciaDisableIsaPciRouting;
  156. ULONG pcmciaIsaIrqRescanComplete;
  157. ULONG pcmciaIrqRouteToPciController;
  158. ULONG pcmciaIrqRouteToIsaController;
  159. ULONG pcmciaIrqRouteToPciLocation;
  160. ULONG pcmciaIrqRouteToIsaLocation;
  161. ULONG pcmciaReportMTD0002AsError;
  162. #if DBG
  163. ULONG PcmciaDebugMask;
  164. #endif
  165. #ifdef ALLOC_DATA_PRAGMA
  166. #pragma data_seg("PAGE")
  167. #endif
  168. //
  169. // Paged const tables
  170. //
  171. const
  172. PCI_CONTROLLER_INFORMATION PciControllerInformation[] = {
  173. // Vendor id Device Id Controller type
  174. // -------------------------------------------------------------------------------
  175. PCI_CIRRUSLOGIC_VENDORID, PCI_CLPD6729_DEVICEID, PcmciaCLPD6729,
  176. PCI_CIRRUSLOGIC_VENDORID, PCI_CLPD6832_DEVICEID, PcmciaCLPD6832,
  177. PCI_CIRRUSLOGIC_VENDORID, PCI_CLPD6834_DEVICEID, PcmciaCLPD6834,
  178. PCI_TI_VENDORID, PCI_TI1031_DEVICEID, PcmciaTI1031,
  179. PCI_TI_VENDORID, PCI_TI1130_DEVICEID, PcmciaTI1130,
  180. PCI_TI_VENDORID, PCI_TI1131_DEVICEID, PcmciaTI1131,
  181. PCI_TI_VENDORID, PCI_TI1250_DEVICEID, PcmciaTI1250,
  182. PCI_TI_VENDORID, PCI_TI1220_DEVICEID, PcmciaTI1220,
  183. PCI_TI_VENDORID, PCI_TI1251B_DEVICEID, PcmciaTI1251B,
  184. PCI_TI_VENDORID, PCI_TI1450_DEVICEID, PcmciaTI1450,
  185. PCI_TOSHIBA_VENDORID, PCI_TOPIC95_DEVICEID, PcmciaTopic95,
  186. PCI_RICOH_VENDORID, PCI_RL5C465_DEVICEID, PcmciaRL5C465,
  187. PCI_RICOH_VENDORID, PCI_RL5C466_DEVICEID, PcmciaRL5C466,
  188. PCI_RICOH_VENDORID, PCI_RL5C475_DEVICEID, PcmciaRL5C475,
  189. PCI_RICOH_VENDORID, PCI_RL5C476_DEVICEID, PcmciaRL5C476,
  190. PCI_RICOH_VENDORID, PCI_RL5C478_DEVICEID, PcmciaRL5C478,
  191. PCI_DATABOOK_VENDORID, PCI_DB87144_DEVICEID, PcmciaDB87144,
  192. PCI_OPTI_VENDORID, PCI_OPTI82C814_DEVICEID, PcmciaOpti82C814,
  193. PCI_OPTI_VENDORID, PCI_OPTI82C824_DEVICEID, PcmciaOpti82C824,
  194. PCI_TRIDENT_VENDORID, PCI_TRID82C194_DEVICEID, PcmciaTrid82C194,
  195. PCI_NEC_VENDORID, PCI_NEC66369_DEVICEID, PcmciaNEC66369,
  196. // --------------------------------------------------------------------
  197. // Additional database entries go above this line
  198. //
  199. PCI_INVALID_VENDORID, 0, 0,
  200. };
  201. const
  202. PCI_VENDOR_INFORMATION PciVendorInformation[] = {
  203. PCI_TI_VENDORID, PcmciaTI,
  204. PCI_TOSHIBA_VENDORID, PcmciaTopic,
  205. PCI_RICOH_VENDORID, PcmciaRicoh,
  206. PCI_O2MICRO_VENDORID, PcmciaO2Micro,
  207. PCI_NEC_VENDORID, PcmciaNEC,
  208. PCI_DATABOOK_VENDORID, PcmciaDatabook,
  209. PCI_OPTI_VENDORID, PcmciaOpti,
  210. PCI_TRIDENT_VENDORID, PcmciaTrid,
  211. PCI_INVALID_VENDORID, 0
  212. };
  213. const
  214. DEVICE_DISPATCH_TABLE DeviceDispatchTable[] = {
  215. {PcmciaIntelCompatible, NULL, PcicSetPower, NULL, NULL, NULL},
  216. {PcmciaPciPcmciaBridge, NULL, PcicSetPower, NULL, NULL, NULL},
  217. {PcmciaElcController, NULL, PcicSetPower, NULL, NULL, NULL},
  218. {PcmciaCardBusCompatible, NULL, CBSetPower, NULL, NULL, CBSetWindowPage},
  219. {PcmciaDatabook, NULL, TcicSetPower, NULL, NULL, NULL},
  220. {PcmciaTI, TIInitialize, CBSetPower, NULL, TISetZV, TISetWindowPage},
  221. {PcmciaCirrusLogic,CLInitialize, CLSetPower, NULL, CLSetZV, CBSetWindowPage},
  222. {PcmciaTopic, TopicInitialize, TopicSetPower, TopicSetAudio, TopicSetZV, CBSetWindowPage},
  223. {PcmciaRicoh, RicohInitialize, CBSetPower, NULL, RicohSetZV, CBSetWindowPage},
  224. {PcmciaDatabookCB, DBInitialize, CBSetPower, NULL, DBSetZV, CBSetWindowPage},
  225. {PcmciaOpti, OptiInitialize, OptiSetPower, NULL, OptiSetZV, NULL},
  226. {PcmciaTrid, NULL, CBSetPower, NULL, NULL, NULL},
  227. {PcmciaO2Micro, O2MInitialize, O2MSetPower, NULL, O2MSetZV, CBSetWindowPage},
  228. {PcmciaNEC_98, NULL, PcicSetPower, NULL, NULL, NULL},
  229. {PcmciaNEC, NULL, CBSetPower, NULL, NULL, NULL},
  230. //------------------------------------------------------------------
  231. // Additional dispatch table entries go above this line
  232. //
  233. {PcmciaInvalidControllerClass, NULL, NULL, NULL, NULL}
  234. };
  235. const
  236. PCMCIA_ID_ENTRY PcmciaAdapterHardwareIds[] = {
  237. PcmciaIntelCompatible, "*PNP0E00",
  238. PcmciaElcController, "*PNP0E02",
  239. PcmciaDatabook, "*DBK0000",
  240. PcmciaCLPD6729, "*PNP0E01",
  241. PcmciaNEC98, "*nEC1E01",
  242. PcmciaNEC98102, "*nEC8091",
  243. PcmciaInvalidControllerType, 0
  244. };
  245. const
  246. PCMCIA_REGISTER_INIT PcicRegisterInitTable[] = {
  247. PCIC_INTERRUPT, IGC_PCCARD_RESETLO,
  248. PCIC_CARD_CHANGE, 0x00,
  249. PCIC_CARD_INT_CONFIG, 0x00,
  250. PCIC_ADD_WIN_ENA, 0x00,
  251. PCIC_IO_CONTROL, 0x00,
  252. //
  253. // Init the 2 I/O windows
  254. //
  255. PCIC_IO_ADD0_STRT_L, 0x00,
  256. PCIC_IO_ADD0_STRT_H, 0x00,
  257. PCIC_IO_ADD0_STOP_L, 0x00,
  258. PCIC_IO_ADD0_STOP_H, 0x00,
  259. PCIC_IO_ADD1_STRT_L, 0x00,
  260. PCIC_IO_ADD1_STRT_H, 0x00,
  261. PCIC_IO_ADD1_STOP_L, 0x00,
  262. PCIC_IO_ADD1_STOP_H, 0x00,
  263. //
  264. // Init all 5 memory windows
  265. //
  266. PCIC_MEM_ADD0_STRT_L, 0xFF,
  267. PCIC_MEM_ADD0_STRT_H, 0x0F,
  268. PCIC_MEM_ADD0_STOP_L, 0xFF,
  269. PCIC_MEM_ADD0_STOP_H, 0x0F,
  270. PCIC_CRDMEM_OFF_ADD0_L, 0x00,
  271. PCIC_CRDMEM_OFF_ADD0_H, 0x00,
  272. PCIC_MEM_ADD1_STRT_L, 0xFF,
  273. PCIC_MEM_ADD1_STRT_H, 0x0F,
  274. PCIC_MEM_ADD1_STOP_L, 0xFF,
  275. PCIC_MEM_ADD1_STOP_H, 0x0F,
  276. PCIC_CRDMEM_OFF_ADD1_L, 0x00,
  277. PCIC_CRDMEM_OFF_ADD1_H, 0x00,
  278. PCIC_MEM_ADD2_STRT_L, 0xFF,
  279. PCIC_MEM_ADD2_STRT_H, 0x0F,
  280. PCIC_MEM_ADD2_STOP_L, 0xFF,
  281. PCIC_MEM_ADD2_STOP_H, 0x0F,
  282. PCIC_CRDMEM_OFF_ADD2_L, 0x00,
  283. PCIC_CRDMEM_OFF_ADD2_H, 0x00,
  284. PCIC_MEM_ADD3_STRT_L, 0xFF,
  285. PCIC_MEM_ADD3_STRT_H, 0x0F,
  286. PCIC_MEM_ADD3_STOP_L, 0xFF,
  287. PCIC_MEM_ADD3_STOP_H, 0x0F,
  288. PCIC_CRDMEM_OFF_ADD3_L, 0x00,
  289. PCIC_CRDMEM_OFF_ADD3_H, 0x00,
  290. PCIC_MEM_ADD4_STRT_L, 0xFF,
  291. PCIC_MEM_ADD4_STRT_H, 0x0F,
  292. PCIC_MEM_ADD4_STOP_L, 0xFF,
  293. PCIC_MEM_ADD4_STOP_H, 0x0F,
  294. PCIC_CRDMEM_OFF_ADD4_L, 0x00,
  295. PCIC_CRDMEM_OFF_ADD4_H, 0x00,
  296. //
  297. // Any other registers go here
  298. //
  299. 0xFFFFFFFF, 0x00
  300. };
  301. #ifdef ALLOC_DATA_PRAGMA
  302. #pragma data_seg()
  303. #endif
  304. //
  305. // Non-paged const tables
  306. //
  307. //
  308. // This should be non-pageable since it is referenced by the
  309. // Power management code - most of which runs at raised IRQL
  310. // This represents the default set of registers that need to be
  311. // saved/restored on a cardbus controller power-down/power-up
  312. //
  313. //
  314. // Register context for the pcmcia controller
  315. //
  316. const
  317. PCMCIA_CONTEXT_RANGE DefaultPciContextSave[] = {
  318. CFGSPACE_BRIDGE_CTRL, 2,
  319. CFGSPACE_LEGACY_MODE_BASE_ADDR, 4,
  320. // CFGSPACE_CB_LATENCY_TIMER, 1,
  321. 0, 0
  322. };
  323. //
  324. // cardbus socket registers required to be saved
  325. //
  326. const
  327. PCMCIA_CONTEXT_RANGE DefaultCardbusContextSave[] = {
  328. 0, 0
  329. };
  330. //
  331. // cardbus socket registers excluded from context save
  332. //
  333. const
  334. PCMCIA_CONTEXT_RANGE ExcludeCardbusContextRange[] = {
  335. CARDBUS_SOCKET_EVENT_REG, 0x4,
  336. CARDBUS_SOCKET_PRESENT_STATE_REG, 0xc,
  337. 0, 0
  338. };
  339. //
  340. // The following table defines any devices that need special
  341. // attention during configuration. Note that values of 0xffff
  342. // mean "don't care". The table is scanned until a match is made
  343. // for the current device.
  344. //
  345. // Values are:
  346. // validentry, devicetype, manufacturer, code, crc, configdelay1, configdelay2, configdelay3, configflags
  347. //
  348. // delay values are in milliseconds
  349. //
  350. const
  351. PCMCIA_DEVICE_CONFIG_PARAMS DeviceConfigParams[] = {
  352. 1, PCCARD_TYPE_MODEM, 0x109, 0x505, 0xD293, 3100, 900, 0, CONFIG_WORKER_APPLY_MODEM_HACK, // motorola BitSurfr 56k
  353. 1, PCCARD_TYPE_MODEM, 0xffff, 0xffff, 0xffff, 0, 1800, 0, 0, // any other modem
  354. 1, PCCARD_TYPE_ATA, 0xffff, 0xffff, 0xffff, 0, 0, 2000, 0, // any ata device
  355. 0
  356. };