Source code of Windows XP (NT5)
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  1. /*++
  2. Copyright (c) 1993 Weitek Corporation
  3. Module Name:
  4. p9gbl.c
  5. Abstract:
  6. This module contains the global data for the Weitek P9 miniport
  7. device driver.
  8. Environment:
  9. Kernel mode
  10. Revision History may be found at the end of this file.
  11. --*/
  12. #include "p9.h"
  13. #include "p9gbl.h"
  14. #include "p9000.h"
  15. #include "bt485.h"
  16. #include "vga.h"
  17. #include "p91regs.h"
  18. #include "p91dac.h"
  19. #include "pci.h"
  20. //
  21. // This global is used as an error flag to error out quickly on the multiple
  22. // calls to P9FindAdapter when a board is not supported.
  23. //
  24. VP_STATUS vpP91AdapterStatus = NO_ERROR;
  25. BOOLEAN bFoundPCI = FALSE;
  26. //
  27. // Coprocessor info structure for the Weitek P9100.
  28. //
  29. //
  30. // The P9100's total address space is 16mb (0x0100000). The maximum
  31. // frame-buffer is 4mb (0x00400000). So define the coproc length as
  32. // the maximum (16mb) less the size of the frame buffer (4mb).
  33. // Note: we might want to map the optional video power coprocessor
  34. // discretely.
  35. //
  36. // NOTE only ask for 0x00C00000 since that;s was preconfigured PCI devices
  37. // have.
  38. //
  39. P9_COPROC P9100Info =
  40. {
  41. P9100_ID,
  42. 0x00C00000, // Size of memory address space.
  43. 0x00000000, // Offset to coproc regs.
  44. 0x00800000, // Size of coproc register block.
  45. 0x00800000, // Offset to frame buffer.
  46. P91SizeVideoMemory // Memory sizing function.
  47. };
  48. //
  49. // Coprocessor info structure for the Weitek P9000.
  50. //
  51. P9_COPROC P9000Info =
  52. {
  53. P9000_ID,
  54. 0x00400000, // Size of memory address space.
  55. 0x00100000, // Offset to coproc regs.
  56. 0x00100000, // Size of coproc register block.
  57. 0x00200000, // Offset to frame buffer.
  58. P9000SizeMem // Memory sizing function.
  59. };
  60. //
  61. // The default adapter description structure for the Weitek P9 PCI
  62. // boards.
  63. //
  64. ADAPTER_DESC WtkPciDesc =
  65. {
  66. {L"Weitek P9000 PCI Adapter"},
  67. 0L, // P9 Memconf value (un-initialized)
  68. HSYNC_INTERNAL | VSYNC_INTERNAL |
  69. COMPOSITE_SYNC | VIDEO_NORMAL, // P9 Srctl value
  70. TRUE, // Should autodetection be attempted?
  71. TRUE, // Is this a PCI adapter ?
  72. PciGetBaseAddr, // Routine to detect/map P9 base addr
  73. VLSetMode, // Routine to set the P9 mode
  74. VLEnableP9, // Routine to enable P9 video
  75. VLDisableP9, // Routine to disable P9 video
  76. PciP9MemEnable, // Routine to enable memory/io
  77. 8, // Clock divisor value
  78. TRUE, // Is a Wtk 5x86 VGA present?
  79. TRUE
  80. };
  81. //
  82. // The default adapter description structure for the Weitek P9100 PCI
  83. // boards.
  84. //
  85. ADAPTER_DESC WtkP91PciDesc =
  86. {
  87. {L"Weitek P9100 PCI Adapter"},
  88. 0L, // P9 Memconf value (un-initialized)
  89. HSYNC_INTERNAL | VSYNC_INTERNAL |
  90. COMPOSITE_SYNC | VIDEO_NORMAL, // P9 Srctl value
  91. TRUE, // Should autodetection be attempted?
  92. TRUE, // Is this a PCI adapter ?
  93. PciGetBaseAddr, // Routine to detect/map P9 base addr
  94. VLSetModeP91, // Routine to set the P9 mode
  95. VLEnableP91, // Routine to enable P9 video
  96. VLDisableP91, // Routine to disable P9 video
  97. // PciP9MemEnable, // Routine to enable memory/io
  98. NULL,
  99. 4, // Clock divisor value
  100. TRUE, // Is a Wtk 5x86 VGA present?
  101. FALSE
  102. };
  103. //
  104. // The default adapter description structure for the Diamond Viper VL board.
  105. //
  106. ADAPTER_DESC ViperVLDesc =
  107. {
  108. {L"Diamond Viper P9000 VL Adapter"},
  109. 0L, // P9 Memconf value (un-initialized)
  110. HSYNC_INTERNAL | VSYNC_INTERNAL |
  111. COMPOSITE_SYNC | VIDEO_NORMAL, // P9 Srctl value
  112. TRUE, // Should autodetection be attempted?
  113. FALSE, // Is this a PCI adapter ?
  114. ViperGetBaseAddr, // Routine to detect/map P9 base addr
  115. ViperSetMode, // Routine to set the P9 mode
  116. ViperEnableP9, // Routine to enable P9 video
  117. ViperDisableP9, // Routine to disable P9 video
  118. ViperEnableMem, // Routine to enable P9 memory
  119. 4, // Clock divisor value
  120. TRUE, // Is a Wtk 5x86 VGA present?
  121. TRUE
  122. };
  123. //
  124. // The default adapter description structure for the Weitek P9100 PCI
  125. // boards.
  126. //
  127. ADAPTER_DESC WtkP91VLDesc =
  128. {
  129. {L"Weitek P9100 VL Adapter"},
  130. 0L, // P9 Memconf value (un-initialized)
  131. HSYNC_INTERNAL | VSYNC_INTERNAL |
  132. COMPOSITE_SYNC | VIDEO_NORMAL, // P9 Srctl value
  133. TRUE, // Should autodetection be attempted?
  134. FALSE, // Is this a PCI adapter ?
  135. VLGetBaseAddrP91, // Routine to detect/map P9 base addr
  136. VLSetModeP91, // Routine to set the P9 mode
  137. VLEnableP91, // Routine to enable P9 video
  138. VLDisableP91, // Routine to disable P9 video
  139. // PciP9MemEnable, // Routine to enable memory/io
  140. NULL,
  141. 4, // Clock divisor value
  142. TRUE, // Is a Wtk 5x86 VGA present?
  143. FALSE
  144. };
  145. //
  146. // The default adapter description structure for the Weitek P9000 VL board.
  147. //
  148. ADAPTER_DESC WtkVLDesc =
  149. {
  150. {L"Generic Weitek P9000 VL Adapter"},
  151. 0L, // P9 Memconf value (un-initialized)
  152. HSYNC_INTERNAL | VSYNC_INTERNAL |
  153. COMPOSITE_SYNC | VIDEO_NORMAL, // P9 Srctl value
  154. FALSE, // Should autodetection be attempted?
  155. FALSE, // Is this a PCI adapter ?
  156. VLGetBaseAddr, // Routine to detect/map P9 base addr
  157. VLSetMode, // Routine to set the P9 mode
  158. VLEnableP9, // Routine to enable P9 video
  159. VLDisableP9, // Routine to disable P9 video
  160. (PVOID) 0, // Routine to enable P9 memory
  161. 4, // Clock divisor value
  162. TRUE, // Is a Wtk 5x86 VGA present?
  163. TRUE
  164. };
  165. //
  166. // List of OEM P9ADAPTER structures.
  167. //
  168. P9ADAPTER OEMAdapter[NUM_OEM_ADAPTERS] =
  169. {
  170. //
  171. // Weitek P9100 PCI adapters, with the IBM525,
  172. // including Viper PCI Adapter.
  173. //
  174. {
  175. &WtkP91PciDesc,
  176. &Ibm525,
  177. &P9100Info
  178. },
  179. // Weitek P9100 PCI adapters, with the Bt485
  180. //
  181. {
  182. &WtkP91PciDesc,
  183. &P91Bt485,
  184. &P9100Info
  185. },
  186. //
  187. // Weitek P9100 PCI adapters, with the Bt489
  188. //
  189. {
  190. &WtkP91PciDesc,
  191. &P91Bt489,
  192. &P9100Info
  193. },
  194. //
  195. // Weitek PCI adapters, including Viper PCI Adapter.
  196. //
  197. {
  198. &WtkPciDesc,
  199. &Bt485,
  200. &P9000Info
  201. },
  202. //
  203. // Weitek P9100 VL adapters, with the IBM525,
  204. //
  205. {
  206. &WtkP91VLDesc,
  207. &Ibm525,
  208. &P9100Info
  209. },
  210. //
  211. // Weitek P9100 VL adapters, with the Bt485,
  212. //
  213. {
  214. &WtkP91VLDesc,
  215. &Bt485,
  216. &P9100Info
  217. },
  218. // Viper VL Adapter.
  219. //
  220. {
  221. &ViperVLDesc,
  222. &Bt485,
  223. &P9000Info
  224. },
  225. //
  226. // Adapters based on the Weitek VL Design.
  227. //
  228. {
  229. &WtkVLDesc,
  230. &Bt485,
  231. &P9000Info
  232. }
  233. };
  234. //
  235. // DriverAccessRanges are used to verify access to the P9 coprocessor's
  236. // address space and to the VGA and DAC registers.
  237. //
  238. VIDEO_ACCESS_RANGE DriverAccessRanges[NUM_DRIVER_ACCESS_RANGES
  239. + NUM_DAC_ACCESS_RANGES
  240. + NUM_MISC_ACCESS_RANGES] =
  241. {
  242. //
  243. // The P9 Coprocessor's access range. Everything is initialized
  244. // except for the base address and length which are Coprocessor
  245. // specific.
  246. //
  247. {
  248. 0L, // Low address. To be initialized.
  249. 0L, // Hi address
  250. 0L, // length. To be initialized.
  251. 0, // Is range in i/o space?
  252. 1, // Range should be visible
  253. 1 // Range should be shareable
  254. },
  255. //
  256. // The VGA Access Range. Every field is initialized.
  257. //
  258. {
  259. 0x000003C0, // Low addr vga & dac
  260. 0x00000000, // Hi addr
  261. 0x20, // length
  262. 1, // Is range in i/o space?
  263. 1, // Range should be visible
  264. 1 // Range should be shareable
  265. },
  266. //
  267. // The following access ranges are for the DAC and are uninitialized.
  268. //
  269. {
  270. 0L, // Low address
  271. 0L, // Hi address
  272. 0L, // length
  273. 0, // Is range in i/o space?
  274. 0, // Range should be visible
  275. 0 // Range should be shareable
  276. },
  277. {
  278. 0L, // Low address
  279. 0L, // Hi address
  280. 0L, // length
  281. 0, // Is range in i/o space?
  282. 0, // Range should be visible
  283. 0 // Range should be shareable
  284. },
  285. {
  286. 0L, // Low address
  287. 0L, // Hi address
  288. 0L, // length
  289. 0, // Is range in i/o space?
  290. 0, // Range should be visible
  291. 0 // Range should be shareable
  292. },
  293. {
  294. 0L, // Low address
  295. 0L, // Hi address
  296. 0L, // length
  297. 0, // Is range in i/o space?
  298. 0, // Range should be visible
  299. 0 // Range should be shareable
  300. },
  301. {
  302. 0L, // Low address
  303. 0L, // Hi address
  304. 0L, // length
  305. 0, // Is range in i/o space?
  306. 0, // Range should be visible
  307. 0 // Range should be shareable
  308. },
  309. {
  310. 0L, // Low address
  311. 0L, // Hi address
  312. 0L, // length
  313. 0, // Is range in i/o space?
  314. 0, // Range should be visible
  315. 0 // Range should be shareable
  316. },
  317. {
  318. 0L, // Low address
  319. 0L, // Hi address
  320. 0L, // length
  321. 0, // Is range in i/o space?
  322. 0, // Range should be visible
  323. 0 // Range should be shareable
  324. },
  325. {
  326. 0L, // Low address
  327. 0L, // Hi address
  328. 0L, // length
  329. 0, // Is range in i/o space?
  330. 0, // Range should be visible
  331. 0 // Range should be shareable
  332. },
  333. {
  334. 0L, // Low address
  335. 0L, // Hi address
  336. 0L, // length
  337. 0, // Is range in i/o space?
  338. 0, // Range should be visible
  339. 0 // Range should be shareable
  340. },
  341. {
  342. 0L, // Low address
  343. 0L, // Hi address
  344. 0L, // length
  345. 0, // Is range in i/o space?
  346. 0, // Range should be visible
  347. 0 // Range should be shareable
  348. },
  349. {
  350. 0L, // Low address
  351. 0L, // Hi address
  352. 0L, // length
  353. 0, // Is range in i/o space?
  354. 0, // Range should be visible
  355. 0 // Range should be shareable
  356. },
  357. {
  358. 0L, // Low address
  359. 0L, // Hi address
  360. 0L, // length
  361. 0, // Is range in i/o space?
  362. 0, // Range should be visible
  363. 0 // Range should be shareable
  364. },
  365. {
  366. 0L, // Low address
  367. 0L, // Hi address
  368. 0L, // length
  369. 0, // Is range in i/o space?
  370. 0, // Range should be visible
  371. 0 // Range should be shareable
  372. },
  373. {
  374. 0L, // Low address
  375. 0L, // Hi address
  376. 0L, // length
  377. 0, // Is range in i/o space?
  378. 0, // Range should be visible
  379. 0 // Range should be shareable
  380. },
  381. {
  382. 0L, // Low address
  383. 0L, // Hi address
  384. 0L, // length
  385. 0, // Is range in i/o space?
  386. 0, // Range should be visible
  387. 0 // Range should be shareable
  388. },
  389. {
  390. 0L, // Low address
  391. 0L, // Hi address
  392. 0L, // length
  393. 0, // Is range in i/o space?
  394. 0, // Range should be visible
  395. 0 // Range should be shareable
  396. },
  397. //
  398. // This is a miscellaneous access range. It is uninitialized and
  399. // is only used (currently) by the PCI adapter type.
  400. //
  401. {
  402. 0L, // Low address
  403. 0L, // Hi address
  404. 0L, // length
  405. 0, // Is range in i/o space?
  406. 0, // Range should be visible
  407. 0 // Range should be shareable
  408. }
  409. };
  410. VDATA v1280_1K_55[] =
  411. {
  412. 10018L, // Dot Freq 1
  413. 184L, // Horiz Sync Pulse
  414. 200L, // Horiz Back Porch
  415. 1280L, // X size
  416. 44L, // Horiz Front Porch
  417. 360L, // hco
  418. POSITIVE, // Horizontal Polarity
  419. 55L, // Vertical Refresh Rate in Hz.
  420. 3L, // Vertical Sync Pulse
  421. 26L, // Vertical Back Porch
  422. 1024L, // Y size
  423. 3L, // Vertical Front Porch
  424. 27L, // vco
  425. POSITIVE, // Vertical Polarity
  426. 0, // IcdSerPixClk
  427. 0xFFFFFFFF, // IcdCtrlPixClk
  428. 0, // IcdSer525Ref
  429. 0xFFFFFFFF, // IcdCtrl525Ref
  430. 0xFFFFFFFF, // 525RefClkCnt
  431. 0xFFFFFFFF, // 525VidClkFreq
  432. 0xFFFFFFFF, // MemCfgClr
  433. 0 // MemCfgSet
  434. };
  435. //
  436. // These values came from the 3.1 driver.
  437. // They are more current than the 3.5 values
  438. //
  439. VDATA v640_480_60[] =
  440. {
  441. 2517L, // Dot Freq 1
  442. 96L, // Horiz Sync Pulse
  443. 32L, // Horiz Back Porch
  444. 640L, // X size
  445. 32L, // Horiz Front Porch
  446. 0L, // hco
  447. NEGATIVE, // Horizontal Polarity
  448. 60L, // Vertical Refresh Rate in Hz.
  449. 4L, // Vertical Sync Pulse
  450. 24L, // Vertical Back Porch
  451. 480L, // Y size
  452. 17L, // Vertical Front Porch
  453. 0L, // vco
  454. NEGATIVE, // Vertical Polarity
  455. 0, // IcdSerPixClk
  456. 0xFFFFFFFF, // IcdCtrlPixClk
  457. 0, // IcdSer525Ref
  458. 0xFFFFFFFF, // IcdCtrl525Ref
  459. 0xFFFFFFFF, // 525RefClkCnt
  460. 0xFFFFFFFF, // 525VidClkFreq
  461. 0xFFFFFFFF, // MemCfgClr
  462. 0 // MemCfgSet
  463. };
  464. VDATA v640_480_72[] =
  465. {
  466. 3150L, // Dot Freq 1
  467. 40L, // Horiz Sync Pulse
  468. 136L, // Horiz Back Porch
  469. 640L, // X size
  470. 32L, // Horiz Front Porch
  471. 144L, // hco
  472. NEGATIVE, // Horizontal Polarity
  473. 72L, // Vertical Refresh Rate in Hz.
  474. 3L, // Vertical Sync Pulse
  475. 28L, // Vertical Back Porch
  476. 480L, // Y size
  477. 9L, // Vertical Front Porch
  478. 35L, // vco
  479. NEGATIVE, // Vertical Polarity
  480. 0, // IcdSerPixClk
  481. 0xFFFFFFFF, // IcdCtrlPixClk
  482. 0, // IcdSer525Ref
  483. 0xFFFFFFFF, // IcdCtrl525Ref
  484. 0xFFFFFFFF, // 525RefClkCnt
  485. 0xFFFFFFFF, // 525VidClkFreq
  486. 0xFFFFFFFF, // MemCfgClr
  487. 0 // MemCfgSet
  488. };
  489. VDATA v800_600_60[] =
  490. {
  491. 4000L, // Dot Freq 1
  492. 128L, // Horiz Sync Pulse
  493. 88L, // Horiz Back Porch
  494. 800L, // X size
  495. 40L, // Horiz Front Porch
  496. 192L, // hco
  497. POSITIVE, // Horizontal Polarity
  498. 60L, // Vertical Refresh Rate in Hz.
  499. 4L, // Vertical Sync Pulse
  500. 23L, // Vertical Back Porch
  501. 600L, // Y size
  502. 1L, // Vertical Front Porch
  503. 22L, // vco
  504. POSITIVE, // Vertical Polarity
  505. 0, // IcdSerPixClk
  506. 0xFFFFFFFF, // IcdCtrlPixClk
  507. 0, // IcdSer525Ref
  508. 0xFFFFFFFF, // IcdCtrl525Ref
  509. 0xFFFFFFFF, // 525RefClkCnt
  510. 0xFFFFFFFF, // 525VidClkFreq
  511. 0xFFFFFFFF, // MemCfgClr
  512. 0 // MemCfgSet
  513. };
  514. VDATA v800_600_72[] =
  515. {
  516. 5000L, // Dot Freq 1
  517. 120L, // Horiz Sync Pulse
  518. 64L, // Horiz Back Porch
  519. 800L, // X size
  520. 56L, // Horiz Front Porch
  521. 192L, // hco
  522. POSITIVE, // Horizontal Polarity
  523. 72L, // Vertical Refresh Rate in Hz.
  524. 6L, // Vertical Sync Pulse
  525. 23L, // Vertical Back Porch
  526. 600L, // Y size
  527. 37L, // Vertical Front Porch
  528. 22L, // vco
  529. POSITIVE, // Vertical Polarity
  530. 0, // IcdSerPixClk
  531. 0xFFFFFFFF, // IcdCtrlPixClk
  532. 0, // IcdSer525Ref
  533. 0xFFFFFFFF, // IcdCtrl525Ref
  534. 0xFFFFFFFF, // 525RefClkCnt
  535. 0xFFFFFFFF, // 525VidClkFreq
  536. 0xFFFFFFFF, // MemCfgClr
  537. 0 // MemCfgSet
  538. };
  539. VDATA v1K_768_60[] =
  540. {
  541. 6500L, // Dot Freq 1
  542. 136L, // Horiz Sync Pulse
  543. 160L, // Horiz Back Porch
  544. 1024L, // X size
  545. 24L, // Horiz Front Porch
  546. 272L, // hco
  547. NEGATIVE, // Horizontal Polarity
  548. 60L, // Vertical Refresh Rate in Hz.
  549. 6L, // Vertical Sync Pulse
  550. 29L, // Vertical Back Porch
  551. 768L, // Y size
  552. 3L, // Vertical Front Porch
  553. 30L, // vco
  554. NEGATIVE, // Vertical Polarity
  555. 0, // IcdSerPixClk
  556. 0xFFFFFFFF, // IcdCtrlPixClk
  557. 0, // IcdSer525Ref
  558. 0xFFFFFFFF, // IcdCtrl525Ref
  559. 0xFFFFFFFF, // 525RefClkCnt
  560. 0xFFFFFFFF, // 525VidClkFreq
  561. 0xFFFFFFFF, // MemCfgClr
  562. 0 // MemCfgSet
  563. };
  564. VDATA v1K_768_70[] =
  565. {
  566. 7500L, // Dot Freq 1
  567. 136L, // Horiz Sync Pulse
  568. 144L, // Horiz Back Porch
  569. 1024L, // X size
  570. 24L, // Horiz Front Porch
  571. 256L, // hco
  572. NEGATIVE, // Horizontal Polarity
  573. 70L, // Vertical Refresh Rate in Hz.
  574. 6L, // Vertical Sync Pulse
  575. 29L, // Vertical Back Porch
  576. 768L, // Y size
  577. 3L, // Vertical Front Porch
  578. 30L, // vco
  579. NEGATIVE, // Vertical Polarity
  580. 0, // IcdSerPixClk
  581. 0xFFFFFFFF, // IcdCtrlPixClk
  582. 0, // IcdSer525Ref
  583. 0xFFFFFFFF, // IcdCtrl525Ref
  584. 0xFFFFFFFF, // 525RefClkCnt
  585. 0xFFFFFFFF, // 525VidClkFreq
  586. 0xFFFFFFFF, // MemCfgClr
  587. 0 // MemCfgSet
  588. };
  589. VDATA v1280_1K_60[] =
  590. {
  591. 11500L, // Dot Freq 1
  592. 224L, // Horiz Sync Pulse
  593. 256L, // Horiz Back Porch
  594. 1280L, // X size
  595. 32L, // Horiz Front Porch
  596. 456L, // hco
  597. POSITIVE, // Horizontal Polarity
  598. 60L, // Vertical Refresh Rate in Hz.
  599. 3L, // Vertical Sync Pulse
  600. 42L, // Vertical Back Porch
  601. 1024L, // Y size
  602. 1L, // Vertical Front Porch
  603. 41L, // vco
  604. POSITIVE, // Vertical Polarity
  605. 0, // IcdSerPixClk
  606. 0xFFFFFFFF, // IcdCtrlPixClk
  607. 0, // IcdSer525Ref
  608. 0xFFFFFFFF, // IcdCtrl525Ref
  609. 0xFFFFFFFF, // 525RefClkCnt
  610. 0xFFFFFFFF, // 525VidClkFreq
  611. 0xFFFFFFFF, // MemCfgClr
  612. 0 // MemCfgSet
  613. };
  614. VDATA v1280_1K_74[] =
  615. {
  616. 13500L, // Dot Freq 1
  617. 144L, // Horiz Sync Pulse
  618. 256L, // Horiz Back Porch
  619. 1280L, // X size
  620. 32L, // Horiz Front Porch
  621. 0L, // hco
  622. POSITIVE, // Horizontal Polarity
  623. 74L, // Vertical Refresh Rate in Hz.
  624. 3L, // Vertical Sync Pulse
  625. 38L, // Vertical Back Porch
  626. 1024L, // Y size
  627. 1L, // Vertical Front Porch
  628. 0L, // vco
  629. POSITIVE, // Vertical Polarity
  630. 0, // IcdSerPixClk
  631. 0xFFFFFFFF, // IcdCtrlPixClk
  632. 0, // IcdSer525Ref
  633. 0xFFFFFFFF, // IcdCtrl525Ref
  634. 0xFFFFFFFF, // 525RefClkCnt
  635. 0xFFFFFFFF, // 525VidClkFreq
  636. 0xFFFFFFFF, // MemCfgClr
  637. 0 // MemCfgSet
  638. };
  639. VDATA v1280_1K_75[] =
  640. {
  641. 12800L, // Dot Freq 1
  642. 112L, // Horiz Sync Pulse
  643. 240L, // Horiz Back Porch
  644. 1280L, // X size
  645. 32L, // Horiz Front Porch
  646. 0L, // hco
  647. POSITIVE, // Horizontal Polarity
  648. 75L, // Vertical Refresh Rate in Hz.
  649. 15L, // Vertical Sync Pulse
  650. 26L, // Vertical Back Porch
  651. 1024L, // Y size
  652. 3L, // Vertical Front Porch
  653. 0L, // vco
  654. POSITIVE, // Vertical Polarity
  655. 0, // IcdSerPixClk
  656. 0xFFFFFFFF, // IcdCtrlPixClk
  657. 0, // IcdSer525Ref
  658. 0xFFFFFFFF, // IcdCtrl525Ref
  659. 0xFFFFFFFF, // 525RefClkCnt
  660. 0xFFFFFFFF, // 525VidClkFreq
  661. 0xFFFFFFFF, // MemCfgClr
  662. 0 // MemCfgSet
  663. };
  664. VDATA v1600_1200_60[] =
  665. {
  666. 16000L, // Dot Freq 1
  667. 144L, // Horiz Sync Pulse
  668. 272L, // Horiz Back Porch
  669. 1600L, // X size
  670. 32L, // Horiz Front Porch
  671. 0L, // hco
  672. NEGATIVE, // Horizontal Polarity
  673. 60L, // Vertical Refresh Rate in Hz.
  674. 8L, // Vertical Sync Pulse
  675. 49L, // Vertical Back Porch
  676. 1200L, // Y size
  677. 4L, // Vertical Front Porch
  678. 0L, // vco
  679. NEGATIVE, // Vertical Polarity
  680. 0, // IcdSerPixClk
  681. 0xFFFFFFFF, // IcdCtrlPixClk
  682. 0, // IcdSer525Ref
  683. 0xFFFFFFFF, // IcdCtrl525Ref
  684. 0xFFFFFFFF, // 525RefClkCnt
  685. 0xFFFFFFFF, // 525VidClkFreq
  686. 0xFFFFFFFF, // MemCfgClr
  687. 0 // MemCfgSet
  688. };
  689. //
  690. // P9 mode information Tables. This is the data which is returned to
  691. // the Win32 driver so that it can select the proper video mode.
  692. //
  693. P9INITDATA P9Modes[mP9ModeCount] =
  694. {
  695. {
  696. 18, // Number of entries in the structure
  697. (P9000_ID | P9100_ID),
  698. v640_480_60, // Ptr to the default video parms
  699. FALSE,
  700. { // containing the video parms.
  701. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode informtion structure
  702. m640_480_8_60, // Index used to set this mode
  703. 640, // X Resolution, in pixels
  704. 480, // Y Resolution, in pixels
  705. 640, // physical scanline byte length
  706. 1, // Number of video memory planes
  707. 8, // Number of bits per plane
  708. 60, // Screen Frequency, in Hertz.
  709. 330, // Horizontal size of screen in mm
  710. 240, // Vertical size of screen in mm
  711. 8, // # of Red bits in non-palette modes
  712. 8, // # of Green bits in non-palette modes
  713. 8, // # of Blue bits in non-palette modes
  714. 0x00000000, // Mask for Red bits in non-palette modes
  715. 0x00000000, // Mask for Green bits in non-palette modes
  716. 0x00000000, // Mask for Blue bits in non-palette modes
  717. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
  718. VIDEO_MODE_MANAGED_PALETTE, // Mode flags
  719. 0L, 0L
  720. }
  721. },
  722. {
  723. 18, // Number of entries in the structure
  724. (P9000_ID | P9100_ID),
  725. v640_480_60, // Ptr to the default video parms
  726. FALSE,
  727. { // containing the video parms.
  728. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode informtion structure
  729. m640_480_16_60, // Index used to set this mode
  730. 640, // X Resolution, in pixels
  731. 480, // Y Resolution, in pixels
  732. 640 * 2, // physical scanline byte length
  733. 1, // Number of video memory planes
  734. 16, // Number of bits per plane
  735. 60, // Screen Frequency, in Hertz.
  736. 330, // Horizontal size of screen in mm
  737. 240, // Vertical size of screen in mm
  738. 5, // # of Red bits in non-palette modes
  739. 5, // # of Green bits in non-palette modes
  740. 5, // # of Blue bits in non-palette modes
  741. 0x00007C00, // Mask for Red bits in non-palette modes
  742. 0x000003E0, // Mask for Green bits in non-palette modes
  743. 0x0000001F, // Mask for Blue bits in non-palette modes
  744. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS, // Mode flags
  745. 0L, 0L
  746. }
  747. },
  748. {
  749. 18, // Number of entries in the structure
  750. P9100_ID,
  751. v640_480_60, // Ptr to the default video parms
  752. FALSE,
  753. { // containing the video parms.
  754. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode informtion structure
  755. m640_480_24_60, // Index used to set this mode
  756. 640, // X Resolution, in pixels
  757. 480, // Y Resolution, in pixels
  758. 640 * 3, // physical scanline byte length
  759. 1, // Number of video memory planes
  760. 24, // Number of bits per plane
  761. 60, // Screen Frequency, in Hertz.
  762. 330, // Horizontal size of screen in mm
  763. 240, // Vertical size of screen in mm
  764. 8, // # of Red bits in non-palette modes
  765. 8, // # of Green bits in non-palette modes
  766. 8, // # of Blue bits in non-palette modes
  767. 0x00FF0000, // Mask for Red bits in non-palette modes
  768. 0x0000FF00, // Mask for Green bits in non-palette modes
  769. 0x000000FF, // Mask for Blue bits in non-palette modes
  770. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS, // Mode flags
  771. 0L, 0L
  772. }
  773. },
  774. {
  775. 18, // Number of entries in the structure
  776. (P9000_ID | P9100_ID),
  777. v640_480_60, // Ptr to the default video parms
  778. FALSE,
  779. { // containing the video parms.
  780. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode informtion structure
  781. m640_480_32_60, // Index used to set this mode
  782. 640, // X Resolution, in pixels
  783. 480, // Y Resolution, in pixels
  784. 640 * 4, // physical scanline byte length
  785. 1, // Number of video memory planes
  786. 32, // Number of bits per plane
  787. 60, // Screen Frequency, in Hertz.
  788. 330, // Horizontal size of screen in mm
  789. 240, // Vertical size of screen in mm
  790. 8, // # of Red bits in non-palette modes
  791. 8, // # of Green bits in non-palette modes
  792. 8, // # of Blue bits in non-palette modes
  793. 0x00FF0000, // Mask for Red bits in non-palette modes
  794. 0x0000FF00, // Mask for Green bits in non-palette modes
  795. 0x000000FF, // Mask for Blue bits in non-palette modes
  796. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS, // Mode flags
  797. 0L, 0L
  798. }
  799. },
  800. {
  801. 18, // Number of entries in the structure
  802. (P9000_ID | P9100_ID),
  803. v640_480_72, // Ptr to the default video parms
  804. FALSE,
  805. { // containing the video parms.
  806. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode informtion structure
  807. m640_480_8_72, // Index used to set this mode
  808. 640, // X Resolution, in pixels
  809. 480, // Y Resolution, in pixels
  810. 640, // physical scanline byte length
  811. 1, // Number of video memory planes
  812. 8, // Number of bits per plane
  813. 72, // Screen Frequency, in Hertz.
  814. 330, // Horizontal size of screen in mm
  815. 240, // Vertical size of screen in mm
  816. 8, // # of Red bits in non-palette modes
  817. 8, // # of Green bits in non-palette modes
  818. 8, // # of Blue bits in non-palette modes
  819. 0x00000000, // Mask for Red bits in non-palette modes
  820. 0x00000000, // Mask for Green bits in non-palette modes
  821. 0x00000000, // Mask for Blue bits in non-palette modes
  822. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
  823. VIDEO_MODE_MANAGED_PALETTE, // Mode flags
  824. 0L, 0L
  825. }
  826. },
  827. {
  828. 18, // Number of entries in the structure
  829. (P9000_ID | P9100_ID),
  830. v640_480_72, // Ptr to the default video parms
  831. FALSE,
  832. { // containing the video parms.
  833. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode informtion structure
  834. m640_480_16_72, // Index used to set this mode
  835. 640, // X Resolution, in pixels
  836. 480, // Y Resolution, in pixels
  837. 640 * 2, // physical scanline byte length
  838. 1, // Number of video memory planes
  839. 16, // Number of bits per plane
  840. 72, // Screen Frequency, in Hertz.
  841. 330, // Horizontal size of screen in mm
  842. 240, // Vertical size of screen in mm
  843. 5, // # of Red bits in non-palette modes
  844. 5, // # of Green bits in non-palette modes
  845. 5, // # of Blue bits in non-palette modes
  846. 0x00007C00, // Mask for Red bits in non-palette modes
  847. 0x000003E0, // Mask for Green bits in non-palette modes
  848. 0x0000001F, // Mask for Blue bits in non-palette modes
  849. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS, // Mode flags
  850. 0L, 0L
  851. }
  852. },
  853. {
  854. 18, // Number of entries in the structure
  855. P9100_ID,
  856. v640_480_72, // Ptr to the default video parms
  857. FALSE,
  858. { // containing the video parms.
  859. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode informtion structure
  860. m640_480_24_72, // Index used to set this mode
  861. 640, // X Resolution, in pixels
  862. 480, // Y Resolution, in pixels
  863. 640 * 3, // physical scanline byte length
  864. 1, // Number of video memory planes
  865. 24, // Number of bits per plane
  866. 72, // Screen Frequency, in Hertz.
  867. 330, // Horizontal size of screen in mm
  868. 240, // Vertical size of screen in mm
  869. 8, // # of Red bits in non-palette modes
  870. 8, // # of Green bits in non-palette modes
  871. 8, // # of Blue bits in non-palette modes
  872. 0x00FF0000, // Mask for Red bits in non-palette modes
  873. 0x0000FF00, // Mask for Green bits in non-palette modes
  874. 0x000000FF, // Mask for Blue bits in non-palette modes
  875. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS, // Mode flags
  876. 0L, 0L
  877. }
  878. },
  879. {
  880. 18, // Number of entries in the structure
  881. (P9000_ID | P9100_ID),
  882. v640_480_72, // Ptr to the default video parms
  883. FALSE,
  884. { // containing the video parms.
  885. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode informtion structure
  886. m640_480_32_72, // Index used to set this mode
  887. 640, // X Resolution, in pixels
  888. 480, // Y Resolution, in pixels
  889. 640 * 4, // physical scanline byte length
  890. 1, // Number of video memory planes
  891. 32, // Number of bits per plane
  892. 72, // Screen Frequency, in Hertz.
  893. 330, // Horizontal size of screen in mm
  894. 240, // Vertical size of screen in mm
  895. 8, // # of Red bits in non-palette modes
  896. 8, // # of Green bits in non-palette modes
  897. 8, // # of Blue bits in non-palette modes
  898. 0x00FF0000, // Mask for Red bits in non-palette modes
  899. 0x0000FF00, // Mask for Green bits in non-palette modes
  900. 0x000000FF, // Mask for Blue bits in non-palette modes
  901. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS, // Mode flags
  902. 0L, 0L
  903. }
  904. },
  905. {
  906. 18, // Number of entries in the mode set structure
  907. (P9000_ID | P9100_ID),
  908. v800_600_60, // Ptr to the default video parms
  909. FALSE,
  910. { // containing the video parms.
  911. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  912. m800_600_8_60, // Index used to set this mode
  913. 800, // X Resolution, in pixels
  914. 600, // Y Resolution, in pixels
  915. 800, // physical scanline byte length
  916. 1, // Number of video memory planes
  917. 8, // Number of bits per plane
  918. 60, // Screen Frequency, in Hertz.
  919. 330, // Horizontal size of screen in mm
  920. 240, // Vertical size of screen in mm
  921. 8, // # of Red bits in non-palette modes
  922. 8, // # of Green bits in non-palette modes
  923. 8, // # of Blue bits in non-palette modes
  924. 0x00000000, // Mask for Red bits in non-palette modes
  925. 0x00000000, // Mask for Green bits in non-palette modes
  926. 0x00000000, // Mask for Blue bits in non-palette modes
  927. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
  928. VIDEO_MODE_MANAGED_PALETTE, // Mode flags
  929. 0L, 0L
  930. }
  931. },
  932. {
  933. 18, // Number of entries in the mode set structure
  934. (P9000_ID | P9100_ID),
  935. v800_600_72, // Ptr to the default video parms
  936. FALSE,
  937. { // containing the video parms.
  938. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  939. m800_600_8_72, // Index used to set this mode
  940. 800, // X Resolution, in pixels
  941. 600, // Y Resolution, in pixels
  942. 800, // physical scanline byte length
  943. 1, // Number of video memory planes
  944. 8, // Number of bits per plane
  945. 72, // Screen Frequency, in Hertz.
  946. 330, // Horizontal size of screen in mm
  947. 240, // Vertical size of screen in mm
  948. 8, // # of Red bits in non-palette modes
  949. 8, // # of Green bits in non-palette modes
  950. 8, // # of Blue bits in non-palette modes
  951. 0x00000000, // Mask for Red bits in non-palette modes
  952. 0x00000000, // Mask for Green bits in non-palette modes
  953. 0x00000000, // Mask for Blue bits in non-palette modes
  954. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
  955. VIDEO_MODE_MANAGED_PALETTE, // Mode flags
  956. 0L, 0L
  957. }
  958. },
  959. {
  960. 18, // Number of entries in the mode set structure
  961. (P9000_ID | P9100_ID),
  962. v800_600_60, // Ptr to the default video parms
  963. FALSE,
  964. { // containing the video parms.
  965. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  966. m800_600_16_60, // Index used to set this mode
  967. 800, // X Resolution, in pixels
  968. 600, // Y Resolution, in pixels
  969. 800 * 2, // physical scanline byte length
  970. 1, // Number of video memory planes
  971. 16, // Number of bits per plane
  972. 60, // Screen Frequency, in Hertz.
  973. 330, // Horizontal size of screen in mm
  974. 240, // Vertical size of screen in mm
  975. 5, // # of Red bits in non-palette modes
  976. 5, // # of Green bits in non-palette modes
  977. 5, // # of Blue bits in non-palette modes
  978. 0x00007C00, // Mask for Red bits in non-palette modes
  979. 0x000003E0, // Mask for Green bits in non-palette modes
  980. 0x0000001F, // Mask for Blue bits in non-palette modes
  981. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS, // Mode flags
  982. 0L, 0L
  983. }
  984. },
  985. {
  986. 18, // Number of entries in the mode set structure
  987. (P9000_ID | P9100_ID),
  988. v800_600_72, // Ptr to the default video parms
  989. FALSE,
  990. { // containing the video parms.
  991. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  992. m800_600_16_72, // Index used to set this mode
  993. 800, // X Resolution, in pixels
  994. 600, // Y Resolution, in pixels
  995. 800 * 2, // physical scanline byte length
  996. 1, // Number of video memory planes
  997. 16, // Number of bits per plane
  998. 72, // Screen Frequency, in Hertz.
  999. 330, // Horizontal size of screen in mm
  1000. 240, // Vertical size of screen in mm
  1001. 5, // # of Red bits in non-palette modes
  1002. 5, // # of Green bits in non-palette modes
  1003. 5, // # of Blue bits in non-palette modes
  1004. 0x00007C00, // Mask for Red bits in non-palette modes
  1005. 0x000003E0, // Mask for Green bits in non-palette modes
  1006. 0x0000001F, // Mask for Blue bits in non-palette modes
  1007. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS, // Mode flags
  1008. 0L, 0L
  1009. }
  1010. },
  1011. {
  1012. 18, // Number of entries in the struct
  1013. P9100_ID,
  1014. v800_600_60, // Ptr to the default video parms
  1015. FALSE,
  1016. { // containing the video parms.
  1017. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  1018. m800_600_24_60, // Index used to set this mode
  1019. 800, // X Resolution, in pixels
  1020. 600, // Y Resolution, in pixels
  1021. 800 * 3, // physical scanline byte length
  1022. 1, // Number of video memory planes
  1023. 24, // Number of bits per plane
  1024. 60, // Screen Frequency, in Hertz.
  1025. 330, // Horizontal size of screen in mm
  1026. 240, // Vertical size of screen in mm
  1027. 8, // # of Red bits in non-palette modes
  1028. 8, // # of Green bits in non-palette modes
  1029. 8, // # of Blue bits in non-palette modes
  1030. 0x00FF0000, // Mask for Red bits in non-palette modes
  1031. 0x0000FF00, // Mask for Green bits in non-palette modes
  1032. 0x000000FF, // Mask for Blue bits in non-palette modes
  1033. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS,
  1034. 0L, 0L
  1035. } // Mode flags
  1036. },
  1037. {
  1038. 18, // Number of entries in the struct
  1039. P9100_ID,
  1040. v800_600_72, // Ptr to the default video parms
  1041. FALSE,
  1042. { // containing the video parms.
  1043. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  1044. m800_600_24_72, // Index used to set this mode
  1045. 800, // X Resolution, in pixels
  1046. 600, // Y Resolution, in pixels
  1047. 800 * 3, // physical scanline byte length
  1048. 1, // Number of video memory planes
  1049. 24, // Number of bits per plane
  1050. 72, // Screen Frequency, in Hertz.
  1051. 330, // Horizontal size of screen in mm
  1052. 240, // Vertical size of screen in mm
  1053. 8, // # of Red bits in non-palette modes
  1054. 8, // # of Green bits in non-palette modes
  1055. 8, // # of Blue bits in non-palette modes
  1056. 0x00FF0000, // Mask for Red bits in non-palette modes
  1057. 0x0000FF00, // Mask for Green bits in non-palette modes
  1058. 0x000000FF, // Mask for Blue bits in non-palette modes
  1059. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS,
  1060. 0L, 0L
  1061. } // Mode flags
  1062. },
  1063. {
  1064. 18, // Number of entries in the struct
  1065. (P9000_ID | P9100_ID),
  1066. v800_600_60, // Ptr to the default video parms
  1067. FALSE,
  1068. { // containing the video parms.
  1069. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  1070. m800_600_32_60, // Index used to set this mode
  1071. 800, // X Resolution, in pixels
  1072. 600, // Y Resolution, in pixels
  1073. 800 * 4, // physical scanline byte length
  1074. 1, // Number of video memory planes
  1075. 32, // Number of bits per plane
  1076. 60, // Screen Frequency, in Hertz.
  1077. 330, // Horizontal size of screen in mm
  1078. 240, // Vertical size of screen in mm
  1079. 8, // # of Red bits in non-palette modes
  1080. 8, // # of Green bits in non-palette modes
  1081. 8, // # of Blue bits in non-palette modes
  1082. 0x00FF0000, // Mask for Red bits in non-palette modes
  1083. 0x0000FF00, // Mask for Green bits in non-palette modes
  1084. 0x000000FF, // Mask for Blue bits in non-palette modes
  1085. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS,
  1086. 0L, 0L
  1087. } // Mode flags
  1088. },
  1089. {
  1090. 18, // Number of entries in the struct
  1091. (P9000_ID | P9100_ID),
  1092. v800_600_72, // Ptr to the default video parms
  1093. FALSE,
  1094. { // containing the video parms.
  1095. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  1096. m800_600_32_72, // Index used to set this mode
  1097. 800, // X Resolution, in pixels
  1098. 600, // Y Resolution, in pixels
  1099. 800 * 4, // physical scanline byte length
  1100. 1, // Number of video memory planes
  1101. 32, // Number of bits per plane
  1102. 72, // Screen Frequency, in Hertz.
  1103. 330, // Horizontal size of screen in mm
  1104. 240, // Vertical size of screen in mm
  1105. 8, // # of Red bits in non-palette modes
  1106. 8, // # of Green bits in non-palette modes
  1107. 8, // # of Blue bits in non-palette modes
  1108. 0x00FF0000, // Mask for Red bits in non-palette modes
  1109. 0x0000FF00, // Mask for Green bits in non-palette modes
  1110. 0x000000FF, // Mask for Blue bits in non-palette modes
  1111. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS,
  1112. 0L, 0L
  1113. } // Mode flags
  1114. },
  1115. {
  1116. 18, // Number of entries in the struct
  1117. (P9000_ID | P9100_ID),
  1118. v1K_768_60, // Ptr to the default video parms
  1119. FALSE,
  1120. { // containing the video parms.
  1121. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  1122. m1K_768_8_60, // Index used to set this mode
  1123. 1024, // X Resolution, in pixels
  1124. 768, // Y Resolution, in pixels
  1125. 1024, // physical scanline byte length
  1126. 1, // Number of video memory planes
  1127. 8, // Number of bits per plane
  1128. 60, // Screen Frequency, in Hertz.
  1129. 330, // Horizontal size of screen in mm
  1130. 240, // Vertical size of screen in mm
  1131. 8, // # of Red bits in non-palette modes
  1132. 8, // # of Green bits in non-palette modes
  1133. 8, // # of Blue bits in non-palette modes
  1134. 0x00000000, // Mask for Red bits in non-palette modes
  1135. 0x00000000, // Mask for Green bits in non-palette modes
  1136. 0x00000000, // Mask for Blue bits in non-palette modes
  1137. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
  1138. VIDEO_MODE_MANAGED_PALETTE, // Mode flags
  1139. 0L, 0L
  1140. }
  1141. },
  1142. {
  1143. 18, // Number of entries in the struct
  1144. (P9000_ID | P9100_ID),
  1145. v1K_768_70, // Ptr to the default video parms
  1146. FALSE,
  1147. { // containing the video parms.
  1148. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  1149. m1K_768_8_70, // Index used to set this mode
  1150. 1024, // X Resolution, in pixels
  1151. 768, // Y Resolution, in pixels
  1152. 1024, // physical scanline byte length
  1153. 1, // Number of video memory planes
  1154. 8, // Number of bits per plane
  1155. 70, // Screen Frequency, in Hertz.
  1156. 330, // Horizontal size of screen in mm
  1157. 240, // Vertical size of screen in mm
  1158. 8, // # of Red bits in non-palette modes
  1159. 8, // # of Green bits in non-palette modes
  1160. 8, // # of Blue bits in non-palette modes
  1161. 0x00000000, // Mask for Red bits in non-palette modes
  1162. 0x00000000, // Mask for Green bits in non-palette modes
  1163. 0x00000000, // Mask for Blue bits in non-palette modes
  1164. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
  1165. VIDEO_MODE_MANAGED_PALETTE, // Mode flags
  1166. 0L, 0L
  1167. }
  1168. },
  1169. {
  1170. 18, // Number of entries in the struct
  1171. (P9000_ID | P9100_ID),
  1172. v1K_768_60, // Ptr to the default video parms
  1173. FALSE,
  1174. { // containing the video parms.
  1175. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  1176. m1K_768_16_60, // Index used to set this mode
  1177. 1024, // X Resolution, in pixels
  1178. 768, // Y Resolution, in pixels
  1179. 1024 * 2, // physical scanline byte length
  1180. 1, // Number of video memory planes
  1181. 16, // Number of bits per plane
  1182. 60, // Screen Frequency, in Hertz.
  1183. 330, // Horizontal size of screen in mm
  1184. 240, // Vertical size of screen in mm
  1185. 5, // # of Red bits in non-palette modes
  1186. 5, // # of Green bits in non-palette modes
  1187. 5, // # of Blue bits in non-palette modes
  1188. 0x00007C00, // Mask for Red bits in non-palette modes
  1189. 0x000003E0, // Mask for Green bits in non-palette modes
  1190. 0x0000001F, // Mask for Blue bits in non-palette modes
  1191. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS,
  1192. 0L, 0L
  1193. } // Mode flags
  1194. },
  1195. {
  1196. 18, // Number of entries in the struct
  1197. (P9000_ID | P9100_ID),
  1198. v1K_768_70, // Ptr to the default video parms
  1199. FALSE,
  1200. { // containing the video parms.
  1201. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  1202. m1K_768_16_70, // Index used to set this mode
  1203. 1024, // X Resolution, in pixels
  1204. 768, // Y Resolution, in pixels
  1205. 1024 * 2, // physical scanline byte length
  1206. 1, // Number of video memory planes
  1207. 16, // Number of bits per plane
  1208. 70, // Screen Frequency, in Hertz.
  1209. 330, // Horizontal size of screen in mm
  1210. 240, // Vertical size of screen in mm
  1211. 5, // # of Red bits in non-palette modes
  1212. 5, // # of Green bits in non-palette modes
  1213. 5, // # of Blue bits in non-palette modes
  1214. 0x00007C00, // Mask for Red bits in non-palette modes
  1215. 0x000003E0, // Mask for Green bits in non-palette modes
  1216. 0x0000001F, // Mask for Blue bits in non-palette modes
  1217. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS,
  1218. 0L, 0L
  1219. } // Mode flags
  1220. },
  1221. {
  1222. 18, // Number of entries in the struct
  1223. P9100_ID,
  1224. v1K_768_60, // Ptr to the default video parms
  1225. FALSE,
  1226. { // containing the video parms.
  1227. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  1228. m1K_768_24_60, // Index used to set this mode
  1229. 1024, // X Resolution, in pixels
  1230. 768, // Y Resolution, in pixels
  1231. 1024 * 3, // physical scanline byte length
  1232. 1, // Number of video memory planes
  1233. 24, // Number of bits per plane
  1234. 60, // Screen Frequency, in Hertz.
  1235. 330, // Horizontal size of screen in mm
  1236. 240, // Vertical size of screen in mm
  1237. 8, // # of Red bits in non-palette modes
  1238. 8, // # of Green bits in non-palette modes
  1239. 8, // # of Blue bits in non-palette modes
  1240. 0x00FF0000, // Mask for Red bits in non-palette modes
  1241. 0x0000FF00, // Mask for Green bits in non-palette modes
  1242. 0x000000FF, // Mask for Blue bits in non-palette modes
  1243. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS,
  1244. 0L, 0L
  1245. } // Mode flags
  1246. },
  1247. {
  1248. 18, // Number of entries in the struct
  1249. P9100_ID,
  1250. v1K_768_70, // Ptr to the default video parms
  1251. FALSE,
  1252. { // containing the video parms.
  1253. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  1254. m1K_768_24_70, // Index used to set this mode
  1255. 1024, // X Resolution, in pixels
  1256. 768, // Y Resolution, in pixels
  1257. 1024 * 3, // physical scanline byte length
  1258. 1, // Number of video memory planes
  1259. 24, // Number of bits per plane
  1260. 70, // Screen Frequency, in Hertz.
  1261. 330, // Horizontal size of screen in mm
  1262. 240, // Vertical size of screen in mm
  1263. 8, // # of Red bits in non-palette modes
  1264. 8, // # of Green bits in non-palette modes
  1265. 8, // # of Blue bits in non-palette modes
  1266. 0x00FF0000, // Mask for Red bits in non-palette modes
  1267. 0x0000FF00, // Mask for Green bits in non-palette modes
  1268. 0x000000FF, // Mask for Blue bits in non-palette modes
  1269. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS,
  1270. 0L, 0L
  1271. } // Mode flags
  1272. },
  1273. {
  1274. 18, // Number of entries in the struct
  1275. P9100_ID,
  1276. v1K_768_60, // Ptr to the default video parms
  1277. FALSE,
  1278. { // containing the video parms.
  1279. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  1280. m1K_768_32_60, // Index used to set this mode
  1281. 1024, // X Resolution, in pixels
  1282. 768, // Y Resolution, in pixels
  1283. 1024 * 4, // physical scanline byte length
  1284. 1, // Number of video memory planes
  1285. 32, // Number of bits per plane
  1286. 60, // Screen Frequency, in Hertz.
  1287. 330, // Horizontal size of screen in mm
  1288. 240, // Vertical size of screen in mm
  1289. 8, // # of Red bits in non-palette modes
  1290. 8, // # of Green bits in non-palette modes
  1291. 8, // # of Blue bits in non-palette modes
  1292. 0x00FF0000, // Mask for Red bits in non-palette modes
  1293. 0x0000FF00, // Mask for Green bits in non-palette modes
  1294. 0x000000FF, // Mask for Blue bits in non-palette modes
  1295. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS,
  1296. 0L, 0L
  1297. } // Mode flags
  1298. },
  1299. {
  1300. 18, // Number of entries in the struct
  1301. P9100_ID,
  1302. v1K_768_70, // Ptr to the default video parms
  1303. FALSE,
  1304. { // containing the video parms.
  1305. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  1306. m1K_768_32_70, // Index used to set this mode
  1307. 1024, // X Resolution, in pixels
  1308. 768, // Y Resolution, in pixels
  1309. 1024 * 4, // physical scanline byte length
  1310. 1, // Number of video memory planes
  1311. 32, // Number of bits per plane
  1312. 70, // Screen Frequency, in Hertz.
  1313. 330, // Horizontal size of screen in mm
  1314. 240, // Vertical size of screen in mm
  1315. 8, // # of Red bits in non-palette modes
  1316. 8, // # of Green bits in non-palette modes
  1317. 8, // # of Blue bits in non-palette modes
  1318. 0x00FF0000, // Mask for Red bits in non-palette modes
  1319. 0x0000FF00, // Mask for Green bits in non-palette modes
  1320. 0x000000FF, // Mask for Blue bits in non-palette modes
  1321. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS,
  1322. 0L, 0L
  1323. } // Mode flags
  1324. },
  1325. {
  1326. 18, // Number of entries in the struct
  1327. P9000_ID,
  1328. v1280_1K_55, // Ptr to the default video parms
  1329. FALSE,
  1330. { // containing the video parms.
  1331. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  1332. m1280_1K_8_55, // Index used to set this mode
  1333. 1280, // X Resolution, in pixels
  1334. 1024, // Y Resolution, in pixels
  1335. 1280, // physical scanline byte length
  1336. 1, // Number of video memory planes
  1337. 8, // Number of bits per plane
  1338. 55, // Screen Frequency, in Hertz.
  1339. 330, // Horizontal size of screen in mm
  1340. 240, // Vertical size of screen in mm
  1341. 8, // # of Red bits in non-palette modes
  1342. 8, // # of Green bits in non-palette modes
  1343. 8, // # of Blue bits in non-palette modes
  1344. 0x00000000, // Mask for Red bits in non-palette modes
  1345. 0x00000000, // Mask for Green bits in non-palette modes
  1346. 0x00000000, // Mask for Blue bits in non-palette modes
  1347. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
  1348. VIDEO_MODE_MANAGED_PALETTE, // Mode flags
  1349. 0L, 0L
  1350. }
  1351. },
  1352. {
  1353. 18, // Number of entries in the struct
  1354. (P9000_ID | P9100_ID),
  1355. v1280_1K_60, // Ptr to the default video parms
  1356. FALSE,
  1357. { // containing the video parms.
  1358. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  1359. m1280_1K_8_60, // Index used to set this mode
  1360. 1280, // X Resolution, in pixels
  1361. 1024, // Y Resolution, in pixels
  1362. 1280, // physical scanline byte length
  1363. 1, // Number of video memory planes
  1364. 8, // Number of bits per plane
  1365. 60, // Screen Frequency, in Hertz.
  1366. 330, // Horizontal size of screen in mm
  1367. 240, // Vertical size of screen in mm
  1368. 8, // # of Red bits in non-palette modes
  1369. 8, // # of Green bits in non-palette modes
  1370. 8, // # of Blue bits in non-palette modes
  1371. 0x00000000, // Mask for Red bits in non-palette modes
  1372. 0x00000000, // Mask for Green bits in non-palette modes
  1373. 0x00000000, // Mask for Blue bits in non-palette modes
  1374. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
  1375. VIDEO_MODE_MANAGED_PALETTE, // Mode flags
  1376. 0L, 0L
  1377. }
  1378. },
  1379. {
  1380. 18, // Number of entries in the struct
  1381. (P9000_ID | P9100_ID),
  1382. v1280_1K_74, // Ptr to the default video parms
  1383. FALSE,
  1384. { // containing the video parms.
  1385. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  1386. m1280_1K_8_74, // Index used to set this mode
  1387. 1280, // X Resolution, in pixels
  1388. 1024, // Y Resolution, in pixels
  1389. 1280, // physical scanline byte length
  1390. 1, // Number of video memory planes
  1391. 8, // Number of bits per plane
  1392. 74, // Screen Frequency, in Hertz.
  1393. 330, // Horizontal size of screen in mm
  1394. 240, // Vertical size of screen in mm
  1395. 8, // # of Red bits in non-palette modes
  1396. 8, // # of Green bits in non-palette modes
  1397. 8, // # of Blue bits in non-palette modes
  1398. 0x00000000, // Mask for Red bits in non-palette modes
  1399. 0x00000000, // Mask for Green bits in non-palette modes
  1400. 0x00000000, // Mask for Blue bits in non-palette modes
  1401. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
  1402. VIDEO_MODE_MANAGED_PALETTE, // Mode flags
  1403. 0L, 0L
  1404. }
  1405. },
  1406. {
  1407. 18, // Number of entries in the struct
  1408. (P9000_ID | P9100_ID),
  1409. v1280_1K_75, // Ptr to the default video parms
  1410. FALSE,
  1411. { // containing the video parms.
  1412. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  1413. m1280_1K_8_75, // Index used to set this mode
  1414. 1280, // X Resolution, in pixels
  1415. 1024, // Y Resolution, in pixels
  1416. 1280, // physical scanline byte length
  1417. 1, // Number of video memory planes
  1418. 8, // Number of bits per plane
  1419. 75, // Screen Frequency, in Hertz.
  1420. 330, // Horizontal size of screen in mm
  1421. 240, // Vertical size of screen in mm
  1422. 8, // # of Red bits in non-palette modes
  1423. 8, // # of Green bits in non-palette modes
  1424. 8, // # of Blue bits in non-palette modes
  1425. 0x00000000, // Mask for Red bits in non-palette modes
  1426. 0x00000000, // Mask for Green bits in non-palette modes
  1427. 0x00000000, // Mask for Blue bits in non-palette modes
  1428. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
  1429. VIDEO_MODE_MANAGED_PALETTE, // Mode flags
  1430. 0L, 0L
  1431. }
  1432. },
  1433. {
  1434. 18, // Number of entries in the struct
  1435. P9100_ID,
  1436. v1280_1K_60, // Ptr to the default video parms
  1437. FALSE,
  1438. { // containing the video parms.
  1439. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  1440. m1280_1K_16_60, // Index used to set this mode
  1441. 1280, // X Resolution, in pixels
  1442. 1024, // Y Resolution, in pixels
  1443. 1280 * 2, // physical scanline byte length
  1444. 1, // Number of video memory planes
  1445. 16, // Number of bits per plane
  1446. 60, // Screen Frequency, in Hertz.
  1447. 330, // Horizontal size of screen in mm
  1448. 240, // Vertical size of screen in mm
  1449. 5, // # of Red bits in non-palette modes
  1450. 5, // # of Green bits in non-palette modes
  1451. 5, // # of Blue bits in non-palette modes
  1452. 0x00007C00, // Mask for Red bits in non-palette modes
  1453. 0x000003E0, // Mask for Green bits in non-palette modes
  1454. 0x0000001F, // Mask for Blue bits in non-palette modes
  1455. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS,
  1456. 0L, 0L
  1457. }
  1458. },
  1459. {
  1460. 18, // Number of entries in the struct
  1461. P9100_ID,
  1462. v1280_1K_74, // Ptr to the default video parms
  1463. FALSE,
  1464. { // containing the video parms.
  1465. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  1466. m1280_1K_16_74, // Index used to set this mode
  1467. 1280, // X Resolution, in pixels
  1468. 1024, // Y Resolution, in pixels
  1469. 1280 * 2, // physical scanline byte length
  1470. 1, // Number of video memory planes
  1471. 16, // Number of bits per plane
  1472. 74, // Screen Frequency, in Hertz.
  1473. 330, // Horizontal size of screen in mm
  1474. 240, // Vertical size of screen in mm
  1475. 5, // # of Red bits in non-palette modes
  1476. 5, // # of Green bits in non-palette modes
  1477. 5, // # of Blue bits in non-palette modes
  1478. 0x00007C00, // Mask for Red bits in non-palette modes
  1479. 0x000003E0, // Mask for Green bits in non-palette modes
  1480. 0x0000001F, // Mask for Blue bits in non-palette modes
  1481. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS,
  1482. 0L, 0L
  1483. }
  1484. },
  1485. {
  1486. 18, // Number of entries in the struct
  1487. P9100_ID,
  1488. v1280_1K_75, // Ptr to the default video parms
  1489. FALSE,
  1490. { // containing the video parms.
  1491. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  1492. m1280_1K_16_75, // Index used to set this mode
  1493. 1280, // X Resolution, in pixels
  1494. 1024, // Y Resolution, in pixels
  1495. 1280 * 2, // physical scanline byte length
  1496. 1, // Number of video memory planes
  1497. 16, // Number of bits per plane
  1498. 75, // Screen Frequency, in Hertz.
  1499. 330, // Horizontal size of screen in mm
  1500. 240, // Vertical size of screen in mm
  1501. 5, // # of Red bits in non-palette modes
  1502. 5, // # of Green bits in non-palette modes
  1503. 5, // # of Blue bits in non-palette modes
  1504. 0x00007C00, // Mask for Red bits in non-palette modes
  1505. 0x000003E0, // Mask for Green bits in non-palette modes
  1506. 0x0000001F, // Mask for Blue bits in non-palette modes
  1507. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS,
  1508. 0L, 0L
  1509. }
  1510. },
  1511. {
  1512. 18, // Number of entries in the struct
  1513. P9100_ID,
  1514. v1280_1K_60, // Ptr to the default video parms
  1515. FALSE,
  1516. { // containing the video parms.
  1517. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  1518. m1280_1K_24_60, // Index used to set this mode
  1519. 1280, // X Resolution, in pixels
  1520. 1024, // Y Resolution, in pixels
  1521. 1280 * 3, // physical scanline byte length
  1522. 1, // Number of video memory planes
  1523. 24, // Number of bits per plane
  1524. 60, // Screen Frequency, in Hertz.
  1525. 330, // Horizontal size of screen in mm
  1526. 240, // Vertical size of screen in mm
  1527. 8, // # of Red bits in non-palette modes
  1528. 8, // # of Green bits in non-palette modes
  1529. 8, // # of Blue bits in non-palette modes
  1530. 0x00FF0000, // Mask for Red bits in non-palette modes
  1531. 0x0000FF00, // Mask for Green bits in non-palette modes
  1532. 0x000000FF, // Mask for Blue bits in non-palette modes
  1533. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS, // Mode flags
  1534. 0L, 0L
  1535. }
  1536. },
  1537. {
  1538. 18, // Number of entries in the struct
  1539. P9100_ID,
  1540. v1280_1K_74, // Ptr to the default video parms
  1541. FALSE,
  1542. { // containing the video parms.
  1543. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  1544. m1280_1K_24_74, // Index used to set this mode
  1545. 1280, // X Resolution, in pixels
  1546. 1024, // Y Resolution, in pixels
  1547. 1280 * 3, // physical scanline byte length
  1548. 1, // Number of video memory planes
  1549. 24, // Number of bits per plane
  1550. 74, // Screen Frequency, in Hertz.
  1551. 330, // Horizontal size of screen in mm
  1552. 240, // Vertical size of screen in mm
  1553. 8, // # of Red bits in non-palette modes
  1554. 8, // # of Green bits in non-palette modes
  1555. 8, // # of Blue bits in non-palette modes
  1556. 0x00FF0000, // Mask for Red bits in non-palette modes
  1557. 0x0000FF00, // Mask for Green bits in non-palette modes
  1558. 0x000000FF, // Mask for Blue bits in non-palette modes
  1559. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS, // Mode flags
  1560. 0L, 0L
  1561. }
  1562. },
  1563. {
  1564. 18, // Number of entries in the struct
  1565. P9100_ID,
  1566. v1280_1K_75, // Ptr to the default video parms
  1567. FALSE,
  1568. { // containing the video parms.
  1569. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  1570. m1280_1K_24_75, // Index used to set this mode
  1571. 1280, // X Resolution, in pixels
  1572. 1024, // Y Resolution, in pixels
  1573. 1280 * 3, // physical scanline byte length
  1574. 1, // Number of video memory planes
  1575. 24, // Number of bits per plane
  1576. 75, // Screen Frequency, in Hertz.
  1577. 330, // Horizontal size of screen in mm
  1578. 240, // Vertical size of screen in mm
  1579. 8, // # of Red bits in non-palette modes
  1580. 8, // # of Green bits in non-palette modes
  1581. 8, // # of Blue bits in non-palette modes
  1582. 0x00FF0000, // Mask for Red bits in non-palette modes
  1583. 0x0000FF00, // Mask for Green bits in non-palette modes
  1584. 0x000000FF, // Mask for Blue bits in non-palette modes
  1585. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS, // Mode flags
  1586. 0L, 0L
  1587. }
  1588. },
  1589. {
  1590. 18, // Number of entries in the struct
  1591. (P9000_ID | P9100_ID),
  1592. v1600_1200_60, // Ptr to the default video parms
  1593. FALSE,
  1594. { // containing the video parms.
  1595. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  1596. m1600_1200_8_60, // Index used to set this mode
  1597. 1600, // X Resolution, in pixels
  1598. 1200, // Y Resolution, in pixels
  1599. 1600, // physical scanline byte length
  1600. 1, // Number of video memory planes
  1601. 8, // Number of bits per plane
  1602. 60, // Screen Frequency, in Hertz.
  1603. 330, // Horizontal size of screen in mm
  1604. 240, // Vertical size of screen in mm
  1605. 8, // # of Red bits in non-palette modes
  1606. 8, // # of Green bits in non-palette modes
  1607. 8, // # of Blue bits in non-palette modes
  1608. 0x00000000, // Mask for Red bits in non-palette modes
  1609. 0x00000000, // Mask for Green bits in non-palette modes
  1610. 0x00000000, // Mask for Blue bits in non-palette modes
  1611. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
  1612. VIDEO_MODE_MANAGED_PALETTE, // Mode flags
  1613. 0L, 0L
  1614. }
  1615. },
  1616. {
  1617. 18, // Number of entries in the struct
  1618. P9100_ID,
  1619. v1600_1200_60, // Ptr to the default video parms
  1620. FALSE,
  1621. { // containing the video parms.
  1622. sizeof(VIDEO_MODE_INFORMATION), // Size of the mode info struct
  1623. m1600_1200_16_60, // Index used to set this mode
  1624. 1600, // X Resolution, in pixels
  1625. 1200, // Y Resolution, in pixels
  1626. 1600 * 2, // physical scanline byte length
  1627. 1, // Number of video memory planes
  1628. 16, // Number of bits per plane
  1629. 60, // Screen Frequency, in Hertz.
  1630. 330, // Horizontal size of screen in mm
  1631. 240, // Vertical size of screen in mm
  1632. 5, // # of Red bits in non-palette modes
  1633. 5, // # of Green bits in non-palette modes
  1634. 5, // # of Blue bits in non-palette modes
  1635. 0x00007C00, // Mask for Red bits in non-palette modes
  1636. 0x000003E0, // Mask for Green bits in non-palette modes
  1637. 0x0000001F, // Mask for Blue bits in non-palette modes
  1638. VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS,
  1639. 0L, 0L
  1640. }
  1641. }
  1642. };
  1643. //
  1644. // Dummy variables used as destination reads of the P9 VRTC register reads.
  1645. // They are used to detect vertical retrace.
  1646. //
  1647. ULONG ulStrtScan;
  1648. ULONG ulCurScan;