Source code of Windows XP (NT5)

3053 lines
68 KiB

  1. /*++
  2. Copyright (c) 1990 Microsoft Corporation
  3. Module Name:
  4. mi386.h
  5. Abstract:
  6. This module contains the private data structures and procedure
  7. prototypes for the hardware dependent portion of the
  8. memory management system.
  9. This module is specifically tailored for the x86.
  10. Author:
  11. Lou Perazzoli (loup) 6-Jan-1990
  12. Landy Wang (landyw) 02-June-1997
  13. Revision History:
  14. --*/
  15. /*++
  16. Virtual Memory Layout on x86 is:
  17. +------------------------------------+
  18. 00000000 | |
  19. | |
  20. | |
  21. | User Mode Addresses |
  22. | |
  23. | All pages within this range |
  24. | are potentially accessible while |
  25. | the CPU is in USER mode. |
  26. | |
  27. | |
  28. +------------------------------------+
  29. 7ffff000 | 64k No Access Area |
  30. +------------------------------------+
  31. 80000000 | |
  32. | NTLDR loads the kernel, HAL and |
  33. | boot drivers here. The kernel |
  34. | then relocates the drivers to the |
  35. | system PTE area. |
  36. | |
  37. | Kernel mode access only. |
  38. | |
  39. | When possible, the PFN database & |
  40. | initial non paged pool is built |
  41. | here using large page mappings. |
  42. | |
  43. +------------------------------------+
  44. | |
  45. | Additional system PTEs, system |
  46. | cache or special pooling |
  47. | |
  48. +------------------------------------+
  49. | |
  50. | System mapped views. |
  51. | |
  52. +------------------------------------+
  53. | |
  54. | Session space. |
  55. | |
  56. +------------------------------------+
  57. C0000000 | Page Table Pages mapped through |
  58. | this 4mb region |
  59. | Kernel mode access only. |
  60. | |
  61. +------------------------------------+
  62. C0400000 | HyperSpace - working set lists |
  63. | and per process memory management |
  64. | structures mapped in this 4mb |
  65. | region. |
  66. | Kernel mode access only. |
  67. +------------------------------------+
  68. C0800000 | NO ACCESS AREA (4MB) |
  69. | |
  70. +------------------------------------+
  71. C0C00000 | System Cache Structures |
  72. | reside in this 4mb region |
  73. | Kernel mode access only. |
  74. +------------------------------------+
  75. C1000000 | System cache resides here. |
  76. | Kernel mode access only. |
  77. | |
  78. | |
  79. +------------------------------------+
  80. E1000000 | Start of paged system area |
  81. | Kernel mode access only. |
  82. | |
  83. | |
  84. +------------------------------------+
  85. | |
  86. | System PTE area - for mapping |
  87. | kernel thread stacks and MDLs |
  88. | that require system VAs. |
  89. | Kernel mode access only. |
  90. | |
  91. +------------------------------------+
  92. | |
  93. | NonPaged System area |
  94. | Kernel mode access only. |
  95. | |
  96. +------------------------------------+
  97. FFBE0000 | Crash Dump Driver area |
  98. | Kernel mode access only. |
  99. +------------------------------------+
  100. FFC00000 | Last 4mb reserved for HAL usage |
  101. +------------------------------------+
  102. --*/
  103. #define _MI_PAGING_LEVELS 2
  104. #define IMAGE_FILE_MACHINE_NATIVE IMAGE_FILE_MACHINE_I386
  105. #if !defined(_X86PAE_)
  106. //
  107. // Define empty list markers.
  108. //
  109. #define MM_EMPTY_LIST ((ULONG)0xFFFFFFFF) //
  110. #define MM_EMPTY_PTE_LIST ((ULONG)0xFFFFF) // N.B. tied to MMPTE definition
  111. #define MI_PTE_BASE_FOR_LOWEST_KERNEL_ADDRESS (MiGetPteAddress (0x00000000))
  112. #define MM_SESSION_SPACE_DEFAULT (0xA0000000)
  113. #define MM_SESSION_SPACE_DEFAULT_END (0xC0000000)
  114. //
  115. // This is the size of the region used by the loader.
  116. //
  117. extern ULONG_PTR MmBootImageSize;
  118. //
  119. // PAGE_SIZE for x86 is 4k, virtual page is 20 bits with a PAGE_SHIFT
  120. // byte offset.
  121. //
  122. #define MM_VIRTUAL_PAGE_FILLER 0
  123. #define MM_VIRTUAL_PAGE_SIZE 20
  124. //
  125. // Address space layout definitions.
  126. //
  127. #define MM_KSEG0_BASE ((ULONG)0x80000000)
  128. #define MM_KSEG2_BASE ((ULONG)0xA0000000)
  129. #define MM_PAGES_IN_KSEG0 ((MM_KSEG2_BASE - MM_KSEG0_BASE) >> PAGE_SHIFT)
  130. #define CODE_START MM_KSEG0_BASE
  131. #define CODE_END MM_KSEG2_BASE
  132. #define MM_SYSTEM_SPACE_START (0xC0800000)
  133. #define MM_SYSTEM_SPACE_END (0xFFFFFFFF)
  134. #define HYPER_SPACE ((PVOID)0xC0400000)
  135. #define HYPER_SPACE_END (0xC07fffff)
  136. #define MM_SYSTEM_VIEW_START (0xA0000000)
  137. #define MM_SYSTEM_VIEW_SIZE (16*1024*1024)
  138. #define MM_LOWEST_4MB_START ((32*1024*1024)/PAGE_SIZE) //32mb
  139. #define MM_DEFAULT_4MB_START (((1024*1024)/PAGE_SIZE)*4096) //4gb
  140. #define MM_HIGHEST_4MB_START (((1024*1024)/PAGE_SIZE)*4096) //4gb
  141. #define MM_USER_ADDRESS_RANGE_LIMIT 0xFFFFFFFF // user address range limit
  142. #define MM_MAXIMUM_ZERO_BITS 21 // maximum number of zero bits
  143. //
  144. // Define the start and maximum size for the system cache.
  145. // Maximum size is normally 512MB, but can be up to 512MB + 448MB = 960MB for
  146. // large system cache machines.
  147. //
  148. #define MM_SYSTEM_CACHE_WORKING_SET (0xC0C00000)
  149. #define MM_SYSTEM_CACHE_START (0xC1000000)
  150. #define MM_SYSTEM_CACHE_END (0xE1000000)
  151. //
  152. // Various resources like additional system PTEs or system cache views, etc,
  153. // can be allocated out of this virtual address range.
  154. //
  155. extern ULONG MiExtraResourceStart;
  156. extern ULONG MiExtraResourceEnd;
  157. extern ULONG_PTR MiUseMaximumSystemSpace;
  158. extern ULONG_PTR MiUseMaximumSystemSpaceEnd;
  159. extern ULONG MiNumberOfExtraSystemPdes;
  160. extern ULONG MiNumberOfExtraSystemPdes3;
  161. extern ULONG MiMaximumSystemExtraSystemPdes;
  162. extern ULONG MiMaximumSystemCacheSizeExtra;
  163. extern PVOID MiSystemCacheStartExtra;
  164. extern PVOID MiSystemCacheEndExtra;
  165. #define MM_SYSTEM_CACHE_END_EXTRA (0xC0000000)
  166. #define MM_PAGED_POOL_START (MmPagedPoolStart)
  167. #define MM_DEFAULT_PAGED_POOL_START (0xE1000000)
  168. #define MM_LOWEST_NONPAGED_SYSTEM_START ((PVOID)(0xEB000000))
  169. #define MmProtopte_Base ((ULONG)MmPagedPoolStart)
  170. #define MM_NONPAGED_POOL_END ((PVOID)(0xFFBE0000))
  171. #define MM_CRASH_DUMP_VA ((PVOID)(0xFFBE0000))
  172. #define MM_DEBUG_VA ((PVOID)0xFFBFF000)
  173. #define NON_PAGED_SYSTEM_END ((ULONG)0xFFFFFFF0) //quadword aligned.
  174. extern BOOLEAN MiWriteCombiningPtes;
  175. LOGICAL
  176. MiRecoverExtraPtes (
  177. VOID
  178. );
  179. //
  180. // Define absolute minimum and maximum count for system PTEs.
  181. //
  182. #define MM_MINIMUM_SYSTEM_PTES 7000
  183. #define MM_MAXIMUM_SYSTEM_PTES 50000
  184. #define MM_DEFAULT_SYSTEM_PTES 11000
  185. //
  186. // Pool limits
  187. //
  188. //
  189. // The maximum amount of nonpaged pool that can be initially created.
  190. //
  191. #define MM_MAX_INITIAL_NONPAGED_POOL ((ULONG)(128*1024*1024))
  192. //
  193. // The total amount of nonpaged pool (initial pool + expansion).
  194. //
  195. #define MM_MAX_ADDITIONAL_NONPAGED_POOL ((ULONG)(128*1024*1024))
  196. //
  197. // The maximum amount of paged pool that can be created.
  198. //
  199. #define MM_MAX_PAGED_POOL ((ULONG)MM_NONPAGED_POOL_END - (ULONG)MM_PAGED_POOL_START)
  200. #define MM_MAX_TOTAL_POOL (((ULONG)MM_NONPAGED_POOL_END) - ((ULONG)(MM_PAGED_POOL_START)))
  201. //
  202. // Structure layout definitions.
  203. //
  204. #define MM_PROTO_PTE_ALIGNMENT ((ULONG)PAGE_SIZE)
  205. #define PAGE_DIRECTORY_MASK ((ULONG)0x003FFFFF)
  206. #define MM_VA_MAPPED_BY_PDE (0x400000)
  207. #define LOWEST_IO_ADDRESS 0xa0000
  208. #define PTE_SHIFT 2
  209. //
  210. // The number of bits in a physical address.
  211. //
  212. #define PHYSICAL_ADDRESS_BITS 32
  213. #define MM_MAXIMUM_NUMBER_OF_COLORS (1)
  214. //
  215. // i386 does not require support for colored pages.
  216. //
  217. #define MM_NUMBER_OF_COLORS (1)
  218. //
  219. // Mask for obtaining color from a physical page number.
  220. //
  221. #define MM_COLOR_MASK (0)
  222. //
  223. // Boundary for aligned pages of like color upon.
  224. //
  225. #define MM_COLOR_ALIGNMENT (0)
  226. //
  227. // Mask for isolating color from virtual address.
  228. //
  229. #define MM_COLOR_MASK_VIRTUAL (0)
  230. //
  231. // Define 256k worth of secondary colors.
  232. //
  233. #define MM_SECONDARY_COLORS_DEFAULT (64)
  234. #define MM_SECONDARY_COLORS_MIN (2)
  235. #define MM_SECONDARY_COLORS_MAX (1024)
  236. //
  237. // Maximum number of paging files.
  238. //
  239. #define MAX_PAGE_FILES 16
  240. //
  241. // Hyper space definitions.
  242. //
  243. #define FIRST_MAPPING_PTE ((ULONG)0xC0400000)
  244. #define NUMBER_OF_MAPPING_PTES 255
  245. #define LAST_MAPPING_PTE \
  246. ((ULONG)((ULONG)FIRST_MAPPING_PTE + (NUMBER_OF_MAPPING_PTES * PAGE_SIZE)))
  247. #define COMPRESSION_MAPPING_PTE ((PMMPTE)((ULONG)LAST_MAPPING_PTE + PAGE_SIZE))
  248. #define IMAGE_MAPPING_PTE ((PMMPTE)((ULONG)COMPRESSION_MAPPING_PTE + PAGE_SIZE))
  249. #define NUMBER_OF_ZEROING_PTES 32
  250. //
  251. // This bitmap consumes 4K when booted /2GB and 6K when booted /3GB, thus
  252. // the working set list start is variable.
  253. //
  254. #define VAD_BITMAP_SPACE ((PVOID)((ULONG)IMAGE_MAPPING_PTE + PAGE_SIZE))
  255. #define WORKING_SET_LIST MmWorkingSetList
  256. #define MM_MAXIMUM_WORKING_SET MiMaximumWorkingSet
  257. extern ULONG MiMaximumWorkingSet;
  258. #define MmWsle ((PMMWSLE)((PUCHAR)WORKING_SET_LIST + sizeof(MMWSL)))
  259. #define MM_WORKING_SET_END ((ULONG)0xC07FF000)
  260. //
  261. // Define masks for fields within the PTE.
  262. ///
  263. #define MM_PTE_VALID_MASK 0x1
  264. #if defined(NT_UP)
  265. #define MM_PTE_WRITE_MASK 0x2
  266. #else
  267. #define MM_PTE_WRITE_MASK 0x800
  268. #endif
  269. #define MM_PTE_OWNER_MASK 0x4
  270. #define MM_PTE_WRITE_THROUGH_MASK 0x8
  271. #define MM_PTE_CACHE_DISABLE_MASK 0x10
  272. #define MM_PTE_ACCESS_MASK 0x20
  273. #if defined(NT_UP)
  274. #define MM_PTE_DIRTY_MASK 0x40
  275. #else
  276. #define MM_PTE_DIRTY_MASK 0x42
  277. #endif
  278. #define MM_PTE_LARGE_PAGE_MASK 0x80
  279. #define MM_PTE_GLOBAL_MASK 0x100
  280. #define MM_PTE_COPY_ON_WRITE_MASK 0x200
  281. #define MM_PTE_PROTOTYPE_MASK 0x400
  282. #define MM_PTE_TRANSITION_MASK 0x800
  283. //
  284. // Bit fields to or into PTE to make a PTE valid based on the
  285. // protection field of the invalid PTE.
  286. //
  287. #define MM_PTE_NOACCESS 0x0 // not expressable on i386
  288. #define MM_PTE_READONLY 0x0
  289. #define MM_PTE_READWRITE MM_PTE_WRITE_MASK
  290. #define MM_PTE_WRITECOPY 0x200 // read-only copy on write bit set.
  291. #define MM_PTE_EXECUTE 0x0 // read-only on i386
  292. #define MM_PTE_EXECUTE_READ 0x0
  293. #define MM_PTE_EXECUTE_READWRITE MM_PTE_WRITE_MASK
  294. #define MM_PTE_EXECUTE_WRITECOPY 0x200 // read-only copy on write bit set.
  295. #define MM_PTE_NOCACHE 0x010
  296. #define MM_PTE_GUARD 0x0 // not expressable on i386
  297. #define MM_PTE_CACHE 0x0
  298. #define MM_PROTECT_FIELD_SHIFT 5
  299. //
  300. // Bits available for the software working set index within the hardware PTE.
  301. //
  302. #define MI_MAXIMUM_PTE_WORKING_SET_INDEX 0
  303. //
  304. // Zero PTE
  305. //
  306. #define MM_ZERO_PTE 0
  307. //
  308. // Zero Kernel PTE
  309. //
  310. #define MM_ZERO_KERNEL_PTE 0
  311. //
  312. // A demand zero PTE with a protection or PAGE_READWRITE.
  313. //
  314. #define MM_DEMAND_ZERO_WRITE_PTE (MM_READWRITE << MM_PROTECT_FIELD_SHIFT)
  315. //
  316. // A demand zero PTE with a protection or PAGE_READWRITE for system space.
  317. //
  318. #define MM_KERNEL_DEMAND_ZERO_PTE (MM_READWRITE << MM_PROTECT_FIELD_SHIFT)
  319. //
  320. // A no access PTE for system space.
  321. //
  322. #define MM_KERNEL_NOACCESS_PTE (MM_NOACCESS << MM_PROTECT_FIELD_SHIFT)
  323. //
  324. // Kernel stack alignment requirements.
  325. //
  326. #define MM_STACK_ALIGNMENT 0x0
  327. #define MM_STACK_OFFSET 0x0
  328. //
  329. // System process definitions
  330. //
  331. #define PDE_PER_PAGE ((ULONG)1024)
  332. #define PTE_PER_PAGE ((ULONG)1024)
  333. #define PD_PER_SYSTEM ((ULONG)1)
  334. //
  335. // Number of page table pages for user addresses.
  336. //
  337. #define MM_USER_PAGE_TABLE_PAGES (768)
  338. //++
  339. //VOID
  340. //MI_MAKE_VALID_PTE (
  341. // OUT OUTPTE,
  342. // IN FRAME,
  343. // IN PMASK,
  344. // IN PPTE
  345. // );
  346. //
  347. // Routine Description:
  348. //
  349. // This macro makes a valid PTE from a page frame number, protection mask,
  350. // and owner.
  351. //
  352. // Arguments
  353. //
  354. // OUTPTE - Supplies the PTE in which to build the transition PTE.
  355. //
  356. // FRAME - Supplies the page frame number for the PTE.
  357. //
  358. // PMASK - Supplies the protection to set in the transition PTE.
  359. //
  360. // PPTE - Supplies a pointer to the PTE which is being made valid.
  361. // For prototype PTEs NULL should be specified.
  362. //
  363. // Return Value:
  364. //
  365. // None.
  366. //
  367. //--
  368. #define MI_MAKE_VALID_PTE(OUTPTE,FRAME,PMASK,PPTE) \
  369. (OUTPTE).u.Long = ((FRAME << 12) | \
  370. (MmProtectToPteMask[PMASK]) | \
  371. MiDetermineUserGlobalPteMask ((PMMPTE)PPTE));
  372. //++
  373. //VOID
  374. //MI_MAKE_VALID_PTE_TRANSITION (
  375. // IN OUT OUTPTE
  376. // IN PROTECT
  377. // );
  378. //
  379. // Routine Description:
  380. //
  381. // This macro takes a valid pte and turns it into a transition PTE.
  382. //
  383. // Arguments
  384. //
  385. // OUTPTE - Supplies the current valid PTE. This PTE is then
  386. // modified to become a transition PTE.
  387. //
  388. // PROTECT - Supplies the protection to set in the transition PTE.
  389. //
  390. // Return Value:
  391. //
  392. // None.
  393. //
  394. //--
  395. #define MI_MAKE_VALID_PTE_TRANSITION(OUTPTE,PROTECT) \
  396. (OUTPTE).u.Soft.Transition = 1; \
  397. (OUTPTE).u.Soft.Valid = 0; \
  398. (OUTPTE).u.Soft.Prototype = 0; \
  399. (OUTPTE).u.Soft.Protection = PROTECT;
  400. //++
  401. //VOID
  402. //MI_MAKE_TRANSITION_PTE (
  403. // OUT OUTPTE,
  404. // IN PAGE,
  405. // IN PROTECT,
  406. // IN PPTE
  407. // );
  408. //
  409. // Routine Description:
  410. //
  411. // This macro takes a valid pte and turns it into a transition PTE.
  412. //
  413. // Arguments
  414. //
  415. // OUTPTE - Supplies the PTE in which to build the transition PTE.
  416. //
  417. // PAGE - Supplies the page frame number for the PTE.
  418. //
  419. // PROTECT - Supplies the protection to set in the transition PTE.
  420. //
  421. // PPTE - Supplies a pointer to the PTE, this is used to determine
  422. // the owner of the PTE.
  423. //
  424. // Return Value:
  425. //
  426. // None.
  427. //
  428. //--
  429. #define MI_MAKE_TRANSITION_PTE(OUTPTE,PAGE,PROTECT,PPTE) \
  430. (OUTPTE).u.Long = 0; \
  431. (OUTPTE).u.Trans.PageFrameNumber = PAGE; \
  432. (OUTPTE).u.Trans.Transition = 1; \
  433. (OUTPTE).u.Trans.Protection = PROTECT; \
  434. (OUTPTE).u.Trans.Owner = MI_DETERMINE_OWNER(PPTE);
  435. //++
  436. //VOID
  437. //MI_MAKE_TRANSITION_PTE_VALID (
  438. // OUT OUTPTE,
  439. // IN PPTE
  440. // );
  441. //
  442. // Routine Description:
  443. //
  444. // This macro takes a transition pte and makes it a valid PTE.
  445. //
  446. // Arguments
  447. //
  448. // OUTPTE - Supplies the PTE in which to build the valid PTE.
  449. //
  450. // PPTE - Supplies a pointer to the transition PTE.
  451. //
  452. // Return Value:
  453. //
  454. // None.
  455. //
  456. //--
  457. #define MI_MAKE_TRANSITION_PTE_VALID(OUTPTE,PPTE) \
  458. ASSERT (((PPTE)->u.Hard.Valid == 0) && \
  459. ((PPTE)->u.Trans.Prototype == 0) && \
  460. ((PPTE)->u.Trans.Transition == 1)); \
  461. (OUTPTE).u.Long = (((PPTE)->u.Long & 0xFFFFF000) | \
  462. (MmProtectToPteMask[(PPTE)->u.Trans.Protection]) | \
  463. MiDetermineUserGlobalPteMask ((PMMPTE)PPTE));
  464. #define MI_FAULT_STATUS_INDICATES_EXECUTION(_FaultStatus) 0
  465. #define MI_FAULT_STATUS_INDICATES_WRITE(_FaultStatus) (_FaultStatus & 0x1)
  466. #define MI_CLEAR_FAULT_STATUS(_FaultStatus) (_FaultStatus = 0)
  467. #define MI_IS_PTE_EXECUTABLE(_TempPte) (1)
  468. //++
  469. //++
  470. //VOID
  471. //MI_SET_PTE_IN_WORKING_SET (
  472. // OUT PMMPTE PTE,
  473. // IN ULONG WSINDEX
  474. // );
  475. //
  476. // Routine Description:
  477. //
  478. // This macro inserts the specified working set index into the argument PTE.
  479. // Since the i386 PTE has no free bits nothing needs to be done on this
  480. // architecture.
  481. //
  482. // Arguments
  483. //
  484. // OUTPTE - Supplies the PTE in which to insert the working set index.
  485. //
  486. // WSINDEX - Supplies the working set index for the PTE.
  487. //
  488. // Return Value:
  489. //
  490. // None.
  491. //
  492. //--
  493. #define MI_SET_PTE_IN_WORKING_SET(PTE, WSINDEX)
  494. //++
  495. //ULONG WsIndex
  496. //MI_GET_WORKING_SET_FROM_PTE(
  497. // IN PMMPTE PTE
  498. // );
  499. //
  500. // Routine Description:
  501. //
  502. // This macro returns the working set index from the argument PTE.
  503. // Since the i386 PTE has no free bits nothing needs to be done on this
  504. // architecture.
  505. //
  506. // Arguments
  507. //
  508. // PTE - Supplies the PTE to extract the working set index from.
  509. //
  510. // Return Value:
  511. //
  512. // This macro returns the working set index for the argument PTE.
  513. //
  514. //--
  515. #define MI_GET_WORKING_SET_FROM_PTE(PTE) 0
  516. //++
  517. //VOID
  518. //MI_SET_PTE_WRITE_COMBINE (
  519. // IN MMPTE PTE
  520. // );
  521. //
  522. // Routine Description:
  523. //
  524. // This macro takes a valid PTE and enables WriteCombining as the
  525. // caching state. Note that the PTE bits may only be set this way
  526. // if the Page Attribute Table is present and the PAT has been
  527. // initialized to provide Write Combining.
  528. //
  529. // If either of the above conditions is not satisfied, then
  530. // the macro enables WEAK UC (PCD = 1, PWT = 0) in the PTE.
  531. //
  532. // Arguments
  533. //
  534. // PTE - Supplies a valid PTE.
  535. //
  536. // Return Value:
  537. //
  538. // None.
  539. //
  540. //--
  541. //
  542. #define MI_SET_PTE_WRITE_COMBINE(PTE) \
  543. { \
  544. if (MiWriteCombiningPtes == TRUE) { \
  545. ((PTE).u.Hard.CacheDisable = 0); \
  546. ((PTE).u.Hard.WriteThrough = 1); \
  547. } else { \
  548. ((PTE).u.Hard.CacheDisable = 1); \
  549. ((PTE).u.Hard.WriteThrough = 0); \
  550. } \
  551. }
  552. //++
  553. //VOID
  554. //MI_PREPARE_FOR_NONCACHED (
  555. // IN MI_PFN_CACHE_ATTRIBUTE CacheAttribute
  556. // );
  557. //
  558. // Routine Description:
  559. //
  560. // This macro prepares the system prior to noncached PTEs being created.
  561. //
  562. // Note the entire TB must be flushed on all processors because there may
  563. // be stale system PTE (or hyperspace or zeropage) mappings in the TB which
  564. // may refer to the same physical page but with a different cache attribute.
  565. //
  566. // Arguments
  567. //
  568. // CacheAttribute - Supplies the cache attribute the PTEs will be filled
  569. // with.
  570. //
  571. // Return Value:
  572. //
  573. // None.
  574. //
  575. //--
  576. #define MI_PREPARE_FOR_NONCACHED(_CacheAttribute) \
  577. if (_CacheAttribute != MiCached) { \
  578. KeFlushEntireTb (FALSE, TRUE); \
  579. KeInvalidateAllCaches (TRUE); \
  580. }
  581. //++
  582. //VOID
  583. //MI_SWEEP_CACHE (
  584. // IN MI_PFN_CACHE_ATTRIBUTE CacheAttribute,
  585. // IN PVOID StartVa,
  586. // IN ULONG NumberOfBytes
  587. // );
  588. //
  589. // Routine Description:
  590. //
  591. // This macro prepares the system prior to noncached PTEs being created.
  592. // This does nothing on x86.
  593. //
  594. // Arguments
  595. //
  596. // CacheAttribute - Supplies the cache attribute the new PTEs were filled
  597. // with.
  598. //
  599. // StartVa - Supplies the starting address that's been mapped.
  600. //
  601. // NumberOfBytes - Supplies the number of bytes that have been mapped.
  602. //
  603. // Return Value:
  604. //
  605. // None.
  606. //
  607. //--
  608. #define MI_SWEEP_CACHE(_CacheAttribute,_StartVa,_NumberOfBytes)
  609. LOGICAL
  610. MiMustFrameBeCached (
  611. IN PFN_NUMBER PageFrameIndex
  612. );
  613. typedef struct _MI_LARGE_PAGE_RANGES {
  614. PFN_NUMBER StartFrame;
  615. PFN_NUMBER LastFrame;
  616. } MI_LARGE_PAGE_RANGES, *PMI_LARGE_PAGE_RANGES;
  617. #define MI_MAX_LARGE_PAGE_RANGES 4
  618. extern MI_LARGE_PAGE_RANGES MiLargePageRanges[];
  619. #define MI_PAGE_FRAME_INDEX_MUST_BE_CACHED(PageFrameIndex) \
  620. MiMustFrameBeCached(PageFrameIndex)
  621. //++
  622. //VOID
  623. //MI_SET_PTE_DIRTY (
  624. // IN MMPTE PTE
  625. // );
  626. //
  627. // Routine Description:
  628. //
  629. // This macro sets the dirty bit(s) in the specified PTE.
  630. //
  631. // Arguments
  632. //
  633. // PTE - Supplies the PTE to set dirty.
  634. //
  635. // Return Value:
  636. //
  637. // None.
  638. //
  639. //--
  640. #define MI_SET_PTE_DIRTY(PTE) (PTE).u.Long |= HARDWARE_PTE_DIRTY_MASK
  641. //++
  642. //VOID
  643. //MI_SET_PTE_CLEAN (
  644. // IN MMPTE PTE
  645. // );
  646. //
  647. // Routine Description:
  648. //
  649. // This macro clears the dirty bit(s) in the specified PTE.
  650. //
  651. // Arguments
  652. //
  653. // PTE - Supplies the PTE to set clear.
  654. //
  655. // Return Value:
  656. //
  657. // None.
  658. //
  659. //--
  660. #define MI_SET_PTE_CLEAN(PTE) (PTE).u.Long &= ~HARDWARE_PTE_DIRTY_MASK
  661. //++
  662. //VOID
  663. //MI_IS_PTE_DIRTY (
  664. // IN MMPTE PTE
  665. // );
  666. //
  667. // Routine Description:
  668. //
  669. // This macro checks the dirty bit(s) in the specified PTE.
  670. //
  671. // Arguments
  672. //
  673. // PTE - Supplies the PTE to check.
  674. //
  675. // Return Value:
  676. //
  677. // TRUE if the page is dirty (modified), FALSE otherwise.
  678. //
  679. //--
  680. #define MI_IS_PTE_DIRTY(PTE) ((PTE).u.Hard.Dirty != 0)
  681. //++
  682. //VOID
  683. //MI_SET_GLOBAL_BIT_IF_SYSTEM (
  684. // OUT OUTPTE,
  685. // IN PPTE
  686. // );
  687. //
  688. // Routine Description:
  689. //
  690. // This macro sets the global bit if the pointer PTE is within
  691. // system space.
  692. //
  693. // Arguments
  694. //
  695. // OUTPTE - Supplies the PTE in which to build the valid PTE.
  696. //
  697. // PPTE - Supplies a pointer to the PTE becoming valid.
  698. //
  699. // Return Value:
  700. //
  701. // None.
  702. //
  703. //--
  704. #define MI_SET_GLOBAL_BIT_IF_SYSTEM(OUTPTE,PPTE) \
  705. if ((((PMMPTE)PPTE) > MiHighestUserPte) && \
  706. ((((PMMPTE)PPTE) <= MiGetPteAddress (PTE_BASE)) || \
  707. (((PMMPTE)PPTE) >= MiGetPteAddress (MM_SYSTEM_CACHE_WORKING_SET)))) { \
  708. (OUTPTE).u.Long |= MmPteGlobal.u.Long; \
  709. } \
  710. else { \
  711. (OUTPTE).u.Long &= ~MmPteGlobal.u.Long; \
  712. }
  713. //++
  714. //VOID
  715. //MI_SET_GLOBAL_STATE (
  716. // IN MMPTE PTE,
  717. // IN ULONG STATE
  718. // );
  719. //
  720. // Routine Description:
  721. //
  722. // This macro sets the global bit in the PTE. if the pointer PTE is within
  723. //
  724. // Arguments
  725. //
  726. // PTE - Supplies the PTE to set global state into.
  727. //
  728. // STATE - Supplies 1 if global, 0 if not.
  729. //
  730. // Return Value:
  731. //
  732. // None.
  733. //
  734. //--
  735. #define MI_SET_GLOBAL_STATE(PTE,STATE) \
  736. if (STATE) { \
  737. (PTE).u.Long |= MmPteGlobal.u.Long; \
  738. } \
  739. else { \
  740. (PTE).u.Long &= ~MmPteGlobal.u.Long; \
  741. }
  742. //++
  743. //VOID
  744. //MI_ENABLE_CACHING (
  745. // IN MMPTE PTE
  746. // );
  747. //
  748. // Routine Description:
  749. //
  750. // This macro takes a valid PTE and sets the caching state to be
  751. // enabled. This is performed by clearing the PCD and PWT bits in the PTE.
  752. //
  753. // Semantics of the overlap between PCD, PWT, and the
  754. // USWC memory type in the MTRR are:
  755. //
  756. // PCD PWT Mtrr Mem Type Effective Memory Type
  757. // 1 0 USWC USWC
  758. // 1 1 USWC UC
  759. //
  760. // Arguments
  761. //
  762. // PTE - Supplies a valid PTE.
  763. //
  764. // Return Value:
  765. //
  766. // None.
  767. //
  768. //--
  769. #define MI_ENABLE_CACHING(PTE) \
  770. { \
  771. ((PTE).u.Hard.CacheDisable = 0); \
  772. ((PTE).u.Hard.WriteThrough = 0); \
  773. }
  774. //++
  775. //VOID
  776. //MI_DISABLE_CACHING (
  777. // IN MMPTE PTE
  778. // );
  779. //
  780. // Routine Description:
  781. //
  782. // This macro takes a valid PTE and sets the caching state to be
  783. // disabled. This is performed by setting the PCD and PWT bits in the PTE.
  784. //
  785. // Semantics of the overlap between PCD, PWT, and the
  786. // USWC memory type in the MTRR are:
  787. //
  788. // PCD PWT Mtrr Mem Type Effective Memory Type
  789. // 1 0 USWC USWC
  790. // 1 1 USWC UC
  791. //
  792. // Since an effective memory type of UC is desired here,
  793. // the WT bit is set.
  794. //
  795. // Arguments
  796. //
  797. // PTE - Supplies a pointer to the valid PTE.
  798. //
  799. // Return Value:
  800. //
  801. // None.
  802. //
  803. //--
  804. #define MI_DISABLE_CACHING(PTE) \
  805. { \
  806. ((PTE).u.Hard.CacheDisable = 1); \
  807. ((PTE).u.Hard.WriteThrough = 1); \
  808. }
  809. //++
  810. //BOOLEAN
  811. //MI_IS_CACHING_DISABLED (
  812. // IN PMMPTE PPTE
  813. // );
  814. //
  815. // Routine Description:
  816. //
  817. // This macro takes a valid PTE and returns TRUE if caching is
  818. // disabled.
  819. //
  820. // Arguments
  821. //
  822. // PPTE - Supplies a pointer to the valid PTE.
  823. //
  824. // Return Value:
  825. //
  826. // TRUE if caching is disabled, FALSE if it is enabled.
  827. //
  828. //--
  829. #define MI_IS_CACHING_DISABLED(PPTE) \
  830. ((PPTE)->u.Hard.CacheDisable == 1)
  831. //++
  832. //VOID
  833. //MI_SET_PFN_DELETED (
  834. // IN PMMPFN PPFN
  835. // );
  836. //
  837. // Routine Description:
  838. //
  839. // This macro takes a pointer to a PFN element and indicates that
  840. // the PFN is no longer in use.
  841. //
  842. // Arguments
  843. //
  844. // PPTE - Supplies a pointer to the PFN element.
  845. //
  846. // Return Value:
  847. //
  848. // none.
  849. //
  850. //--
  851. #define MI_SET_PFN_DELETED(PPFN) \
  852. PPFN->PteAddress = (PMMPTE)(((ULONG_PTR)(PPFN->PteAddress)) | 0x1);
  853. //++
  854. //VOID
  855. //MI_MARK_PFN_UNDELETED (
  856. // IN PMMPFN PPFN
  857. // );
  858. //
  859. // Routine Description:
  860. //
  861. // This macro takes a pointer to a deleted PFN element and mark that
  862. // the PFN is not deleted.
  863. //
  864. // Arguments
  865. //
  866. // PPTE - Supplies a pointer to the PFN element.
  867. //
  868. // Return Value:
  869. //
  870. // none.
  871. //
  872. //--
  873. #define MI_MARK_PFN_UNDELETED(PPFN) \
  874. PPFN->PteAddress = (PMMPTE)((ULONG_PTR)PPFN->PteAddress & ~0x1);
  875. //++
  876. //BOOLEAN
  877. //MI_IS_PFN_DELETED (
  878. // IN PMMPFN PPFN
  879. // );
  880. //
  881. // Routine Description:
  882. //
  883. // This macro takes a pointer to a PFN element and determines if
  884. // the PFN is no longer in use.
  885. //
  886. // Arguments
  887. //
  888. // PPTE - Supplies a pointer to the PFN element.
  889. //
  890. // Return Value:
  891. //
  892. // TRUE if PFN is no longer used, FALSE if it is still being used.
  893. //
  894. //--
  895. #define MI_IS_PFN_DELETED(PPFN) \
  896. ((ULONG_PTR)(PPFN)->PteAddress & 0x1)
  897. //++
  898. //VOID
  899. //MI_CHECK_PAGE_ALIGNMENT (
  900. // IN ULONG PAGE,
  901. // IN PMMPTE PPTE
  902. // );
  903. //
  904. // Routine Description:
  905. //
  906. // This macro takes a PFN element number (Page) and checks to see
  907. // if the virtual alignment for the previous address of the page
  908. // is compatible with the new address of the page. If they are
  909. // not compatible, the D cache is flushed.
  910. //
  911. // Arguments
  912. //
  913. // PAGE - Supplies the PFN element.
  914. // PPTE - Supplies a pointer to the new PTE which will contain the page.
  915. //
  916. // Return Value:
  917. //
  918. // none.
  919. //
  920. //--
  921. // does nothing on i386.
  922. #define MI_CHECK_PAGE_ALIGNMENT(PAGE,PPTE)
  923. //++
  924. //VOID
  925. //MI_INITIALIZE_HYPERSPACE_MAP (
  926. // VOID
  927. // );
  928. //
  929. // Routine Description:
  930. //
  931. // This macro initializes the PTEs reserved for double mapping within
  932. // hyperspace.
  933. //
  934. // Arguments
  935. //
  936. // None.
  937. //
  938. // Return Value:
  939. //
  940. // None.
  941. //
  942. //--
  943. // does nothing on i386.
  944. #define MI_INITIALIZE_HYPERSPACE_MAP(INDEX)
  945. //++
  946. //ULONG
  947. //MI_GET_PAGE_COLOR_FROM_PTE (
  948. // IN PMMPTE PTEADDRESS
  949. // );
  950. //
  951. // Routine Description:
  952. //
  953. // This macro determines the page's color based on the PTE address
  954. // that maps the page.
  955. //
  956. // Arguments
  957. //
  958. // PTEADDRESS - Supplies the PTE address the page is (or was) mapped at.
  959. //
  960. // Return Value:
  961. //
  962. // The page's color.
  963. //
  964. //--
  965. #define MI_GET_PAGE_COLOR_FROM_PTE(PTEADDRESS) \
  966. ((ULONG)((MI_SYSTEM_PAGE_COLOR++) & MmSecondaryColorMask))
  967. //++
  968. //ULONG
  969. //MI_GET_PAGE_COLOR_FROM_VA (
  970. // IN PVOID ADDRESS
  971. // );
  972. //
  973. // Routine Description:
  974. //
  975. // This macro determines the page's color based on the PTE address
  976. // that maps the page.
  977. //
  978. // Arguments
  979. //
  980. // ADDRESS - Supplies the address the page is (or was) mapped at.
  981. //
  982. // Return Value:
  983. //
  984. // The page's color.
  985. //
  986. //--
  987. #define MI_GET_PAGE_COLOR_FROM_VA(ADDRESS) \
  988. ((ULONG)((MI_SYSTEM_PAGE_COLOR++) & MmSecondaryColorMask))
  989. //++
  990. //ULONG
  991. //MI_GET_PAGE_COLOR_FROM_SESSION (
  992. // IN PMM_SESSION_SPACE SessionSpace
  993. // );
  994. //
  995. // Routine Description:
  996. //
  997. // This macro determines the page's color based on the PTE address
  998. // that maps the page.
  999. //
  1000. // Arguments
  1001. //
  1002. // SessionSpace - Supplies the session space the page will be mapped into.
  1003. //
  1004. // Return Value:
  1005. //
  1006. // The page's color.
  1007. //
  1008. //--
  1009. #define MI_GET_PAGE_COLOR_FROM_SESSION(_SessionSpace) \
  1010. ((ULONG)((_SessionSpace->Color++) & MmSecondaryColorMask))
  1011. //++
  1012. //ULONG
  1013. //MI_PAGE_COLOR_PTE_PROCESS (
  1014. // IN PMMPTE PTE,
  1015. // IN PUSHORT COLOR
  1016. // );
  1017. //
  1018. // Routine Description:
  1019. //
  1020. // Select page color for this process.
  1021. //
  1022. // Arguments
  1023. //
  1024. // PTE Not used.
  1025. // COLOR Value from which color is determined. This
  1026. // variable is incremented.
  1027. //
  1028. // Return Value:
  1029. //
  1030. // Page color.
  1031. //
  1032. //--
  1033. #define MI_PAGE_COLOR_PTE_PROCESS(PTE,COLOR) \
  1034. ((ULONG)((*(COLOR))++) & MmSecondaryColorMask)
  1035. //++
  1036. //ULONG
  1037. //MI_PAGE_COLOR_VA_PROCESS (
  1038. // IN PVOID ADDRESS,
  1039. // IN PEPROCESS COLOR
  1040. // );
  1041. //
  1042. // Routine Description:
  1043. //
  1044. // This macro determines the page's color based on the PTE address
  1045. // that maps the page.
  1046. //
  1047. // Arguments
  1048. //
  1049. // ADDRESS - Supplies the address the page is (or was) mapped at.
  1050. //
  1051. // Return Value:
  1052. //
  1053. // The page's color.
  1054. //
  1055. //--
  1056. #define MI_PAGE_COLOR_VA_PROCESS(ADDRESS,COLOR) \
  1057. ((ULONG)((*(COLOR))++) & MmSecondaryColorMask)
  1058. //++
  1059. //ULONG
  1060. //MI_GET_NEXT_COLOR (
  1061. // IN ULONG COLOR
  1062. // );
  1063. //
  1064. // Routine Description:
  1065. //
  1066. // This macro returns the next color in the sequence.
  1067. //
  1068. // Arguments
  1069. //
  1070. // COLOR - Supplies the color to return the next of.
  1071. //
  1072. // Return Value:
  1073. //
  1074. // Next color in sequence.
  1075. //
  1076. //--
  1077. #define MI_GET_NEXT_COLOR(COLOR) ((COLOR + 1) & MM_COLOR_MASK)
  1078. //++
  1079. //ULONG
  1080. //MI_GET_PREVIOUS_COLOR (
  1081. // IN ULONG COLOR
  1082. // );
  1083. //
  1084. // Routine Description:
  1085. //
  1086. // This macro returns the previous color in the sequence.
  1087. //
  1088. // Arguments
  1089. //
  1090. // COLOR - Supplies the color to return the previous of.
  1091. //
  1092. // Return Value:
  1093. //
  1094. // Previous color in sequence.
  1095. //
  1096. //--
  1097. #define MI_GET_PREVIOUS_COLOR(COLOR) (0)
  1098. #define MI_GET_SECONDARY_COLOR(PAGE,PFN) (PAGE & MmSecondaryColorMask)
  1099. #define MI_GET_COLOR_FROM_SECONDARY(SECONDARY_COLOR) (0)
  1100. //++
  1101. //VOID
  1102. //MI_GET_MODIFIED_PAGE_BY_COLOR (
  1103. // OUT ULONG PAGE,
  1104. // IN ULONG COLOR
  1105. // );
  1106. //
  1107. // Routine Description:
  1108. //
  1109. // This macro returns the first page destined for a paging
  1110. // file with the desired color. It does NOT remove the page
  1111. // from its list.
  1112. //
  1113. // Arguments
  1114. //
  1115. // PAGE - Returns the page located, the value MM_EMPTY_LIST is
  1116. // returned if there is no page of the specified color.
  1117. //
  1118. // COLOR - Supplies the color of page to locate.
  1119. //
  1120. // Return Value:
  1121. //
  1122. // none.
  1123. //
  1124. //--
  1125. #define MI_GET_MODIFIED_PAGE_BY_COLOR(PAGE,COLOR) \
  1126. PAGE = MmModifiedPageListByColor[COLOR].Flink
  1127. //++
  1128. //VOID
  1129. //MI_GET_MODIFIED_PAGE_ANY_COLOR (
  1130. // OUT ULONG PAGE,
  1131. // IN OUT ULONG COLOR
  1132. // );
  1133. //
  1134. // Routine Description:
  1135. //
  1136. // This macro returns the first page destined for a paging
  1137. // file with the desired color. If not page of the desired
  1138. // color exists, all colored lists are searched for a page.
  1139. // It does NOT remove the page from its list.
  1140. //
  1141. // Arguments
  1142. //
  1143. // PAGE - Returns the page located, the value MM_EMPTY_LIST is
  1144. // returned if there is no page of the specified color.
  1145. //
  1146. // COLOR - Supplies the color of page to locate and returns the
  1147. // color of the page located.
  1148. //
  1149. // Return Value:
  1150. //
  1151. // none.
  1152. //
  1153. //--
  1154. #define MI_GET_MODIFIED_PAGE_ANY_COLOR(PAGE,COLOR) \
  1155. { \
  1156. if (MmTotalPagesForPagingFile == 0) { \
  1157. PAGE = MM_EMPTY_LIST; \
  1158. } else { \
  1159. PAGE = MmModifiedPageListByColor[COLOR].Flink; \
  1160. } \
  1161. }
  1162. //++
  1163. //VOID
  1164. //MI_MAKE_VALID_PTE_WRITE_COPY (
  1165. // IN OUT PMMPTE PTE
  1166. // );
  1167. //
  1168. // Routine Description:
  1169. //
  1170. // This macro checks to see if the PTE indicates that the
  1171. // page is writable and if so it clears the write bit and
  1172. // sets the copy-on-write bit.
  1173. //
  1174. // Arguments
  1175. //
  1176. // PTE - Supplies the PTE to operate upon.
  1177. //
  1178. // Return Value:
  1179. //
  1180. // None.
  1181. //
  1182. //--
  1183. #if defined(NT_UP)
  1184. #define MI_MAKE_VALID_PTE_WRITE_COPY(PPTE) \
  1185. if ((PPTE)->u.Hard.Write == 1) { \
  1186. (PPTE)->u.Hard.CopyOnWrite = 1; \
  1187. (PPTE)->u.Hard.Write = 0; \
  1188. }
  1189. #else
  1190. #define MI_MAKE_VALID_PTE_WRITE_COPY(PPTE) \
  1191. if ((PPTE)->u.Hard.Write == 1) { \
  1192. (PPTE)->u.Hard.CopyOnWrite = 1; \
  1193. (PPTE)->u.Hard.Write = 0; \
  1194. (PPTE)->u.Hard.Writable = 0; \
  1195. }
  1196. #endif
  1197. //++
  1198. //ULONG
  1199. //MI_DETERMINE_OWNER (
  1200. // IN MMPTE PPTE
  1201. // );
  1202. //
  1203. // Routine Description:
  1204. //
  1205. // This macro examines the virtual address of the PTE and determines
  1206. // if the PTE resides in system space or user space.
  1207. //
  1208. // Arguments
  1209. //
  1210. // PTE - Supplies the PTE to operate upon.
  1211. //
  1212. // Return Value:
  1213. //
  1214. // 1 if the owner is USER_MODE, 0 if the owner is KERNEL_MODE.
  1215. //
  1216. //--
  1217. #define MI_DETERMINE_OWNER(PPTE) \
  1218. ((((PPTE) <= MiHighestUserPte) || \
  1219. ((PPTE) >= MiGetPdeAddress(NULL) && \
  1220. ((PPTE) <= MiHighestUserPde))) ? 1 : 0)
  1221. //++
  1222. //VOID
  1223. //MI_SET_ACCESSED_IN_PTE (
  1224. // IN OUT MMPTE PPTE
  1225. // );
  1226. //
  1227. // Routine Description:
  1228. //
  1229. // This macro sets the ACCESSED field in the PTE.
  1230. //
  1231. // Arguments
  1232. //
  1233. // PTE - Supplies the PTE to operate upon.
  1234. //
  1235. // Return Value:
  1236. //
  1237. // None
  1238. //
  1239. //--
  1240. #define MI_SET_ACCESSED_IN_PTE(PPTE,ACCESSED) \
  1241. ((PPTE)->u.Hard.Accessed = ACCESSED)
  1242. //++
  1243. //ULONG
  1244. //MI_GET_ACCESSED_IN_PTE (
  1245. // IN OUT MMPTE PPTE
  1246. // );
  1247. //
  1248. // Routine Description:
  1249. //
  1250. // This macro returns the state of the ACCESSED field in the PTE.
  1251. //
  1252. // Arguments
  1253. //
  1254. // PTE - Supplies the PTE to operate upon.
  1255. //
  1256. // Return Value:
  1257. //
  1258. // The state of the ACCESSED field.
  1259. //
  1260. //--
  1261. #define MI_GET_ACCESSED_IN_PTE(PPTE) ((PPTE)->u.Hard.Accessed)
  1262. //++
  1263. //VOID
  1264. //MI_SET_OWNER_IN_PTE (
  1265. // IN PMMPTE PPTE
  1266. // IN ULONG OWNER
  1267. // );
  1268. //
  1269. // Routine Description:
  1270. //
  1271. // This macro sets the owner field in the PTE.
  1272. //
  1273. // Arguments
  1274. //
  1275. // PTE - Supplies the PTE to operate upon.
  1276. //
  1277. // Return Value:
  1278. //
  1279. // None.
  1280. //
  1281. //--
  1282. #define MI_SET_OWNER_IN_PTE(PPTE,OWNER) ((PPTE)->u.Hard.Owner = OWNER)
  1283. //++
  1284. //ULONG
  1285. //MI_GET_OWNER_IN_PTE (
  1286. // IN PMMPTE PPTE
  1287. // );
  1288. //
  1289. // Routine Description:
  1290. //
  1291. // This macro gets the owner field from the PTE.
  1292. //
  1293. // Arguments
  1294. //
  1295. // PTE - Supplies the PTE to operate upon.
  1296. //
  1297. // Return Value:
  1298. //
  1299. // The state of the OWNER field.
  1300. //
  1301. //--
  1302. #define MI_GET_OWNER_IN_PTE(PPTE) ((PPTE)->u.Hard.Owner)
  1303. //
  1304. // bit mask to clear out fields in a PTE to or in prototype pte offset.
  1305. //
  1306. #define CLEAR_FOR_PROTO_PTE_ADDRESS ((ULONG)0x701)
  1307. //
  1308. // bit mask to clear out fields in a PTE to or in paging file location.
  1309. //
  1310. #define CLEAR_FOR_PAGE_FILE 0x000003E0
  1311. //++
  1312. //VOID
  1313. //MI_SET_PAGING_FILE_INFO (
  1314. // OUT MMPTE OUTPTE,
  1315. // IN MMPTE PPTE,
  1316. // IN ULONG FILEINFO,
  1317. // IN ULONG OFFSET
  1318. // );
  1319. //
  1320. // Routine Description:
  1321. //
  1322. // This macro sets into the specified PTE the supplied information
  1323. // to indicate where the backing store for the page is located.
  1324. //
  1325. // Arguments
  1326. //
  1327. // OUTPTE - Supplies the PTE in which to store the result.
  1328. //
  1329. // PTE - Supplies the PTE to operate upon.
  1330. //
  1331. // FILEINFO - Supplies the number of the paging file.
  1332. //
  1333. // OFFSET - Supplies the offset into the paging file.
  1334. //
  1335. // Return Value:
  1336. //
  1337. // None.
  1338. //
  1339. //--
  1340. #define MI_SET_PAGING_FILE_INFO(OUTPTE,PPTE,FILEINFO,OFFSET) \
  1341. (OUTPTE).u.Long = (PPTE).u.Long; \
  1342. (OUTPTE).u.Long &= CLEAR_FOR_PAGE_FILE; \
  1343. (OUTPTE).u.Long |= ((FILEINFO << 1) | (OFFSET << 12));
  1344. //++
  1345. //PMMPTE
  1346. //MiPteToProto (
  1347. // IN OUT MMPTE PPTE,
  1348. // IN ULONG FILEINFO,
  1349. // IN ULONG OFFSET
  1350. // );
  1351. //
  1352. // Routine Description:
  1353. //
  1354. // This macro returns the address of the corresponding prototype which
  1355. // was encoded earlier into the supplied PTE.
  1356. //
  1357. // NOTE THAT A PROTOPTE CAN ONLY RESIDE IN PAGED POOL!!!!!!
  1358. //
  1359. // MAX SIZE = 2^(2+7+21) = 2^30 = 1GB.
  1360. //
  1361. // NOTE that the valid bit must be zero!
  1362. //
  1363. // Arguments
  1364. //
  1365. // lpte - Supplies the PTE to operate upon.
  1366. //
  1367. // Return Value:
  1368. //
  1369. // Pointer to the prototype PTE that backs this PTE.
  1370. //
  1371. //--
  1372. #define MiPteToProto(lpte) (PMMPTE)((PMMPTE)(((((lpte)->u.Long) >> 11) << 9) + \
  1373. (((((lpte)->u.Long)) << 24) >> 23) + \
  1374. MmProtopte_Base))
  1375. //++
  1376. //ULONG
  1377. //MiProtoAddressForPte (
  1378. // IN PMMPTE proto_va
  1379. // );
  1380. //
  1381. // Routine Description:
  1382. //
  1383. // This macro sets into the specified PTE the supplied information
  1384. // to indicate where the backing store for the page is located.
  1385. // MiProtoAddressForPte returns the bit field to OR into the PTE to
  1386. // reference a prototype PTE. And set the protoPTE bit,
  1387. // MM_PTE_PROTOTYPE_MASK.
  1388. //
  1389. // Arguments
  1390. //
  1391. // proto_va - Supplies the address of the prototype PTE.
  1392. //
  1393. // Return Value:
  1394. //
  1395. // Mask to set into the PTE.
  1396. //
  1397. //--
  1398. #define MiProtoAddressForPte(proto_va) \
  1399. ((((((ULONG)proto_va - MmProtopte_Base) >> 1) & (ULONG)0x000000FE) | \
  1400. (((((ULONG)proto_va - MmProtopte_Base) << 2) & (ULONG)0xfffff800))) | \
  1401. MM_PTE_PROTOTYPE_MASK)
  1402. //++
  1403. //ULONG
  1404. //MiProtoAddressForKernelPte (
  1405. // IN PMMPTE proto_va
  1406. // );
  1407. //
  1408. // Routine Description:
  1409. //
  1410. // This macro sets into the specified PTE the supplied information
  1411. // to indicate where the backing store for the page is located.
  1412. // MiProtoAddressForPte returns the bit field to OR into the PTE to
  1413. // reference a prototype PTE. And set the protoPTE bit,
  1414. // MM_PTE_PROTOTYPE_MASK.
  1415. //
  1416. // This macro also sets any other information (such as global bits)
  1417. // required for kernel mode PTEs.
  1418. //
  1419. // Arguments
  1420. //
  1421. // proto_va - Supplies the address of the prototype PTE.
  1422. //
  1423. // Return Value:
  1424. //
  1425. // Mask to set into the PTE.
  1426. //
  1427. //--
  1428. // not different on x86.
  1429. #define MiProtoAddressForKernelPte(proto_va) MiProtoAddressForPte(proto_va)
  1430. //++
  1431. //PSUBSECTION
  1432. //MiGetSubsectionAddress (
  1433. // IN PMMPTE lpte
  1434. // );
  1435. //
  1436. // Routine Description:
  1437. //
  1438. // This macro takes a PTE and returns the address of the subsection that
  1439. // the PTE refers to. Subsections are quadword structures allocated
  1440. // from nonpaged pool.
  1441. //
  1442. // NOTE THIS MACRO LIMITS THE SIZE OF NONPAGED POOL!
  1443. // MAXIMUM NONPAGED POOL = 2^(3+4+21) = 2^28 = 256mb.
  1444. //
  1445. //
  1446. // Arguments
  1447. //
  1448. // lpte - Supplies the PTE to operate upon.
  1449. //
  1450. // Return Value:
  1451. //
  1452. // A pointer to the subsection referred to by the supplied PTE.
  1453. //
  1454. //--
  1455. #define MiGetSubsectionAddress(lpte) \
  1456. (((lpte)->u.Long & 0x80000000) ? \
  1457. ((PSUBSECTION)((PCHAR)MmSubsectionBase + \
  1458. ((((lpte)->u.Long & 0x7ffff800) >> 4) | \
  1459. (((lpte)->u.Long<<2) & 0x78)))) \
  1460. : \
  1461. ((PSUBSECTION)((PCHAR)MmNonPagedPoolEnd - \
  1462. (((((lpte)->u.Long)>>11)<<7) | \
  1463. (((lpte)->u.Long<<2) & 0x78)))))
  1464. //++
  1465. //ULONG
  1466. //MiGetSubsectionAddressForPte (
  1467. // IN PSUBSECTION VA
  1468. // );
  1469. //
  1470. // Routine Description:
  1471. //
  1472. // This macro takes the address of a subsection and encodes it for use
  1473. // in a PTE.
  1474. //
  1475. // NOTE - THE SUBSECTION ADDRESS MUST BE QUADWORD ALIGNED!
  1476. //
  1477. // Arguments
  1478. //
  1479. // VA - Supplies a pointer to the subsection to encode.
  1480. //
  1481. // Return Value:
  1482. //
  1483. // The mask to set into the PTE to make it reference the supplied
  1484. // subsection.
  1485. //
  1486. //--
  1487. #define MiGetSubsectionAddressForPte(VA) \
  1488. (((ULONG)(VA) < (ULONG)MmSubsectionBase + 128*1024*1024) ? \
  1489. (((((ULONG)VA - (ULONG)MmSubsectionBase)>>2) & (ULONG)0x0000001E) | \
  1490. ((((((ULONG)VA - (ULONG)MmSubsectionBase)<<4) & (ULONG)0x7ffff800)))| \
  1491. 0x80000000) \
  1492. : \
  1493. (((((ULONG)MmNonPagedPoolEnd - (ULONG)VA)>>2) & (ULONG)0x0000001E) | \
  1494. ((((((ULONG)MmNonPagedPoolEnd - (ULONG)VA)<<4) & (ULONG)0x7ffff800)))))
  1495. //++
  1496. //PMMPTE
  1497. //MiGetPdeAddress (
  1498. // IN PVOID va
  1499. // );
  1500. //
  1501. // Routine Description:
  1502. //
  1503. // MiGetPdeAddress returns the address of the PDE which maps the
  1504. // given virtual address.
  1505. //
  1506. // Arguments
  1507. //
  1508. // Va - Supplies the virtual address to locate the PDE for.
  1509. //
  1510. // Return Value:
  1511. //
  1512. // The address of the PDE.
  1513. //
  1514. //--
  1515. #define MiGetPdeAddress(va) ((PMMPTE)(((((ULONG)(va)) >> 22) << 2) + PDE_BASE))
  1516. //++
  1517. //PMMPTE
  1518. //MiGetPteAddress (
  1519. // IN PVOID va
  1520. // );
  1521. //
  1522. // Routine Description:
  1523. //
  1524. // MiGetPteAddress returns the address of the PTE which maps the
  1525. // given virtual address.
  1526. //
  1527. // Arguments
  1528. //
  1529. // Va - Supplies the virtual address to locate the PTE for.
  1530. //
  1531. // Return Value:
  1532. //
  1533. // The address of the PTE.
  1534. //
  1535. //--
  1536. #define MiGetPteAddress(va) ((PMMPTE)(((((ULONG)(va)) >> 12) << 2) + PTE_BASE))
  1537. //++
  1538. //ULONG
  1539. //MiGetPpeOffset (
  1540. // IN PVOID va
  1541. // );
  1542. //
  1543. // Routine Description:
  1544. //
  1545. // MiGetPpeOffset returns the offset into a page root
  1546. // for a given virtual address.
  1547. //
  1548. // Arguments
  1549. //
  1550. // Va - Supplies the virtual address to locate the offset for.
  1551. //
  1552. // Return Value:
  1553. //
  1554. // The offset into the page root table the corresponding PPE is at.
  1555. //
  1556. //--
  1557. #define MiGetPpeOffset(va) (0)
  1558. //++
  1559. //ULONG
  1560. //MiGetPdeOffset (
  1561. // IN PVOID va
  1562. // );
  1563. //
  1564. // Routine Description:
  1565. //
  1566. // MiGetPdeOffset returns the offset into a page directory
  1567. // for a given virtual address.
  1568. //
  1569. // Arguments
  1570. //
  1571. // Va - Supplies the virtual address to locate the offset for.
  1572. //
  1573. // Return Value:
  1574. //
  1575. // The offset into the page directory table the corresponding PDE is at.
  1576. //
  1577. //--
  1578. #define MiGetPdeOffset(va) (((ULONG)(va)) >> 22)
  1579. //++
  1580. //ULONG
  1581. //MiGetPdeIndex (
  1582. // IN PVOID va
  1583. // );
  1584. //
  1585. // Routine Description:
  1586. //
  1587. // MiGetPdeIndex returns the page directory index
  1588. // for a given virtual address.
  1589. //
  1590. // Arguments
  1591. //
  1592. // Va - Supplies the virtual address to locate the offset for.
  1593. //
  1594. // Return Value:
  1595. //
  1596. // The index into the page directory - ie: the virtual page table number.
  1597. // This is different from the page directory offset because this spans
  1598. // page directories on supported platforms.
  1599. //
  1600. //--
  1601. #define MiGetPdeIndex MiGetPdeOffset
  1602. //++
  1603. //ULONG
  1604. //MiGetPteOffset (
  1605. // IN PVOID va
  1606. // );
  1607. //
  1608. // Routine Description:
  1609. //
  1610. // MiGetPteOffset returns the offset into a page table page
  1611. // for a given virtual address.
  1612. //
  1613. // Arguments
  1614. //
  1615. // Va - Supplies the virtual address to locate the offset for.
  1616. //
  1617. // Return Value:
  1618. //
  1619. // The offset into the page table page table the corresponding PTE is at.
  1620. //
  1621. //--
  1622. #define MiGetPteOffset(va) ((((ULONG)(va)) << 10) >> 22)
  1623. //++
  1624. //PVOID
  1625. //MiGetVirtualAddressMappedByPpe (
  1626. // IN PMMPTE PTE
  1627. // );
  1628. //
  1629. // Routine Description:
  1630. //
  1631. // MiGetVirtualAddressMappedByPpe returns the virtual address
  1632. // which is mapped by a given PPE address.
  1633. //
  1634. // Arguments
  1635. //
  1636. // PPE - Supplies the PPE to get the virtual address for.
  1637. //
  1638. // Return Value:
  1639. //
  1640. // Virtual address mapped by the PPE.
  1641. //
  1642. //--
  1643. #define MiGetVirtualAddressMappedByPpe(PPE) (NULL)
  1644. //++
  1645. //PVOID
  1646. //MiGetVirtualAddressMappedByPde (
  1647. // IN PMMPTE PTE
  1648. // );
  1649. //
  1650. // Routine Description:
  1651. //
  1652. // MiGetVirtualAddressMappedByPde returns the virtual address
  1653. // which is mapped by a given PDE address.
  1654. //
  1655. // Arguments
  1656. //
  1657. // PDE - Supplies the PDE to get the virtual address for.
  1658. //
  1659. // Return Value:
  1660. //
  1661. // Virtual address mapped by the PDE.
  1662. //
  1663. //--
  1664. #define MiGetVirtualAddressMappedByPde(PDE) ((PVOID)((ULONG)(PDE) << 20))
  1665. //++
  1666. //PVOID
  1667. //MiGetVirtualAddressMappedByPte (
  1668. // IN PMMPTE PTE
  1669. // );
  1670. //
  1671. // Routine Description:
  1672. //
  1673. // MiGetVirtualAddressMappedByPte returns the virtual address
  1674. // which is mapped by a given PTE address.
  1675. //
  1676. // Arguments
  1677. //
  1678. // PTE - Supplies the PTE to get the virtual address for.
  1679. //
  1680. // Return Value:
  1681. //
  1682. // Virtual address mapped by the PTE.
  1683. //
  1684. //--
  1685. #define MiGetVirtualAddressMappedByPte(PTE) ((PVOID)((ULONG)(PTE) << 10))
  1686. //++
  1687. //LOGICAL
  1688. //MiIsVirtualAddressOnPpeBoundary (
  1689. // IN PVOID VA
  1690. // );
  1691. //
  1692. // Routine Description:
  1693. //
  1694. // MiIsVirtualAddressOnPpeBoundary returns TRUE if the virtual address is
  1695. // on a page directory entry boundary.
  1696. //
  1697. // Arguments
  1698. //
  1699. // VA - Supplies the virtual address to check.
  1700. //
  1701. // Return Value:
  1702. //
  1703. // TRUE if on a boundary, FALSE if not.
  1704. //
  1705. //--
  1706. #define MiIsVirtualAddressOnPpeBoundary(VA) (FALSE)
  1707. //++
  1708. //LOGICAL
  1709. //MiIsVirtualAddressOnPdeBoundary (
  1710. // IN PVOID VA
  1711. // );
  1712. //
  1713. // Routine Description:
  1714. //
  1715. // MiIsVirtualAddressOnPdeBoundary returns TRUE if the virtual address is
  1716. // on a page directory entry boundary.
  1717. //
  1718. // Arguments
  1719. //
  1720. // VA - Supplies the virtual address to check.
  1721. //
  1722. // Return Value:
  1723. //
  1724. // TRUE if on a 4MB PDE boundary, FALSE if not.
  1725. //
  1726. //--
  1727. #define MiIsVirtualAddressOnPdeBoundary(VA) (((ULONG_PTR)(VA) & PAGE_DIRECTORY_MASK) == 0)
  1728. //++
  1729. //LOGICAL
  1730. //MiIsPteOnPdeBoundary (
  1731. // IN PVOID PTE
  1732. // );
  1733. //
  1734. // Routine Description:
  1735. //
  1736. // MiIsPteOnPdeBoundary returns TRUE if the PTE is
  1737. // on a page directory entry boundary.
  1738. //
  1739. // Arguments
  1740. //
  1741. // PTE - Supplies the PTE to check.
  1742. //
  1743. // Return Value:
  1744. //
  1745. // TRUE if on a 4MB PDE boundary, FALSE if not.
  1746. //
  1747. //--
  1748. #define MiIsPteOnPdeBoundary(PTE) (((ULONG_PTR)(PTE) & (PAGE_SIZE - 1)) == 0)
  1749. //++
  1750. //ULONG
  1751. //GET_PAGING_FILE_NUMBER (
  1752. // IN MMPTE PTE
  1753. // );
  1754. //
  1755. // Routine Description:
  1756. //
  1757. // This macro extracts the paging file number from a PTE.
  1758. //
  1759. // Arguments
  1760. //
  1761. // PTE - Supplies the PTE to operate upon.
  1762. //
  1763. // Return Value:
  1764. //
  1765. // The paging file number.
  1766. //
  1767. //--
  1768. #define GET_PAGING_FILE_NUMBER(PTE) ((((PTE).u.Long) >> 1) & 0x0000000F)
  1769. //++
  1770. //ULONG
  1771. //GET_PAGING_FILE_OFFSET (
  1772. // IN MMPTE PTE
  1773. // );
  1774. //
  1775. // Routine Description:
  1776. //
  1777. // This macro extracts the offset into the paging file from a PTE.
  1778. //
  1779. // Arguments
  1780. //
  1781. // PTE - Supplies the PTE to operate upon.
  1782. //
  1783. // Return Value:
  1784. //
  1785. // The paging file offset.
  1786. //
  1787. //--
  1788. #define GET_PAGING_FILE_OFFSET(PTE) ((((PTE).u.Long) >> 12) & 0x000FFFFF)
  1789. //++
  1790. //ULONG
  1791. //IS_PTE_NOT_DEMAND_ZERO (
  1792. // IN PMMPTE PPTE
  1793. // );
  1794. //
  1795. // Routine Description:
  1796. //
  1797. // This macro checks to see if a given PTE is NOT a demand zero PTE.
  1798. //
  1799. // Arguments
  1800. //
  1801. // PTE - Supplies the PTE to operate upon.
  1802. //
  1803. // Return Value:
  1804. //
  1805. // Returns 0 if the PTE is demand zero, non-zero otherwise.
  1806. //
  1807. //--
  1808. #define IS_PTE_NOT_DEMAND_ZERO(PTE) ((PTE).u.Long & (ULONG)0xFFFFFC01)
  1809. //++
  1810. //VOID
  1811. //MI_MAKING_VALID_PTE_INVALID(
  1812. // IN PMMPTE PPTE
  1813. // );
  1814. //
  1815. // Routine Description:
  1816. //
  1817. // Prepare to make a single valid PTE invalid.
  1818. // No action is required on x86.
  1819. //
  1820. // Arguments
  1821. //
  1822. // SYSTEM_WIDE - Supplies TRUE if this will happen on all processors.
  1823. //
  1824. // Return Value:
  1825. //
  1826. // None.
  1827. //
  1828. //--
  1829. #define MI_MAKING_VALID_PTE_INVALID(SYSTEM_WIDE)
  1830. //++
  1831. //VOID
  1832. //MI_MAKING_VALID_MULTIPLE_PTES_INVALID(
  1833. // IN PMMPTE PPTE
  1834. // );
  1835. //
  1836. // Routine Description:
  1837. //
  1838. // Prepare to make multiple valid PTEs invalid.
  1839. // No action is required on x86.
  1840. //
  1841. // Arguments
  1842. //
  1843. // SYSTEM_WIDE - Supplies TRUE if this will happen on all processors.
  1844. //
  1845. // Return Value:
  1846. //
  1847. // None.
  1848. //
  1849. //--
  1850. #define MI_MAKING_MULTIPLE_PTES_INVALID(SYSTEM_WIDE)
  1851. //++
  1852. //VOID
  1853. //MI_MAKE_PROTECT_WRITE_COPY (
  1854. // IN OUT MMPTE PPTE
  1855. // );
  1856. //
  1857. // Routine Description:
  1858. //
  1859. // This macro makes a writable PTE a writable-copy PTE.
  1860. //
  1861. // Arguments
  1862. //
  1863. // PTE - Supplies the PTE to operate upon.
  1864. //
  1865. // Return Value:
  1866. //
  1867. // NONE
  1868. //
  1869. //--
  1870. #define MI_MAKE_PROTECT_WRITE_COPY(PTE) \
  1871. if ((PTE).u.Soft.Protection & MM_PROTECTION_WRITE_MASK) { \
  1872. (PTE).u.Long |= MM_PROTECTION_COPY_MASK << MM_PROTECT_FIELD_SHIFT; \
  1873. }
  1874. //++
  1875. //VOID
  1876. //MI_SET_PAGE_DIRTY(
  1877. // IN PMMPTE PPTE,
  1878. // IN PVOID VA,
  1879. // IN PVOID PFNHELD
  1880. // );
  1881. //
  1882. // Routine Description:
  1883. //
  1884. // This macro sets the dirty bit (and release page file space).
  1885. //
  1886. // Arguments
  1887. //
  1888. // TEMP - Supplies a temporary for usage.
  1889. //
  1890. // PPTE - Supplies a pointer to the PTE that corresponds to VA.
  1891. //
  1892. // VA - Supplies a the virtual address of the page fault.
  1893. //
  1894. // PFNHELD - Supplies TRUE if the PFN lock is held.
  1895. //
  1896. // Return Value:
  1897. //
  1898. // None.
  1899. //
  1900. //--
  1901. #if defined(NT_UP)
  1902. #define MI_SET_PAGE_DIRTY(PPTE,VA,PFNHELD)
  1903. #else
  1904. #define MI_SET_PAGE_DIRTY(PPTE,VA,PFNHELD) \
  1905. if ((PPTE)->u.Hard.Dirty == 1) { \
  1906. MiSetDirtyBit ((VA),(PPTE),(PFNHELD)); \
  1907. }
  1908. #endif
  1909. //++
  1910. //VOID
  1911. //MI_NO_FAULT_FOUND(
  1912. // IN FAULTSTATUS,
  1913. // IN PMMPTE PPTE,
  1914. // IN PVOID VA,
  1915. // IN PVOID PFNHELD
  1916. // );
  1917. //
  1918. // Routine Description:
  1919. //
  1920. // This macro handles the case when a page fault is taken and no
  1921. // PTE with the valid bit clear is found.
  1922. //
  1923. // Arguments
  1924. //
  1925. // FAULTSTATUS - Supplies the fault status.
  1926. //
  1927. // PPTE - Supplies a pointer to the PTE that corresponds to VA.
  1928. //
  1929. // VA - Supplies a the virtual address of the page fault.
  1930. //
  1931. // PFNHELD - Supplies TRUE if the PFN lock is held.
  1932. //
  1933. // Return Value:
  1934. //
  1935. // None.
  1936. //
  1937. //--
  1938. #if defined(NT_UP)
  1939. #define MI_NO_FAULT_FOUND(FAULTSTATUS,PPTE,VA,PFNHELD)
  1940. #else
  1941. #define MI_NO_FAULT_FOUND(FAULTSTATUS,PPTE,VA,PFNHELD) \
  1942. if ((MI_FAULT_STATUS_INDICATES_WRITE(FAULTSTATUS)) && ((PPTE)->u.Hard.Dirty == 0)) { \
  1943. MiSetDirtyBit ((VA),(PPTE),(PFNHELD)); \
  1944. }
  1945. #endif
  1946. //++
  1947. //ULONG
  1948. //MI_CAPTURE_DIRTY_BIT_TO_PFN (
  1949. // IN PMMPTE PPTE,
  1950. // IN PMMPFN PPFN
  1951. // );
  1952. //
  1953. // Routine Description:
  1954. //
  1955. // This macro gets captures the state of the dirty bit to the PFN
  1956. // and frees any associated page file space if the PTE has been
  1957. // modified element.
  1958. //
  1959. // NOTE - THE PFN LOCK MUST BE HELD!
  1960. //
  1961. // Arguments
  1962. //
  1963. // PPTE - Supplies the PTE to operate upon.
  1964. //
  1965. // PPFN - Supplies a pointer to the PFN database element that corresponds
  1966. // to the page mapped by the PTE.
  1967. //
  1968. // Return Value:
  1969. //
  1970. // None.
  1971. //
  1972. //--
  1973. #define MI_CAPTURE_DIRTY_BIT_TO_PFN(PPTE,PPFN) \
  1974. ASSERT (KeGetCurrentIrql() > APC_LEVEL); \
  1975. if (((PPFN)->u3.e1.Modified == 0) && \
  1976. ((PPTE)->u.Hard.Dirty != 0)) { \
  1977. MI_SET_MODIFIED (PPFN, 1, 0x18); \
  1978. if (((PPFN)->OriginalPte.u.Soft.Prototype == 0) && \
  1979. ((PPFN)->u3.e1.WriteInProgress == 0)) { \
  1980. MiReleasePageFileSpace ((PPFN)->OriginalPte); \
  1981. (PPFN)->OriginalPte.u.Soft.PageFileHigh = 0; \
  1982. } \
  1983. }
  1984. //++
  1985. //BOOLEAN
  1986. //MI_IS_PHYSICAL_ADDRESS (
  1987. // IN PVOID VA
  1988. // );
  1989. //
  1990. // Routine Description:
  1991. //
  1992. // This macro determines if a given virtual address is really a
  1993. // physical address.
  1994. //
  1995. // Arguments
  1996. //
  1997. // VA - Supplies the virtual address.
  1998. //
  1999. // Return Value:
  2000. //
  2001. // FALSE if it is not a physical address, TRUE if it is.
  2002. //
  2003. //--
  2004. #define MI_IS_PHYSICAL_ADDRESS(Va) \
  2005. ((MiGetPdeAddress(Va)->u.Long & 0x81) == 0x81)
  2006. //++
  2007. //ULONG
  2008. //MI_CONVERT_PHYSICAL_TO_PFN (
  2009. // IN PVOID VA
  2010. // );
  2011. //
  2012. // Routine Description:
  2013. //
  2014. // This macro converts a physical address (see MI_IS_PHYSICAL_ADDRESS)
  2015. // to its corresponding physical frame number.
  2016. //
  2017. // Arguments
  2018. //
  2019. // VA - Supplies a pointer to the physical address.
  2020. //
  2021. // Return Value:
  2022. //
  2023. // Returns the PFN for the page.
  2024. //
  2025. //--
  2026. #define MI_CONVERT_PHYSICAL_TO_PFN(Va) \
  2027. ((PFN_NUMBER)(MiGetPdeAddress(Va)->u.Hard.PageFrameNumber) + (MiGetPteOffset((ULONG)Va)))
  2028. typedef struct _MMCOLOR_TABLES {
  2029. PFN_NUMBER Flink;
  2030. PVOID Blink;
  2031. PFN_NUMBER Count;
  2032. } MMCOLOR_TABLES, *PMMCOLOR_TABLES;
  2033. extern PMMCOLOR_TABLES MmFreePagesByColor[2];
  2034. extern ULONG MmTotalPagesForPagingFile;
  2035. //
  2036. // A VALID Page Table Entry on the x86 has the following definition.
  2037. //
  2038. #define MI_MAXIMUM_PAGEFILE_SIZE (((UINT64)1 * 1024 * 1024 - 1) * PAGE_SIZE)
  2039. #define MI_PTE_LOOKUP_NEEDED (0xfffff)
  2040. typedef struct _MMPTE_SOFTWARE {
  2041. ULONG Valid : 1;
  2042. ULONG PageFileLow : 4;
  2043. ULONG Protection : 5;
  2044. ULONG Prototype : 1;
  2045. ULONG Transition : 1;
  2046. ULONG PageFileHigh : 20;
  2047. } MMPTE_SOFTWARE;
  2048. typedef struct _MMPTE_TRANSITION {
  2049. ULONG Valid : 1;
  2050. ULONG Write : 1;
  2051. ULONG Owner : 1;
  2052. ULONG WriteThrough : 1;
  2053. ULONG CacheDisable : 1;
  2054. ULONG Protection : 5;
  2055. ULONG Prototype : 1;
  2056. ULONG Transition : 1;
  2057. ULONG PageFrameNumber : 20;
  2058. } MMPTE_TRANSITION;
  2059. typedef struct _MMPTE_PROTOTYPE {
  2060. ULONG Valid : 1;
  2061. ULONG ProtoAddressLow : 7;
  2062. ULONG ReadOnly : 1; // if set allow read only access.
  2063. ULONG WhichPool : 1;
  2064. ULONG Prototype : 1;
  2065. ULONG ProtoAddressHigh : 21;
  2066. } MMPTE_PROTOTYPE;
  2067. typedef struct _MMPTE_SUBSECTION {
  2068. ULONG Valid : 1;
  2069. ULONG SubsectionAddressLow : 4;
  2070. ULONG Protection : 5;
  2071. ULONG Prototype : 1;
  2072. ULONG SubsectionAddressHigh : 20;
  2073. ULONG WhichPool : 1;
  2074. } MMPTE_SUBSECTION;
  2075. typedef struct _MMPTE_LIST {
  2076. ULONG Valid : 1;
  2077. ULONG OneEntry : 1;
  2078. ULONG filler0 : 8;
  2079. //
  2080. // Note the Prototype bit must not be used for lists like freed nonpaged
  2081. // pool because lookaside pops can legitimately reference bogus addresses
  2082. // (since the pop is unsynchronized) and the fault handler must be able to
  2083. // distinguish lists from protos so a retry status can be returned (vs a
  2084. // fatal bugcheck).
  2085. //
  2086. ULONG Prototype : 1; // MUST BE ZERO as per above comment.
  2087. ULONG filler1 : 1;
  2088. ULONG NextEntry : 20;
  2089. } MMPTE_LIST;
  2090. //
  2091. // A Page Table Entry on the x86 has the following definition.
  2092. // Note the MP version is to avoid stalls when flushing TBs across processors.
  2093. //
  2094. typedef struct _MMPTE_HARDWARE {
  2095. ULONG Valid : 1;
  2096. #if defined(NT_UP)
  2097. ULONG Write : 1; // UP version
  2098. #else
  2099. ULONG Writable : 1; // changed for MP version
  2100. #endif
  2101. ULONG Owner : 1;
  2102. ULONG WriteThrough : 1;
  2103. ULONG CacheDisable : 1;
  2104. ULONG Accessed : 1;
  2105. ULONG Dirty : 1;
  2106. ULONG LargePage : 1;
  2107. ULONG Global : 1;
  2108. ULONG CopyOnWrite : 1; // software field
  2109. ULONG Prototype : 1; // software field
  2110. #if defined(NT_UP)
  2111. ULONG reserved : 1; // software field
  2112. #else
  2113. ULONG Write : 1; // software field - MP change
  2114. #endif
  2115. ULONG PageFrameNumber : 20;
  2116. } MMPTE_HARDWARE, *PMMPTE_HARDWARE;
  2117. #if defined(NT_UP)
  2118. #define HARDWARE_PTE_DIRTY_MASK 0x40
  2119. #else
  2120. #define HARDWARE_PTE_DIRTY_MASK 0x42
  2121. #endif
  2122. #define MI_GET_PAGE_FRAME_FROM_PTE(PTE) ((PTE)->u.Hard.PageFrameNumber)
  2123. #define MI_GET_PAGE_FRAME_FROM_TRANSITION_PTE(PTE) ((PTE)->u.Trans.PageFrameNumber)
  2124. #define MI_GET_PROTECTION_FROM_SOFT_PTE(PTE) ((PTE)->u.Soft.Protection)
  2125. #define MI_GET_PROTECTION_FROM_TRANSITION_PTE(PTE) ((PTE)->u.Trans.Protection)
  2126. typedef struct _MMPTE {
  2127. union {
  2128. ULONG Long;
  2129. MMPTE_HARDWARE Hard;
  2130. HARDWARE_PTE Flush;
  2131. MMPTE_PROTOTYPE Proto;
  2132. MMPTE_SOFTWARE Soft;
  2133. MMPTE_TRANSITION Trans;
  2134. MMPTE_SUBSECTION Subsect;
  2135. MMPTE_LIST List;
  2136. } u;
  2137. } MMPTE;
  2138. typedef MMPTE *PMMPTE;
  2139. extern MMPTE MmPteGlobal; // Set if processor supports Global Page, else zero.
  2140. extern PMMPTE MiFirstReservedZeroingPte;
  2141. #define InterlockedCompareExchangePte(_PointerPte, _NewContents, _OldContents) \
  2142. InterlockedCompareExchange ((PLONG)(_PointerPte), _NewContents, _OldContents)
  2143. //++
  2144. //VOID
  2145. //MI_WRITE_VALID_PTE (
  2146. // IN PMMPTE PointerPte,
  2147. // IN MMPTE PteContents
  2148. // );
  2149. //
  2150. // Routine Description:
  2151. //
  2152. // MI_WRITE_VALID_PTE fills in the specified PTE making it valid with the
  2153. // specified contents.
  2154. //
  2155. // Arguments
  2156. //
  2157. // PointerPte - Supplies a PTE to fill.
  2158. //
  2159. // PteContents - Supplies the contents to put in the PTE.
  2160. //
  2161. // Return Value:
  2162. //
  2163. // None.
  2164. //
  2165. //--
  2166. #define MI_WRITE_VALID_PTE(_PointerPte, _PteContents) \
  2167. (*(_PointerPte) = (_PteContents))
  2168. //++
  2169. //VOID
  2170. //MI_WRITE_INVALID_PTE (
  2171. // IN PMMPTE PointerPte,
  2172. // IN MMPTE PteContents
  2173. // );
  2174. //
  2175. // Routine Description:
  2176. //
  2177. // MI_WRITE_INVALID_PTE fills in the specified PTE making it invalid with the
  2178. // specified contents.
  2179. //
  2180. // Arguments
  2181. //
  2182. // PointerPte - Supplies a PTE to fill.
  2183. //
  2184. // PteContents - Supplies the contents to put in the PTE.
  2185. //
  2186. // Return Value:
  2187. //
  2188. // None.
  2189. //
  2190. //--
  2191. #define MI_WRITE_INVALID_PTE(_PointerPte, _PteContents) \
  2192. (*(_PointerPte) = (_PteContents))
  2193. //++
  2194. //VOID
  2195. //MI_WRITE_VALID_PTE_NEW_PROTECTION (
  2196. // IN PMMPTE PointerPte,
  2197. // IN MMPTE PteContents
  2198. // );
  2199. //
  2200. // Routine Description:
  2201. //
  2202. // MI_WRITE_VALID_PTE_NEW_PROTECTION fills in the specified PTE (which was
  2203. // already valid) changing only the protection or the dirty bit.
  2204. //
  2205. // Arguments
  2206. //
  2207. // PointerPte - Supplies a PTE to fill.
  2208. //
  2209. // PteContents - Supplies the contents to put in the PTE.
  2210. //
  2211. // Return Value:
  2212. //
  2213. // None.
  2214. //
  2215. //--
  2216. #define MI_WRITE_VALID_PTE_NEW_PROTECTION(_PointerPte, _PteContents) \
  2217. (*(_PointerPte) = (_PteContents))
  2218. //++
  2219. //VOID
  2220. //MiFillMemoryPte (
  2221. // IN PMMPTE Destination,
  2222. // IN ULONG Length,
  2223. // IN MMPTE Pattern,
  2224. // };
  2225. //
  2226. // Routine Description:
  2227. //
  2228. // This function fills memory with the specified PTE pattern.
  2229. //
  2230. // Arguments
  2231. //
  2232. // Destination - Supplies a pointer to the memory to fill.
  2233. //
  2234. // Length - Supplies the length, in bytes, of the memory to be
  2235. // filled.
  2236. //
  2237. // Pattern - Supplies the PTE fill pattern.
  2238. //
  2239. // Return Value:
  2240. //
  2241. // None.
  2242. //
  2243. //--
  2244. #define MiFillMemoryPte(Destination, Length, Pattern) \
  2245. RtlFillMemoryUlong ((Destination), (Length), (Pattern))
  2246. ULONG
  2247. FASTCALL
  2248. MiDetermineUserGlobalPteMask (
  2249. IN PMMPTE Pte
  2250. );
  2251. //++
  2252. //BOOLEAN
  2253. //MI_IS_PAGE_TABLE_ADDRESS (
  2254. // IN PVOID VA
  2255. // );
  2256. //
  2257. // Routine Description:
  2258. //
  2259. // This macro takes a virtual address and determines if
  2260. // it is a page table address.
  2261. //
  2262. // Arguments
  2263. //
  2264. // VA - Supplies a virtual address.
  2265. //
  2266. // Return Value:
  2267. //
  2268. // TRUE if the address is a page table address, FALSE if not.
  2269. //
  2270. //--
  2271. #define MI_IS_PAGE_TABLE_ADDRESS(VA) \
  2272. ((PVOID)(VA) >= (PVOID)PTE_BASE && (PVOID)(VA) <= (PVOID)PTE_TOP)
  2273. //++
  2274. //BOOLEAN
  2275. //MI_IS_KERNEL_PAGE_TABLE_ADDRESS (
  2276. // IN PVOID VA
  2277. // );
  2278. //
  2279. // Routine Description:
  2280. //
  2281. // This macro takes a virtual address and determines if
  2282. // it is a page table address for a kernel address.
  2283. //
  2284. // Arguments
  2285. //
  2286. // VA - Supplies a virtual address.
  2287. //
  2288. // Return Value:
  2289. //
  2290. // TRUE if the address is a kernel page table address, FALSE if not.
  2291. //
  2292. //--
  2293. #define MI_IS_KERNEL_PAGE_TABLE_ADDRESS(VA) \
  2294. ((PVOID)(VA) >= (PVOID)MiGetPteAddress(MmSystemRangeStart) && (PVOID)(VA) <= (PVOID)PTE_TOP)
  2295. //++
  2296. //BOOLEAN
  2297. //MI_IS_PAGE_DIRECTORY_ADDRESS (
  2298. // IN PVOID VA
  2299. // );
  2300. //
  2301. // Routine Description:
  2302. //
  2303. // This macro takes a virtual address and determines if
  2304. // it is a page directory address.
  2305. //
  2306. // Arguments
  2307. //
  2308. // VA - Supplies a virtual address.
  2309. //
  2310. // Return Value:
  2311. //
  2312. // TRUE if the address is a page directory address, FALSE if not.
  2313. //
  2314. //--
  2315. #define MI_IS_PAGE_DIRECTORY_ADDRESS(VA) \
  2316. ((PVOID)(VA) >= (PVOID)PDE_BASE && (PVOID)(VA) <= (PVOID)PDE_TOP)
  2317. //++
  2318. //BOOLEAN
  2319. //MI_IS_HYPER_SPACE_ADDRESS (
  2320. // IN PVOID VA
  2321. // );
  2322. //
  2323. // Routine Description:
  2324. //
  2325. // This macro takes a virtual address and determines if
  2326. // it is a hyper space address.
  2327. //
  2328. // Arguments
  2329. //
  2330. // VA - Supplies a virtual address.
  2331. //
  2332. // Return Value:
  2333. //
  2334. // TRUE if the address is a hyper space address, FALSE if not.
  2335. //
  2336. //--
  2337. #define MI_IS_HYPER_SPACE_ADDRESS(VA) \
  2338. ((PVOID)(VA) >= (PVOID)HYPER_SPACE && (PVOID)(VA) <= (PVOID)HYPER_SPACE_END)
  2339. //++
  2340. //BOOLEAN
  2341. //MI_IS_PROCESS_SPACE_ADDRESS (
  2342. // IN PVOID VA
  2343. // );
  2344. //
  2345. // Routine Description:
  2346. //
  2347. // This macro takes a virtual address and determines if
  2348. // it is a process-specific address. This is an address in user space
  2349. // or page table pages or hyper space.
  2350. //
  2351. // Arguments
  2352. //
  2353. // VA - Supplies a virtual address.
  2354. //
  2355. // Return Value:
  2356. //
  2357. // TRUE if the address is a process-specific address, FALSE if not.
  2358. //
  2359. //--
  2360. #define MI_IS_PROCESS_SPACE_ADDRESS(VA) \
  2361. (((PVOID)(VA) <= (PVOID)MM_HIGHEST_USER_ADDRESS) || \
  2362. ((PVOID)(VA) >= (PVOID)PTE_BASE && (PVOID)(VA) <= (PVOID)HYPER_SPACE_END))
  2363. //++
  2364. //BOOLEAN
  2365. //MI_IS_PTE_PROTOTYPE (
  2366. // IN PMMPTE PTE
  2367. // );
  2368. //
  2369. // Routine Description:
  2370. //
  2371. // This macro takes a PTE address and determines if it is a prototype PTE.
  2372. //
  2373. // Arguments
  2374. //
  2375. // PTE - Supplies the virtual address of the PTE to check.
  2376. //
  2377. // Return Value:
  2378. //
  2379. // TRUE if the PTE is in a segment (ie, a prototype PTE), FALSE if not.
  2380. //
  2381. //--
  2382. #define MI_IS_PTE_PROTOTYPE(PTE) \
  2383. ((PTE) > (PMMPTE)PTE_TOP)
  2384. //++
  2385. //BOOLEAN
  2386. //MI_IS_SYSTEM_CACHE_ADDRESS (
  2387. // IN PVOID VA
  2388. // );
  2389. //
  2390. // Routine Description:
  2391. //
  2392. // This macro takes a virtual address and determines if
  2393. // it is a system cache address.
  2394. //
  2395. // Arguments
  2396. //
  2397. // VA - Supplies a virtual address.
  2398. //
  2399. // Return Value:
  2400. //
  2401. // TRUE if the address is in the system cache, FALSE if not.
  2402. //
  2403. //--
  2404. #define MI_IS_SYSTEM_CACHE_ADDRESS(VA) \
  2405. (((PVOID)(VA) >= (PVOID)MmSystemCacheStart && \
  2406. (PVOID)(VA) <= (PVOID)MmSystemCacheEnd) || \
  2407. ((PVOID)(VA) >= (PVOID)MiSystemCacheStartExtra && \
  2408. (PVOID)(VA) <= (PVOID)MiSystemCacheEndExtra))
  2409. //++
  2410. //VOID
  2411. //MI_BARRIER_SYNCHRONIZE (
  2412. // IN ULONG TimeStamp
  2413. // );
  2414. //
  2415. // Routine Description:
  2416. //
  2417. // MI_BARRIER_SYNCHRONIZE compares the argument timestamp against the
  2418. // current IPI barrier sequence stamp. When equal, all processors will
  2419. // issue memory barriers to ensure that newly created pages remain coherent.
  2420. //
  2421. // When a page is put in the zeroed or free page list the current
  2422. // barrier sequence stamp is read (interlocked - this is necessary
  2423. // to get the correct value - memory barriers won't do the trick)
  2424. // and stored in the pfn entry for the page. The current barrier
  2425. // sequence stamp is maintained by the IPI send logic and is
  2426. // incremented (interlocked) when the target set of an IPI send
  2427. // includes all processors, but the one doing the send. When a page
  2428. // is needed its sequence number is compared against the current
  2429. // barrier sequence number. If it is equal, then the contents of
  2430. // the page may not be coherent on all processors, and an IPI must
  2431. // be sent to all processors to ensure a memory barrier is
  2432. // executed (generic call can be used for this). Sending the IPI
  2433. // automatically updates the barrier sequence number. The compare
  2434. // is for equality as this is the only value that requires the IPI
  2435. // (i.e., the sequence number wraps, values in both directions are
  2436. // older). When a page is removed in this fashion and either found
  2437. // to be coherent or made coherent, it cannot be modified between
  2438. // that time and writing the PTE. If the page is modified between
  2439. // these times, then an IPI must be sent.
  2440. //
  2441. // Arguments
  2442. //
  2443. // TimeStamp - Supplies the timestamp at the time when the page was zeroed.
  2444. //
  2445. // Return Value:
  2446. //
  2447. // None.
  2448. //
  2449. //--
  2450. // does nothing on i386.
  2451. #define MI_BARRIER_SYNCHRONIZE(TimeStamp)
  2452. //++
  2453. //VOID
  2454. //MI_BARRIER_STAMP_ZEROED_PAGE (
  2455. // IN PULONG PointerTimeStamp
  2456. // );
  2457. //
  2458. // Routine Description:
  2459. //
  2460. // MI_BARRIER_STAMP_ZEROED_PAGE issues an interlocked read to get the
  2461. // current IPI barrier sequence stamp. This is called AFTER a page is
  2462. // zeroed.
  2463. //
  2464. // Arguments
  2465. //
  2466. // PointerTimeStamp - Supplies a timestamp pointer to fill with the
  2467. // current IPI barrier sequence stamp.
  2468. //
  2469. // Return Value:
  2470. //
  2471. // None.
  2472. //
  2473. //--
  2474. // does nothing on i386.
  2475. #define MI_BARRIER_STAMP_ZEROED_PAGE(PointerTimeStamp)
  2476. //++
  2477. //VOID
  2478. //MI_FLUSH_SINGLE_SESSION_TB (
  2479. // IN PVOID Virtual,
  2480. // IN ULONG Invalid,
  2481. // IN LOGICAL AllProcessors,
  2482. // IN PMMPTE PtePointer,
  2483. // IN MMPTE PteValue,
  2484. // IN MMPTE PreviousPte
  2485. // );
  2486. //
  2487. // Routine Description:
  2488. //
  2489. // MI_FLUSH_SINGLE_SESSION_TB flushes the requested single address
  2490. // translation from the TB.
  2491. //
  2492. // Since there are no ASNs on the x86, this routine becomes a single
  2493. // TB invalidate.
  2494. //
  2495. // Arguments
  2496. //
  2497. // Virtual - Supplies the virtual address to invalidate.
  2498. //
  2499. // Invalid - TRUE if invalidating.
  2500. //
  2501. // AllProcessors - TRUE if all processors need to be IPI'd.
  2502. //
  2503. // PtePointer - Supplies the PTE to invalidate.
  2504. //
  2505. // PteValue - Supplies the new PTE value.
  2506. //
  2507. // PreviousPte - The previous PTE value is returned here.
  2508. //
  2509. // Return Value:
  2510. //
  2511. // None.
  2512. //
  2513. //--
  2514. #define MI_FLUSH_SINGLE_SESSION_TB(Virtual, Invalid, AllProcessors, PtePointer, PteValue, PreviousPte) \
  2515. PreviousPte.u.Flush = KeFlushSingleTb (Virtual, \
  2516. TRUE, \
  2517. TRUE, \
  2518. PtePointer, \
  2519. PteValue);
  2520. //++
  2521. //VOID
  2522. //MI_FLUSH_ENTIRE_SESSION_TB (
  2523. // IN ULONG Invalid,
  2524. // IN LOGICAL AllProcessors
  2525. // );
  2526. //
  2527. // Routine Description:
  2528. //
  2529. // MI_FLUSH_ENTIRE_SESSION_TB flushes the entire TB on processors which
  2530. // support ASNs.
  2531. //
  2532. // Since there are no ASNs on the x86, this routine does nothing.
  2533. //
  2534. // Arguments
  2535. //
  2536. // Invalid - TRUE if invalidating.
  2537. //
  2538. // AllProcessors - TRUE if all processors need to be IPI'd.
  2539. //
  2540. // Return Value:
  2541. //
  2542. // None.
  2543. //
  2544. #define MI_FLUSH_ENTIRE_SESSION_TB(Invalid, AllProcessors) \
  2545. NOTHING;
  2546. //++
  2547. //LOGICAL
  2548. //MI_RESERVED_BITS_CANONICAL (
  2549. // IN PVOID VirtualAddress
  2550. // );
  2551. //
  2552. // Routine Description:
  2553. //
  2554. // This routine checks whether all of the reserved bits are correct.
  2555. //
  2556. // This does nothing on the x86.
  2557. //
  2558. // Arguments
  2559. //
  2560. // VirtualAddress - Supplies the virtual address to check.
  2561. //
  2562. // Return Value:
  2563. //
  2564. // None.
  2565. //
  2566. #define MI_RESERVED_BITS_CANONICAL(VirtualAddress) TRUE
  2567. //++
  2568. //VOID
  2569. //MI_DISPLAY_TRAP_INFORMATION (
  2570. // IN PVOID TrapInformation
  2571. // );
  2572. //
  2573. // Routine Description:
  2574. //
  2575. // Display any relevant trap information to aid debugging.
  2576. //
  2577. // Arguments
  2578. //
  2579. // TrapInformation - Supplies a pointer to a trap frame.
  2580. //
  2581. // Return Value:
  2582. //
  2583. // None.
  2584. //
  2585. #define MI_DISPLAY_TRAP_INFORMATION(TrapInformation) \
  2586. KdPrint(("MM:***EIP %p, EFL %p\n", \
  2587. ((PKTRAP_FRAME) (TrapInformation))->Eip, \
  2588. ((PKTRAP_FRAME) (TrapInformation))->EFlags)); \
  2589. KdPrint(("MM:***EAX %p, ECX %p EDX %p\n", \
  2590. ((PKTRAP_FRAME) (TrapInformation))->Eax, \
  2591. ((PKTRAP_FRAME) (TrapInformation))->Ecx, \
  2592. ((PKTRAP_FRAME) (TrapInformation))->Edx)); \
  2593. KdPrint(("MM:***EBX %p, ESI %p EDI %p\n", \
  2594. ((PKTRAP_FRAME) (TrapInformation))->Ebx, \
  2595. ((PKTRAP_FRAME) (TrapInformation))->Esi, \
  2596. ((PKTRAP_FRAME) (TrapInformation))->Edi));
  2597. #else
  2598. #include "i386\mipae.h"
  2599. #endif