Source code of Windows XP (NT5)
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  1. //***************************************************************************
  2. //
  3. // FileName:
  4. // $Workfile: mixhal.cpp $
  5. //
  6. // Author:
  7. // TOSHIBA [PCS](PSY) Seiichi Nakamura
  8. // Copyright (c) 1997 TOSHIBA CORPORATION
  9. //
  10. // Description:
  11. //
  12. //***************************************************************************
  13. // $Header: /DVD Drivers/ZiVA.WDM/mixhal.cpp 65 99/03/02 11:03a Yagi $
  14. // $Modtime: 99/03/02 10:26a $
  15. // $Nokeywords:$
  16. //***************************************************************************
  17. // Date | Author | Description
  18. // -----------+--------------+--------------------------------------------
  19. // 1998.03.27 | Hideki Yagi | Add SetDataDirection method.
  20. //
  21. //***************************************************************************
  22. //
  23. //***************************************************************************
  24. #include "includes.h"
  25. #include "timeout.h"
  26. #include "ioif.h"
  27. #include "zivachip.h"
  28. #include "adv.h"
  29. #include "mixhal.h"
  30. // by oka
  31. #include "userdata.h"
  32. #include "zivabrd.h"
  33. //---------------------------------------------------------------------------
  34. // CMixHALStream Constructor
  35. //---------------------------------------------------------------------------
  36. CMixHALStream::CMixHALStream( void ): m_pZiVA(NULL), m_pKernelObj( NULL ), m_pioif(NULL), m_pZiVABoard( NULL )
  37. {
  38. pQueuedBuff[0] = NULL;
  39. pQueuedBuff[1] = NULL;
  40. fCanSendData = FALSE;
  41. fCanDMA = FALSE;
  42. m_StreamState = StreamStop;
  43. };
  44. //---------------------------------------------------------------------------
  45. // CMixHALStream::Init
  46. //---------------------------------------------------------------------------
  47. void CMixHALStream::Init( CZiVA *pZiVA, IKernelService *pKernelObj, CIOIF *pioif , CMPEGBoardHAL *pZiVABoard)
  48. {
  49. pQueuedBuff[0] = NULL;
  50. pQueuedBuff[1] = NULL;
  51. m_StreamState = StreamStop;
  52. m_pZiVA = pZiVA;
  53. m_pKernelObj = pKernelObj;
  54. m_pioif = pioif;
  55. m_pZiVABoard = pZiVABoard;
  56. fCanSendData = FALSE;
  57. fCanDMA = FALSE;
  58. };
  59. //---------------------------------------------------------------------------
  60. // CMixHALStream Defifo
  61. //---------------------------------------------------------------------------
  62. HALRESULT CMixHALStream::DeFifo( void )
  63. {
  64. // if( m_StreamState == StreamPause )
  65. // return HAL_SUCCESS;
  66. // 1998/5/21 seichan
  67. // �����ݏ������[�`���ƒʏ��̃��[�`�����瓯���ɌĂ΂��邱�Ƃ�
  68. // �֎~���邽�߂ɁA�����݋֎~�ɐݒ�
  69. CAutoHwInt hwintlock( m_pKernelObj );
  70. if( fCanDMA == FALSE )
  71. return HAL_SUCCESS;
  72. DWORD pQueueNum = m_DmaFifo.GetMaxSize() - m_DmaFifo.GetItemNum();
  73. if( pQueueNum == 0 || m_HalFifo.GetItemNum() == 0 )
  74. return HAL_SUCCESS;
  75. IHALBuffer *pData;
  76. m_HalFifo.GetItem( &pData );
  77. return SendToDMA( pData );
  78. };
  79. //---------------------------------------
  80. // CMixHALStream::SendData
  81. //---------------------------------------
  82. HALRESULT CMixHALStream::SendData( IHALBuffer *pData )
  83. {
  84. ASSERT( m_pioif != NULL );
  85. ASSERT( pData != NULL );
  86. DWORD QueueNum;
  87. GetAvailableQueue( &QueueNum );
  88. if( QueueNum == 0 || fCanSendData == FALSE )
  89. {
  90. DBG_BREAK();
  91. return HAL_ERROR;
  92. };
  93. if( m_HalFifo.AddItem( pData ) == FALSE )
  94. {
  95. DBG_BREAK();
  96. return HAL_ERROR;
  97. };
  98. return DeFifo();
  99. };
  100. //---------------------------------------
  101. // CMixHALStream::SendToDMA
  102. //---------------------------------------
  103. HALRESULT CMixHALStream::SendToDMA( IHALBuffer *pData )
  104. {
  105. ASSERT( m_pioif != NULL );
  106. ASSERT( pData != NULL );
  107. /*
  108. // check power state
  109. POWERSTATE PowerState;
  110. ASSERT( m_pZiVABoard != NULL );
  111. m_pZiVABoard->GetPowerState( &PowerState );
  112. if( PowerState == POWERSTATE_OFF )
  113. {
  114. DBG_BREAK();
  115. return HAL_ERROR;
  116. };
  117. */
  118. DWORD i;
  119. for( i = 0 ; i < ZIVA_QUEUE_SIZE; i ++ )
  120. {
  121. if( pQueuedBuff[i] == NULL )
  122. break;
  123. };
  124. if( i == ZIVA_QUEUE_SIZE )
  125. {
  126. DBG_BREAK();
  127. return HAL_ERROR;
  128. };
  129. pQueuedBuff[i] = pData;
  130. #ifdef _WDMDDK_NONEED_CAUSE_FIXED_BY_UCODE
  131. // ZiVA 1.1��WDM�Ń��j���[�����܂��\���ł��Ȃ�����������
  132. {
  133. UCHAR *Buffer = pData->GetLinBuffPointer();
  134. ASSERT( Buffer != NULL );
  135. if( Buffer != NULL )
  136. {
  137. // SCR check
  138. if( ((Buffer[4] & 0x44) == 0x44 )
  139. && ((Buffer[6] & 0x04) == 0x04 )
  140. && ((Buffer[8] & 0x04) == 0x04 )
  141. && ((Buffer[9] & 0x01) == 0x01 ) )
  142. {
  143. DWORD SCR = 0;
  144. SCR += ((Buffer[4] & 0x03) >> 0) << 28;
  145. SCR += ((Buffer[5] & 0xff) >> 0) << 20;
  146. SCR += ((Buffer[6] & 0xf8) >> 3) << 15;
  147. SCR += ((Buffer[6] & 0x03) >> 0) << 13;
  148. SCR += ((Buffer[7] & 0xff) >> 0) << 5;
  149. SCR += ((Buffer[8] & 0xf8) >> 3) << 0;
  150. /*
  151. DWORD PTS = 0;
  152. if( (Buffer[14+7] & 0x80 ) != 0 ) // check PTS_DTS Flags
  153. {
  154. PTS = ( ( Buffer[14+9] >> 1 ) & 0x7 ) << 30; // 32-30
  155. PTS |= ( ( Buffer[14+10] >> 0 ) & 0xff ) << 22; // 29-22
  156. PTS |= ( ( Buffer[14+11] >> 1 ) & 0x7f ) << 15; // 21-15
  157. PTS |= ( ( Buffer[14+12] >> 0 ) & 0xff ) << 7; // 14-7
  158. PTS |= ( ( Buffer[14+13] >> 1 ) & 0x7f ) << 0; // 6-0
  159. if( Buffer[14+3] == 0xe0 )
  160. DBG_PRINTF((" [%04d]SCR = 0x%x PTS = 0x%x Video \r\n",BuffCount, SCR,PTS ));
  161. else
  162. DBG_PRINTF((" [%04d]SCR = 0x%x PTS = 0x%x (0x%x)\r\n",BuffCount, SCR,PTS,Buffer[14+3] ));
  163. }
  164. else
  165. {
  166. if( Buffer[14+3] == 0xe0 )
  167. DBG_PRINTF((" [%04d]SCR = 0x%x Video \r\n", BuffCount, SCR ));
  168. else
  169. DBG_PRINTF((" [%04d]SCR = 0x%x (0x%x)\r\n", BuffCount, SCR,Buffer[14+3] ));
  170. };
  171. */
  172. if( SCR < 500 *90 )
  173. {
  174. // set scr = 0 !!!!
  175. Buffer[4] = 0x44;
  176. Buffer[5] = 0x00;
  177. Buffer[6] = 0x04;
  178. Buffer[7] = 0x00;
  179. Buffer[8] = 0x04;
  180. Buffer[9] = 0x01;
  181. };
  182. }
  183. else
  184. {
  185. DBG_PRINTF((" mixhal: SCR CHECK ERROR !!! LINE=%d\r\n", __LINE__ ));
  186. DBG_BREAK();
  187. };
  188. };
  189. };
  190. #endif
  191. switch( i )
  192. {
  193. case 0:
  194. // Select DMA0
  195. m_pioif->luke2.IO_CONT &= 0xFFFFFFF8;
  196. break;
  197. case 1:
  198. // Select DMA1
  199. m_pioif->luke2.IO_CONT = ( m_pioif->luke2.IO_CONT & 0xFFFFFFF8 ) | 0x04;
  200. break;
  201. default:
  202. DBG_BREAK();
  203. return HAL_ERROR;
  204. };
  205. m_pioif->luke2.IO_MADR = (DWORD)pData->GetBuffPointer();
  206. m_pioif->luke2.IO_MTC = pData->GetSize() -1;
  207. switch( i )
  208. {
  209. case 0:
  210. // Start DMA0
  211. m_DmaFifo.AddItem( 0 );
  212. m_pioif->luke2.IO_CONT = ( m_pioif->luke2.IO_CONT & 0xFFFFFFF8 ) | 0x01;
  213. break;
  214. case 1:
  215. // Start DMA1
  216. m_DmaFifo.AddItem( 1 );
  217. m_pioif->luke2.IO_CONT = ( m_pioif->luke2.IO_CONT & 0xFFFFFFF8 ) | 0x04 | 0x02;
  218. break;
  219. default:
  220. DBG_BREAK();
  221. return HAL_ERROR;
  222. };
  223. return HAL_SUCCESS;
  224. };
  225. //---------------------------------------
  226. // CMixHALStream::SetTransferMode
  227. //---------------------------------------
  228. HALRESULT CMixHALStream::SetTransferMode( HALSTREAMMODE dwStreamMode )
  229. {
  230. // check power state
  231. POWERSTATE PowerState;
  232. ASSERT( m_pZiVABoard != NULL );
  233. m_pZiVABoard->GetPowerState( &PowerState );
  234. if( PowerState == POWERSTATE_OFF )
  235. {
  236. DBG_BREAK();
  237. return HAL_ERROR;
  238. };
  239. switch( dwStreamMode )
  240. {
  241. case HALSTREAM_DVD_MODE:
  242. if( ZiVADVDMode() == FALSE )
  243. {
  244. DBG_BREAK();
  245. return HAL_ERROR;
  246. };
  247. break;
  248. default:
  249. return HAL_NOT_IMPLEMENT;
  250. }
  251. return HAL_SUCCESS;
  252. };
  253. //---------------------------------------
  254. // CMixHALStream::GetAvailableQueue
  255. //---------------------------------------
  256. HALRESULT CMixHALStream::GetAvailableQueue( DWORD *pQueueNum )
  257. {
  258. ASSERT( m_pKernelObj != NULL );
  259. CAutoHwInt hwintlock( m_pKernelObj );
  260. *pQueueNum = m_HalFifo.GetMaxSize() - m_HalFifo.GetItemNum();
  261. // *pQueueNum = m_DmaFifo.GetMaxSize() - m_DmaFifo.GetItemNum();
  262. return HAL_SUCCESS;
  263. };
  264. //---------------------------------------
  265. // CMixHALStream::SetPlayNormal
  266. //---------------------------------------
  267. HALRESULT CMixHALStream::SetPlayNormal( void )
  268. {
  269. ASSERT( m_pZiVA != NULL );
  270. // check power state
  271. POWERSTATE PowerState;
  272. ASSERT( m_pZiVABoard != NULL );
  273. m_pZiVABoard->GetPowerState( &PowerState );
  274. if( PowerState == POWERSTATE_OFF )
  275. {
  276. DBG_BREAK();
  277. return HAL_ERROR;
  278. };
  279. VideoProperty_SkipFieldControl_Value ContData;
  280. m_pZiVABoard->GetVideoProperty_SkipFieldControl( &ContData );
  281. if( ContData == SkipFieldControl_On )
  282. m_pZiVA->INT_MASK = m_pZiVABoard->GetEventIntMask() | ZIVA_INT_VSYNC;
  283. else
  284. m_pZiVA->INT_MASK = m_pZiVABoard->GetEventIntMask();
  285. if( ZIVA_STATE_PLAY != m_pZiVA->PROC_STATE )
  286. m_pZiVA->Resume();
  287. DWORD Volume;
  288. m_pZiVABoard->GetAudioProperty_Volume( (PVOID)&Volume );
  289. m_pZiVABoard->SetAudioProperty_Volume( (PVOID)&Volume );
  290. if( ZiVAStatusWait( ZIVA_STATE_PLAY ) == FALSE )
  291. {
  292. DBG_BREAK();
  293. return HAL_ERROR;
  294. };
  295. fCanSendData = TRUE;
  296. fCanDMA = TRUE;
  297. m_StreamState = StreamPlay;
  298. DeFifo();
  299. return HAL_SUCCESS;
  300. };
  301. //---------------------------------------
  302. // CMixHALStream::SetPlaySlow
  303. //---------------------------------------
  304. HALRESULT CMixHALStream::SetPlaySlow( DWORD SlowFlag )
  305. {
  306. ASSERT( m_pZiVA != NULL );
  307. // check power state
  308. POWERSTATE PowerState;
  309. ASSERT( m_pZiVABoard != NULL );
  310. m_pZiVABoard->GetPowerState( &PowerState );
  311. if( PowerState == POWERSTATE_OFF )
  312. {
  313. DBG_BREAK();
  314. return HAL_ERROR;
  315. };
  316. if( (SlowFlag>31)||(SlowFlag<2) )
  317. return HAL_INVALID_PARAM;
  318. // ZiVA support 3<=param<=32, & 1.5<=speed<=16
  319. DWORD SlowSpeed;
  320. SlowSpeed = SlowFlag * 2;
  321. if( SlowSpeed > 32 )
  322. SlowSpeed = 32;
  323. m_pZiVA->AUDIO_ATTENUATION = 0x96; // Audio Mute
  324. m_pZiVA->INT_MASK = m_pZiVABoard->GetEventIntMask();
  325. VideoProperty_TVSystem_Value TvSystem = TV_NTSC;
  326. m_pZiVABoard->GetVideoProperty_TVSystem( &TvSystem );
  327. if( TvSystem == TV_NTSC )
  328. m_pZiVA->SlowMotion( SlowSpeed, 3 );
  329. else
  330. m_pZiVA->SlowMotion( SlowSpeed, 1 );
  331. if( ZiVAStatusWait( ZIVA_STATE_SLOWMOTION ) == FALSE )
  332. {
  333. DBG_BREAK();
  334. return HAL_ERROR;
  335. };
  336. fCanSendData = TRUE;
  337. fCanDMA = TRUE;
  338. m_StreamState = StreamSlow;
  339. DeFifo();
  340. return HAL_SUCCESS;
  341. };
  342. //---------------------------------------
  343. // CMixHALStream::SetPlayPause
  344. //---------------------------------------
  345. HALRESULT CMixHALStream::SetPlayPause( void )
  346. {
  347. ASSERT( m_pZiVA != NULL );
  348. // check power state
  349. POWERSTATE PowerState;
  350. ASSERT( m_pZiVABoard != NULL );
  351. m_pZiVABoard->GetPowerState( &PowerState );
  352. if( PowerState == POWERSTATE_OFF )
  353. {
  354. DBG_BREAK();
  355. return HAL_ERROR;
  356. };
  357. m_pZiVA->AUDIO_ATTENUATION = 0x96; // Audio Mute
  358. if( m_StreamState == StreamStop )
  359. {
  360. //#ifdef _WDMDDK_
  361. // CAutoHwInt hwintlock( m_pKernelObj );
  362. //#endif
  363. // wait play
  364. if( m_pZiVABoard->m_NeedPowerOnDelay == TRUE )
  365. {
  366. m_pZiVABoard->m_NeedPowerOnDelay = FALSE;
  367. DWORD CurrTime;
  368. m_pKernelObj->GetTickCount( &CurrTime );
  369. if( CurrTime < m_pZiVABoard->m_PowerOnTime + 600 )
  370. m_pKernelObj->Sleep( m_pZiVABoard->m_PowerOnTime + 600 - CurrTime );
  371. };
  372. for( int counter = 0 ; counter < 5 ; counter ++ )
  373. {
  374. // Play Command Send to ZIVA
  375. //#ifndef _WDMDDK_
  376. m_pKernelObj->DisableHwInt();
  377. //#endif
  378. m_pZiVA->INT_MASK = ZIVA_INT_RDYD;
  379. m_pZiVABoard->ClearRDYDEvent();
  380. //#ifndef _WDMDDK_
  381. m_pKernelObj->EnableHwInt();
  382. //#endif
  383. m_pZiVA->Play( 1, 0, 0, 0 );
  384. // Wait RDYD interrupt
  385. if( m_pZiVABoard->WaitRDYD() == FALSE )
  386. {
  387. DBG_PRINTF( ( "mixhal: SetPlayPause FAIL. LINE = %d\n", __LINE__ ));
  388. DBG_BREAK();
  389. if( counter == 4 )
  390. return HAL_ERROR;
  391. DBG_PRINTF( ( "---------------- retry %d --------------\n", counter ));
  392. // Abort Command Send to ZIVA
  393. //#ifndef _WDMDDK_
  394. m_pKernelObj->DisableHwInt();
  395. //#endif
  396. m_pZiVA->INT_MASK = ZIVA_INT_ENDC;
  397. m_pZiVABoard->ClearENDCEvent();
  398. //#ifndef _WDMDDK_
  399. m_pKernelObj->EnableHwInt();
  400. //#endif
  401. m_pZiVA->Abort( 1 );
  402. // Wait ENDC interrupt
  403. if( m_pZiVABoard->WaitENDC() == FALSE )
  404. {
  405. DBG_PRINTF( ( "mixhal: SetPlayStop FAIL. LINE = %d\n", __LINE__ ));
  406. DBG_BREAK();
  407. return HAL_ERROR;
  408. };
  409. }
  410. else
  411. {
  412. DBG_PRINTF( ( "RDYD OK!\n"));
  413. break;
  414. };
  415. };
  416. m_pZiVA->INT_MASK = (m_pZiVABoard->GetEventIntMask() & (~ZIVA_INT_EPTM));
  417. fCanDMA = FALSE;
  418. //#ifdef _WDMDDK_
  419. // m_pZiVABoard->HALHwInterrupt();
  420. //#endif
  421. }
  422. else
  423. {
  424. m_pZiVA->INT_MASK = (m_pZiVABoard->GetEventIntMask() & (~ZIVA_INT_EPTM));
  425. m_pZiVA->Pause( 3 );
  426. if( ZiVAStatusWait( ZIVA_STATE_PAUSE ) == FALSE )
  427. {
  428. DBG_BREAK();
  429. return HAL_ERROR;
  430. };
  431. fCanDMA = TRUE;
  432. };
  433. fCanSendData = TRUE;
  434. m_StreamState = StreamPause;
  435. return HAL_SUCCESS;
  436. };
  437. //---------------------------------------
  438. // CMixHALStream::SetPlayScan
  439. //---------------------------------------
  440. HALRESULT CMixHALStream::SetPlayScan( DWORD ScanFlag )
  441. {
  442. ASSERT( m_pZiVA != NULL );
  443. // check power state
  444. POWERSTATE PowerState;
  445. ASSERT( m_pZiVABoard != NULL );
  446. m_pZiVABoard->GetPowerState( &PowerState );
  447. if( PowerState == POWERSTATE_OFF )
  448. {
  449. DBG_BREAK();
  450. return HAL_ERROR;
  451. };
  452. m_pZiVA->AUDIO_ATTENUATION = 0x96; // Audio Mute
  453. // Ziva Playback timing host interrupt enable NV, GOP-V
  454. m_pZiVA->INT_MASK = (m_pZiVABoard->GetEventIntMask() & (~ZIVA_INT_EPTM));
  455. switch( ScanFlag )
  456. {
  457. case ScanOnlyI:
  458. m_pZiVA->Scan( 0, 0, 3 );
  459. break;
  460. case ScanIandP:
  461. m_pZiVA->Scan( 1, 0, 3 );
  462. break;
  463. default:
  464. return HAL_ERROR;
  465. };
  466. m_pZiVA->SelectStream( 2, 0xffff );
  467. m_pZiVA->SelectStream( 1, 0xffff );
  468. fCanSendData = TRUE;
  469. fCanDMA = TRUE;
  470. m_StreamState = StreamScan;
  471. DeFifo();
  472. return HAL_SUCCESS;
  473. };
  474. //---------------------------------------
  475. // CMixHALStream::SetPlaySingleStep
  476. //---------------------------------------
  477. HALRESULT CMixHALStream::SetPlaySingleStep( void )
  478. {
  479. ASSERT( m_pZiVA != NULL );
  480. // check power state
  481. POWERSTATE PowerState;
  482. ASSERT( m_pZiVABoard != NULL );
  483. m_pZiVABoard->GetPowerState( &PowerState );
  484. if( PowerState == POWERSTATE_OFF )
  485. {
  486. DBG_BREAK();
  487. return HAL_ERROR;
  488. };
  489. m_pZiVA->AUDIO_ATTENUATION = 0x96; // Audio Mute
  490. m_pZiVA->INT_MASK = m_pZiVABoard->GetEventIntMask();
  491. VideoProperty_TVSystem_Value TvSystem = TV_NTSC;
  492. m_pZiVABoard->GetVideoProperty_TVSystem( &TvSystem );
  493. if( TvSystem == TV_NTSC )
  494. m_pZiVA->SingleStep( 3 );
  495. else
  496. m_pZiVA->SingleStep( 1 );
  497. if( ZiVAStatusWait( ZIVA_STATE_PAUSE ) == FALSE )
  498. {
  499. DBG_BREAK();
  500. return HAL_ERROR;
  501. };
  502. fCanSendData = TRUE;
  503. fCanDMA = TRUE;
  504. m_StreamState = StreamSingleStep;
  505. DeFifo();
  506. return HAL_SUCCESS;
  507. };
  508. //---------------------------------------
  509. // CMixHALStream::SetPlayStop
  510. //---------------------------------------
  511. HALRESULT CMixHALStream::SetPlayStop( void )
  512. {
  513. DBG_PRINTF( ( "mixhal: SetPlayStop called.\n"));
  514. ASSERT( m_pZiVA != NULL );
  515. ASSERT( m_pioif != NULL );
  516. fCanSendData = FALSE;
  517. // check power state
  518. POWERSTATE PowerState;
  519. ASSERT( m_pZiVABoard != NULL );
  520. m_pZiVABoard->GetPowerState( &PowerState );
  521. if( PowerState == POWERSTATE_OFF )
  522. {
  523. IHALBuffer *pFinishBuff;
  524. DWORD Num, DmaNo ;
  525. Num = m_DmaFifo.GetItemNum();
  526. for( DWORD i = 0 ; i < Num ; i ++ )
  527. {
  528. m_DmaFifo.GetItem( &DmaNo );
  529. pFinishBuff = DMAFinish( DmaNo );
  530. if( pFinishBuff != NULL )
  531. m_pZiVABoard->NotifyEvent( &m_pZiVABoard->m_SendDataEventList , (VOID *)pFinishBuff );
  532. };
  533. m_pZiVABoard->m_NaviCount = 0;
  534. m_DmaFifo.Flush();
  535. Num = m_HalFifo.GetItemNum();
  536. for( i = 0 ; i < Num ; i ++ )
  537. {
  538. m_HalFifo.GetItem( &pFinishBuff );
  539. if( pFinishBuff != NULL )
  540. m_pZiVABoard->NotifyEvent( &m_pZiVABoard->m_SendDataEventList , (VOID *)pFinishBuff );
  541. };
  542. m_HalFifo.Flush();
  543. m_StreamState = StreamStop;
  544. fCanDMA = FALSE;
  545. return HAL_SUCCESS;
  546. };
  547. m_pZiVA->AUDIO_ATTENUATION = 0x96; // Audio Mute
  548. m_pKernelObj->Sleep( 40 ); // wait 40 msec for Audio Mute
  549. //#ifdef _WDMDDK_
  550. // {
  551. // CAutoHwInt hwintlock( m_pKernelObj );
  552. //#endif
  553. // Abort Command Send to ZIVA
  554. //#ifndef _WDMDDK_
  555. m_pKernelObj->DisableHwInt();
  556. //#endif
  557. m_pZiVA->INT_MASK = ZIVA_INT_ENDC;
  558. m_pZiVABoard->ClearENDCEvent();
  559. //#ifndef _WDMDDK_
  560. m_pKernelObj->EnableHwInt();
  561. //#endif
  562. m_pZiVA->Abort( 1 );
  563. // Wait ENDC interrupt
  564. if( m_pZiVABoard->WaitENDC() == FALSE )
  565. {
  566. DBG_PRINTF( ( "mixhal: SetPlayStop FAIL. LINE = %d\n", __LINE__ ));
  567. DBG_BREAK();
  568. return HAL_ERROR;
  569. };
  570. // Wait IDLE STATE
  571. CTimeOut TimeOutObj( 1000, 10, m_pKernelObj );
  572. while( TRUE )
  573. {
  574. // Check IDLE State
  575. if( m_pZiVA->PROC_STATE == (DWORD)ZIVA_STATE_IDLE )
  576. break;
  577. TimeOutObj.Sleep();
  578. if( TimeOutObj.CheckTimeOut() == TRUE )
  579. {
  580. DBG_PRINTF( ( "mixhal: SetPlayStop FAIL. ZiVA Status = 0x%x\n", m_pZiVA->PROC_STATE ));
  581. DBG_BREAK();
  582. return HAL_ERROR;
  583. };
  584. };
  585. // Send DMA ABORT Command to LUKE2
  586. //#ifndef _WDMDDK_
  587. m_pKernelObj->DisableHwInt();
  588. //#endif
  589. m_pZiVABoard->ClearMasterAbortEvent();
  590. m_pioif->luke2.IO_INTF |= 0x04; // DMA abort
  591. m_pZiVA->INT_MASK = 0x0000; // disable all ziva interrupt
  592. //#ifndef _WDMDDK_
  593. m_pKernelObj->EnableHwInt();
  594. //#endif
  595. // Wait Master Abort interrupt
  596. if( m_pZiVABoard->WaitMasterAbort() == FALSE )
  597. {
  598. DBG_PRINTF( ( "mixhal: SetPlayStop FAIL. LINE = %d\n", __LINE__ ));
  599. DBG_BREAK();
  600. return HAL_ERROR;
  601. };
  602. //#ifdef _WDMDDK_
  603. // m_pZiVABoard->HALHwInterrupt();
  604. // };
  605. //#endif
  606. ASSERT( m_DmaFifo.GetItemNum() == 0 );
  607. ASSERT( m_HalFifo.GetItemNum() == 0 );
  608. fCanDMA = FALSE;
  609. m_StreamState = StreamStop;
  610. return HAL_SUCCESS;
  611. };
  612. //---------------------------------------
  613. // CMixHALStream::CPPInit
  614. //---------------------------------------
  615. HALRESULT CMixHALStream::CPPInit( void )
  616. {
  617. ASSERT( m_pZiVA != NULL );
  618. ASSERT( m_pKernelObj != NULL );
  619. ASSERT( m_StreamState == StreamStop );
  620. m_CppState = CppState_OK;
  621. // check power state
  622. POWERSTATE PowerState;
  623. ASSERT( m_pZiVABoard != NULL );
  624. m_pZiVABoard->GetPowerState( &PowerState );
  625. if( PowerState == POWERSTATE_OFF )
  626. {
  627. DBG_BREAK();
  628. return HAL_ERROR;
  629. };
  630. //#ifdef _WDMDDK_
  631. // {
  632. // CAutoHwInt hwintlock( m_pKernelObj );
  633. //#endif
  634. // Abort Command Send to ZIVA
  635. //#ifndef _WDMDDK_
  636. m_pKernelObj->DisableHwInt();
  637. //#endif
  638. m_pZiVA->INT_MASK = ZIVA_INT_ENDC;
  639. m_pZiVABoard->ClearENDCEvent();
  640. //#ifndef _WDMDDK_
  641. m_pKernelObj->EnableHwInt();
  642. //#endif
  643. m_pZiVA->Abort( 1 );
  644. // Wait ENDC interrupt
  645. if( m_pZiVABoard->WaitENDC() == FALSE )
  646. {
  647. DBG_PRINTF( ( "mixhal: Abort FAIL. LINE = %d\n", __LINE__ ));
  648. DBG_BREAK();
  649. return HAL_ERROR;
  650. };
  651. CTimeOut TimeOutObj( 1000, 10, m_pKernelObj );
  652. while( TRUE )
  653. {
  654. // Check IDLE State
  655. if( m_pZiVA->PROC_STATE == (DWORD)ZIVA_STATE_IDLE )
  656. break;
  657. TimeOutObj.Sleep();
  658. if( TimeOutObj.CheckTimeOut() == TRUE )
  659. {
  660. DBG_PRINTF( ( "mixhal: CPPInit FAIL. ZiVA Status = 0x%x\n", m_pZiVA->PROC_STATE ));
  661. DBG_BREAK();
  662. return HAL_ERROR;
  663. };
  664. };
  665. //#ifdef _WDMDDK_
  666. // m_pZiVABoard->HALHwInterrupt();
  667. // };
  668. //#endif
  669. m_pZiVA->CppInit( m_pZiVA->KEY_ADDRESS ); // Key Addr Setup
  670. m_pZiVA->KEY_LENGTH = 0x1; // 2048 bytes
  671. m_pZiVA->TransferKey( 1 , 0 ); // TransferKey( 1, 1 )?
  672. // m_pZiVA->KEY_COMMAND = SET_DECRYPTION_MODE;
  673. m_pZiVA->KEY_COMMAND = SET_PASS_THROUGH_MODE;
  674. m_pZiVA->HOST_OPTIONS |= 0x04; // add by H. Yagi 99.03.02
  675. m_pZiVA->KEY_STATUS = SET_NEW_COMMAND;
  676. ZiVACopyProtectStatusCheck( COMMAND_COMPLETE );
  677. m_pZiVA->KEY_COMMAND = RESET_AUTHENTICATION;
  678. m_pZiVA->KEY_STATUS = SET_NEW_COMMAND;
  679. ZiVACopyProtectStatusCheck( COMMAND_COMPLETE );
  680. return HAL_SUCCESS;
  681. };
  682. //---------------------------------------
  683. // CMixHALStream::GetDriveChallenge
  684. //---------------------------------------
  685. HALRESULT CMixHALStream::GetDriveChallenge( UCHAR *pDriveChallenge )
  686. {
  687. ASSERT( m_pZiVA != NULL );
  688. // check power state
  689. POWERSTATE PowerState;
  690. ASSERT( m_pZiVABoard != NULL );
  691. m_pZiVABoard->GetPowerState( &PowerState );
  692. if( PowerState == POWERSTATE_OFF )
  693. {
  694. DBG_PRINTF( ( "mixhal: Copyprotect ERROR!! line=%d\n",__LINE__ ));
  695. DBG_BREAK();
  696. return HAL_ERROR;
  697. };
  698. m_pZiVA->TransferKey( 1 , 0 ); // TransferKey( 1, 1 )?
  699. m_pZiVA->KEY_COMMAND = GET_CHALLENGE_DATA;
  700. m_pZiVA->KEY_STATUS = SET_NEW_COMMAND;
  701. // wait for KEY_COMMAND complete.
  702. if( ZiVACopyProtectStatusCheck( COMMAND_COMPLETE ) == FALSE )
  703. {
  704. DBG_PRINTF( ( "mixhal: Copyprotect ERROR!! line=%d\n",__LINE__ ));
  705. DBG_BREAK();
  706. return HAL_ERROR;
  707. };
  708. pDriveChallenge[0] = (BYTE)m_pZiVA->DRIVE_CHALLENGE_9;
  709. pDriveChallenge[1] = (BYTE)m_pZiVA->DRIVE_CHALLENGE_8;
  710. pDriveChallenge[2] = (BYTE)m_pZiVA->DRIVE_CHALLENGE_7;
  711. pDriveChallenge[3] = (BYTE)m_pZiVA->DRIVE_CHALLENGE_6;
  712. pDriveChallenge[4] = (BYTE)m_pZiVA->DRIVE_CHALLENGE_5;
  713. pDriveChallenge[5] = (BYTE)m_pZiVA->DRIVE_CHALLENGE_4;
  714. pDriveChallenge[6] = (BYTE)m_pZiVA->DRIVE_CHALLENGE_3;
  715. pDriveChallenge[7] = (BYTE)m_pZiVA->DRIVE_CHALLENGE_2;
  716. pDriveChallenge[8] = (BYTE)m_pZiVA->DRIVE_CHALLENGE_1;
  717. pDriveChallenge[9] = (BYTE)m_pZiVA->DRIVE_CHALLENGE_0;
  718. return HAL_SUCCESS;
  719. };
  720. //---------------------------------------
  721. // CMixHALStream::SetDriveResponse
  722. //---------------------------------------
  723. HALRESULT CMixHALStream::SetDriveResponse( UCHAR *pDriveResponse )
  724. {
  725. ASSERT( m_pZiVA != NULL );
  726. // check power state
  727. POWERSTATE PowerState;
  728. ASSERT( m_pZiVABoard != NULL );
  729. m_pZiVABoard->GetPowerState( &PowerState );
  730. if( PowerState == POWERSTATE_OFF )
  731. {
  732. DBG_PRINTF( ( "mixhal: Copyprotect ERROR!! line=%d\n",__LINE__ ));
  733. DBG_BREAK();
  734. return HAL_ERROR;
  735. };
  736. m_pZiVA->DRIVE_RESULT_4 = pDriveResponse[0];
  737. m_pZiVA->DRIVE_RESULT_3 = pDriveResponse[1];
  738. m_pZiVA->DRIVE_RESULT_2 = pDriveResponse[2];
  739. m_pZiVA->DRIVE_RESULT_1 = pDriveResponse[3];
  740. m_pZiVA->DRIVE_RESULT_0 = pDriveResponse[4];
  741. m_pZiVA->KEY_COMMAND = SEND_RESPONSE_DATA;
  742. m_pZiVA->KEY_STATUS = SET_NEW_COMMAND;
  743. if( ZiVACopyProtectStatusCheck( COMMAND_COMPLETE ) == FALSE )
  744. {
  745. DBG_PRINTF( ( "mixhal: Copyprotect ERROR!! line=%d\n",__LINE__ ));
  746. DBG_BREAK();
  747. return HAL_ERROR;
  748. };
  749. return HAL_SUCCESS;
  750. };
  751. //---------------------------------------
  752. // CMixHALStream::SetDecoderChallenge
  753. //---------------------------------------
  754. HALRESULT CMixHALStream::SetDecoderChallenge( UCHAR *pDecoderChallenge )
  755. {
  756. ASSERT( m_pZiVA != NULL );
  757. // check power state
  758. POWERSTATE PowerState;
  759. ASSERT( m_pZiVABoard != NULL );
  760. m_pZiVABoard->GetPowerState( &PowerState );
  761. if( PowerState == POWERSTATE_OFF )
  762. {
  763. DBG_PRINTF( ( "mixhal: Copyprotect ERROR!! line=%d\n",__LINE__ ));
  764. DBG_BREAK();
  765. return HAL_ERROR;
  766. };
  767. m_pZiVA->DECODER_CHALLENGE_9 = pDecoderChallenge[0];
  768. m_pZiVA->DECODER_CHALLENGE_8 = pDecoderChallenge[1];
  769. m_pZiVA->DECODER_CHALLENGE_7 = pDecoderChallenge[2];
  770. m_pZiVA->DECODER_CHALLENGE_6 = pDecoderChallenge[3];
  771. m_pZiVA->DECODER_CHALLENGE_5 = pDecoderChallenge[4];
  772. m_pZiVA->DECODER_CHALLENGE_4 = pDecoderChallenge[5];
  773. m_pZiVA->DECODER_CHALLENGE_3 = pDecoderChallenge[6];
  774. m_pZiVA->DECODER_CHALLENGE_2 = pDecoderChallenge[7];
  775. m_pZiVA->DECODER_CHALLENGE_1 = pDecoderChallenge[8];
  776. m_pZiVA->DECODER_CHALLENGE_0 = pDecoderChallenge[9];
  777. m_pZiVA->KEY_COMMAND = SEND_CHALLENGE_DATA;
  778. m_pZiVA->KEY_STATUS = SET_NEW_COMMAND;
  779. if( ZiVACopyProtectStatusCheck( COMMAND_COMPLETE ) == FALSE )
  780. {
  781. DBG_PRINTF( ( "mixhal: Copyprotect ERROR!! line=%d\n",__LINE__ ));
  782. DBG_BREAK();
  783. return HAL_ERROR;
  784. };
  785. return HAL_SUCCESS;
  786. };
  787. //---------------------------------------
  788. // CMixHALStream::GetDecoderResponse
  789. //---------------------------------------
  790. HALRESULT CMixHALStream::GetDecoderResponse( UCHAR *pDecoderResponse )
  791. {
  792. ASSERT( m_pZiVA != NULL );
  793. // check power state
  794. POWERSTATE PowerState;
  795. ASSERT( m_pZiVABoard != NULL );
  796. m_pZiVABoard->GetPowerState( &PowerState );
  797. if( PowerState == POWERSTATE_OFF )
  798. {
  799. DBG_PRINTF( ( "mixhal: Copyprotect ERROR!! line=%d\n",__LINE__ ));
  800. DBG_BREAK();
  801. return HAL_ERROR;
  802. };
  803. m_pZiVA->KEY_COMMAND = GET_RESPONSE_DATA;
  804. m_pZiVA->KEY_STATUS = SET_NEW_COMMAND;
  805. if( ZiVACopyProtectStatusCheck( COMMAND_COMPLETE ) == FALSE )
  806. {
  807. DBG_PRINTF( ( "mixhal: Copyprotect ERROR!! line=%d\n",__LINE__ ));
  808. DBG_BREAK();
  809. return HAL_ERROR;
  810. };
  811. pDecoderResponse[0] = (BYTE)m_pZiVA->DECODER_RESULT_4;
  812. pDecoderResponse[1] = (BYTE)m_pZiVA->DECODER_RESULT_3;
  813. pDecoderResponse[2] = (BYTE)m_pZiVA->DECODER_RESULT_2;
  814. pDecoderResponse[3] = (BYTE)m_pZiVA->DECODER_RESULT_1;
  815. pDecoderResponse[4] = (BYTE)m_pZiVA->DECODER_RESULT_0;
  816. return HAL_SUCCESS;
  817. };
  818. //---------------------------------------
  819. // CMixHALStream::SetDiskKey
  820. //---------------------------------------
  821. HALRESULT CMixHALStream::SetDiskKey( UCHAR *pDiskKey )
  822. {
  823. // check power state
  824. POWERSTATE PowerState;
  825. ASSERT( m_pZiVABoard != NULL );
  826. m_pZiVABoard->GetPowerState( &PowerState );
  827. if( PowerState == POWERSTATE_OFF )
  828. {
  829. DBG_PRINTF( ( "mixhal: Copyprotect ERROR!! line=%d\n",__LINE__ ));
  830. DBG_BREAK();
  831. return HAL_ERROR;
  832. };
  833. m_pZiVA->KEY_COMMAND = SEND_DISK_KEY;
  834. m_pZiVA->KEY_STATUS = SET_NEW_COMMAND;
  835. // wait for KEY_COMMAND complete.
  836. if( ZiVACopyProtectStatusCheck( READY_DKEY ) == FALSE )
  837. {
  838. DBG_PRINTF( ( "mixhal: Copyprotect ERROR!! line=%d\n",__LINE__ ));
  839. DBG_BREAK();
  840. return HAL_ERROR;
  841. };
  842. // DATA Transfer By DMA!!
  843. DWORD QueueNum;
  844. GetAvailableQueue( &QueueNum );
  845. // check DMA
  846. if( QueueNum != ZIVA_QUEUE_SIZE )
  847. {
  848. DBG_PRINTF( ( "mixhal: Copyprotect ERROR!! line=%d\n",__LINE__ ));
  849. DBG_BREAK();
  850. return HAL_ERROR;
  851. };
  852. // Check MY DMA Buffer
  853. if( m_pZiVABoard->GetDMABufferPhysicalAddr() == 0
  854. || m_pZiVABoard->GetDMABufferLinearAddr() == 0 )
  855. {
  856. DBG_PRINTF( ( "mixhal: Copyprotect ERROR!! line=%d\n",__LINE__ ));
  857. DBG_BREAK();
  858. return HAL_ERROR;
  859. };
  860. UCHAR *pDMABuffer = (UCHAR *)m_pZiVABoard->GetDMABufferLinearAddr();
  861. // copy to My DMA Buffer
  862. for( int i = 0 ; i < 2048 ; i ++ )
  863. pDMABuffer[i] = pDiskKey[i];
  864. //// output debug info.
  865. // DBG_PRINTF( ("!!!!!!! Disc Key Transfer\n\r") );
  866. // ULONG k, j;
  867. // for( k=0; k<2048; ){
  868. // DBG_PRINTF( ("DISCKEY: ") );
  869. // for( j=0; j<8 && k<2048; j++, k++ ){
  870. // DBG_PRINTF( ("0x%02x ", (UCHAR)pDMABuffer[k] ) );
  871. // }
  872. // DBG_PRINTF( ("\n\r") );
  873. // }
  874. // Select DMA0
  875. m_pioif->luke2.IO_CONT &= 0xFFFFFFF8;
  876. m_pioif->luke2.IO_MADR = m_pZiVABoard->GetDMABufferPhysicalAddr();
  877. m_pioif->luke2.IO_MTC = 2048 -1;
  878. // DMA0 START!!
  879. m_pioif->luke2.IO_CONT = ( m_pioif->luke2.IO_CONT & 0xFFFFFFF8 ) | 0x01;
  880. // wait for transfering Disk-Key
  881. if( ZiVACopyProtectStatusCheck( COMMAND_COMPLETE ) == FALSE )
  882. {
  883. DBG_PRINTF( ( "mixhal: Copyprotect ERROR!! line=%d\n",__LINE__ ));
  884. DBG_BREAK();
  885. m_CppState = CppState_Error; // Yagi 98.02.09
  886. // return HAL_ERROR; // Yagi 98.02.09
  887. };
  888. m_pZiVA->KEY_COMMAND = RESET_AUTHENTICATION;
  889. m_pZiVA->KEY_STATUS = SET_NEW_COMMAND;
  890. // wait KEY_COMMAND
  891. if( ZiVACopyProtectStatusCheck( COMMAND_COMPLETE ) == FALSE )
  892. {
  893. DBG_PRINTF( ( "mixhal: Copyprotect ERROR!! line=%d\n",__LINE__ ));
  894. DBG_BREAK();
  895. return HAL_ERROR;
  896. };
  897. if( m_CppState!=CppState_OK ){
  898. return( HAL_ERROR );
  899. }else{
  900. return HAL_SUCCESS;
  901. }
  902. };
  903. //---------------------------------------
  904. // CMixHALStream::SetTitleKey
  905. //---------------------------------------
  906. HALRESULT CMixHALStream::SetTitleKey( UCHAR *pTitleKey )
  907. {
  908. ASSERT( m_pZiVA != NULL );
  909. // check power state
  910. POWERSTATE PowerState;
  911. ASSERT( m_pZiVABoard != NULL );
  912. m_pZiVABoard->GetPowerState( &PowerState );
  913. if( PowerState == POWERSTATE_OFF )
  914. {
  915. DBG_PRINTF( ( "mixhal: Copyprotect ERROR!! line=%d\n",__LINE__ ));
  916. DBG_BREAK();
  917. return HAL_ERROR;
  918. };
  919. m_pZiVA->TITLE_KEY_4 = pTitleKey[1];
  920. m_pZiVA->TITLE_KEY_3 = pTitleKey[2];
  921. m_pZiVA->TITLE_KEY_2 = pTitleKey[3];
  922. m_pZiVA->TITLE_KEY_1 = pTitleKey[4];
  923. m_pZiVA->TITLE_KEY_0 = pTitleKey[5];
  924. m_pZiVA->KEY_COMMAND = SEND_TITLE_KEY;
  925. m_pZiVA->KEY_STATUS = SET_NEW_COMMAND;
  926. // wait foe SEND_TITLE_KEY complete.
  927. if( ZiVACopyProtectStatusCheck( COMMAND_COMPLETE ) == FALSE )
  928. {
  929. DBG_PRINTF( ( "mixhal: Copyprotect ERROR!! line=%d\n",__LINE__ ));
  930. DBG_BREAK();
  931. return HAL_ERROR;
  932. };
  933. // If you remove these commented mark( // ), you can play the bad disk-key
  934. // title(Not encrypted but copy protected info). Yagi 98.02.09
  935. // 98.05.29 H.Yagi
  936. // if( m_CppState != CppState_Error ){
  937. m_pZiVA->KEY_COMMAND = SET_DECRYPTION_MODE;
  938. // }else{
  939. // m_pZiVA->KEY_COMMAND = SET_PASS_THROUGH_MODE;
  940. // m_pZiVA->HOST_OPTIONS |= 0x04;
  941. // }
  942. m_pZiVA->KEY_STATUS = SET_NEW_COMMAND;
  943. if( ZiVACopyProtectStatusCheck( COMMAND_COMPLETE ) == FALSE )
  944. {
  945. DBG_PRINTF( ( "mixhal: Copyprotect ERROR!! line=%d\n",__LINE__ ));
  946. DBG_BREAK();
  947. return HAL_ERROR;
  948. };
  949. m_pZiVA->KEY_COMMAND = RESET_AUTHENTICATION;
  950. m_pZiVA->KEY_STATUS = SET_NEW_COMMAND;
  951. if( ZiVACopyProtectStatusCheck( COMMAND_COMPLETE ) == FALSE )
  952. {
  953. DBG_PRINTF( ( "mixhal: Copyprotect ERROR!! line=%d\n",__LINE__ ));
  954. DBG_BREAK();
  955. return HAL_ERROR;
  956. };
  957. return HAL_SUCCESS;
  958. };
  959. //---------------------------------------
  960. // CMixHALStream::ZiVACopyProtectStatusCheck
  961. //---------------------------------------
  962. BOOL CMixHALStream::ZiVACopyProtectStatusCheck( COPY_PROTECT_COMMAND Cmd )
  963. {
  964. ASSERT( m_pKernelObj != NULL );
  965. // check power state
  966. POWERSTATE PowerState;
  967. ASSERT( m_pZiVABoard != NULL );
  968. m_pZiVABoard->GetPowerState( &PowerState );
  969. if( PowerState == POWERSTATE_OFF )
  970. {
  971. DBG_PRINTF( ( "mixhal: Copyprotect ERROR!! line=%d\n",__LINE__ ));
  972. DBG_BREAK();
  973. return HAL_ERROR;
  974. };
  975. CTimeOut TimeOut( 1000, 10 , m_pKernelObj );
  976. while( TRUE )
  977. {
  978. if( (DWORD)Cmd == m_pZiVA->KEY_STATUS )
  979. return TRUE;
  980. TimeOut.Sleep(); // Sleep
  981. if( TimeOut.CheckTimeOut() == TRUE ){
  982. DBG_PRINTF(("CPP STATUS ERROR = 0x%x\n", m_pZiVA->KEY_STATUS ));
  983. DBG_BREAK();
  984. return FALSE;
  985. };
  986. };
  987. // DBG_BREAK();
  988. // return FALSE;
  989. };
  990. //---------------------------------------
  991. // CMixHALStream::ZiVAStatusWait
  992. //---------------------------------------
  993. BOOL CMixHALStream::ZiVAStatusWait( DWORD Status )
  994. {
  995. // debug debug
  996. return TRUE;
  997. // check power state
  998. POWERSTATE PowerState;
  999. ASSERT( m_pZiVABoard != NULL );
  1000. m_pZiVABoard->GetPowerState( &PowerState );
  1001. if( PowerState == POWERSTATE_OFF )
  1002. {
  1003. DBG_BREAK();
  1004. return HAL_ERROR;
  1005. };
  1006. ASSERT( m_pKernelObj != NULL );
  1007. CTimeOut TimeOut( 1000, 10 , m_pKernelObj );
  1008. while( TRUE )
  1009. {
  1010. if( Status == m_pZiVA->PROC_STATE )
  1011. return TRUE;
  1012. TimeOut.Sleep(); // Sleep
  1013. if( TimeOut.CheckTimeOut() == TRUE ){
  1014. DBG_PRINTF(("ZIVA STATUS ERROR = 0x%x\n", m_pZiVA->PROC_STATE ));
  1015. DBG_BREAK();
  1016. return FALSE;
  1017. };
  1018. };
  1019. DBG_BREAK();
  1020. return FALSE;
  1021. };
  1022. //---------------------------------------
  1023. // CMixHALStream::DMAFinish
  1024. //---------------------------------------
  1025. IHALBuffer *CMixHALStream::DMAFinish( DWORD dwDMA_No )
  1026. {
  1027. IHALBuffer *pRetBuff;
  1028. if( ZIVA_QUEUE_SIZE <= dwDMA_No || pQueuedBuff[dwDMA_No] == NULL )
  1029. return NULL;
  1030. pRetBuff = pQueuedBuff[dwDMA_No ];
  1031. pQueuedBuff[dwDMA_No] = NULL;
  1032. return pRetBuff;
  1033. };
  1034. //---------------------------------------
  1035. // CMixHALStream::ZiVADVDMode
  1036. //---------------------------------------
  1037. BOOL CMixHALStream::ZiVADVDMode( void )
  1038. {
  1039. ASSERT( m_pZiVA != NULL );
  1040. ASSERT( m_StreamState == StreamStop );
  1041. // check power state
  1042. POWERSTATE PowerState;
  1043. ASSERT( m_pZiVABoard != NULL );
  1044. m_pZiVABoard->GetPowerState( &PowerState );
  1045. if( PowerState == POWERSTATE_OFF )
  1046. {
  1047. DBG_BREAK();
  1048. return FALSE;
  1049. };
  1050. // Audio Mute
  1051. // m_pioif->luke2.IO_CONT = ( m_pioif->luke2.IO_CONT & 0xffffff00) | 0x40;
  1052. m_pioif->luke2.IO_CONT = ( m_pioif->luke2.IO_CONT & 0xffffff00); // *Luke2Z specification is changed.
  1053. m_pioif->luke2.IO_PSCNT = 0x02; // I don't decide insert it
  1054. // in this place....
  1055. //#ifdef _WDMDDK_
  1056. // {
  1057. // CAutoHwInt hwintlock( m_pKernelObj );
  1058. //#endif
  1059. // Abort Command Send to ZIVA
  1060. //#ifndef _WDMDDK_
  1061. m_pKernelObj->DisableHwInt();
  1062. //#endif
  1063. m_pZiVA->INT_MASK = ZIVA_INT_ENDC;
  1064. m_pZiVABoard->ClearENDCEvent();
  1065. //#ifndef _WDMDDK_
  1066. m_pKernelObj->EnableHwInt();
  1067. //#endif
  1068. m_pZiVA->Abort( 1 );
  1069. // Wait ENDC interrupt
  1070. if( m_pZiVABoard->WaitENDC() == FALSE )
  1071. {
  1072. DBG_PRINTF( ( "mixhal: Abort FAIL. LINE = %d\n", __LINE__ ));
  1073. DBG_BREAK();
  1074. return HAL_ERROR;
  1075. };
  1076. CTimeOut TimeOutObj( 1000, 10, m_pKernelObj );
  1077. while( TRUE )
  1078. {
  1079. // Check IDLE State
  1080. if( m_pZiVA->PROC_STATE == (DWORD)ZIVA_STATE_IDLE )
  1081. break;
  1082. TimeOutObj.Sleep();
  1083. if( TimeOutObj.CheckTimeOut() == TRUE )
  1084. {
  1085. DBG_PRINTF( ( "ZiVADVDMode ERROR !!! ZiVA Status = 0x%x\n", m_pZiVA->PROC_STATE ));
  1086. DBG_BREAK();
  1087. return HAL_ERROR;
  1088. };
  1089. };
  1090. //#ifdef _WDMDDK_
  1091. // m_pZiVABoard->HALHwInterrupt();
  1092. // };
  1093. //#endif
  1094. // m_pZiVA->VIDEO_ENV_CHANGE = 0x01; // NTSC mode
  1095. m_pZiVA->BITSTREAM_TYPE = 0x00; // OK?
  1096. m_pZiVA->BITSTREAM_SOURCE = 0x00; // OK?
  1097. m_pZiVA->SD_MODE = 0x0D; // OK?
  1098. m_pZiVA->CD_MODE = 0x24; // OK?
  1099. m_pZiVA->AV_SYNC_MODE = 0x01; // SYNC_A/V
  1100. m_pZiVA->DISPLAY_ASPECT_RATIO = 0x00; // outout is 4:3
  1101. m_pZiVA->NewPlayMode();
  1102. // set several data for Audio Parameters.
  1103. // Note that these setting are implemented here now for only
  1104. // H/W debug.
  1105. m_pZiVA->AUDIO_CONFIG = 0x06;
  1106. m_pZiVA->AUDIO_DAC_MODE = 0x8;
  1107. // m_pZiVA->AUDIO_CLOCK_SELECTION = 0x00; // FS384
  1108. m_pZiVA->AUDIO_CLOCK_SELECTION = 0x01; // FS384
  1109. m_pZiVA->IEC_958_DELAY = 0x0;
  1110. m_pZiVA->AUDIO_ATTENUATION = 0x96; // Audio Mute
  1111. m_pZiVA->AU_CLK_INOUT = 0x01; // Toshiba special
  1112. m_pZiVA->HIGHLIGHT_ENABLE = 0x00; // ziva Hilight engine disable.
  1113. // AC-3 setting.
  1114. // Note that these setting are implemented here now for only
  1115. // H/W debug.
  1116. // m_pZiVA->AC3_OUT_MODE = 0x07;
  1117. // m_pZiVA->AC3_OUTPUT_MODE = 0x02;
  1118. m_pZiVA->AC3_OUTPUT_MODE = 0x00; // Dolby Pro-Logic
  1119. m_pZiVA->AC3_OPERATIONAL_MODE = 0x0; // OK?
  1120. m_pZiVA->NEW_AUDIO_CONFIG = 0x01;
  1121. CTimeOut TimeOut2( 1000, 10, m_pKernelObj ); // wait 1s, sleep 1ms
  1122. while( TRUE )
  1123. {
  1124. if( 0 == m_pZiVA->NEW_AUDIO_CONFIG )
  1125. break;
  1126. TimeOut2.Sleep();
  1127. if( TimeOut2.CheckTimeOut()==TRUE )
  1128. {
  1129. DBG_BREAK();
  1130. return FALSE;
  1131. };
  1132. }
  1133. // Audio Mute Off
  1134. // m_pioif->luke2.IO_CONT = m_pioif->luke2.IO_CONT & 0xffffffb8;
  1135. m_pioif->luke2.IO_CONT = ( (m_pioif->luke2.IO_CONT & 0xffffffb8)|0x40 ); // *Luke2Z spec is changed.
  1136. return TRUE;
  1137. };
  1138. //---------------------------------------
  1139. // CMixHALStream::SetDataDirection 1998.03.27 H.Yagi
  1140. //---------------------------------------
  1141. HALRESULT CMixHALStream::SetDataDirection( DirectionType DataType )
  1142. {
  1143. // check power state
  1144. POWERSTATE PowerState;
  1145. ASSERT( m_pZiVABoard != NULL );
  1146. m_pZiVABoard->GetPowerState( &PowerState );
  1147. if( PowerState == POWERSTATE_OFF )
  1148. {
  1149. DBG_BREAK();
  1150. return HAL_ERROR;
  1151. };
  1152. switch( DataType )
  1153. {
  1154. case DataType_NormalAll:
  1155. case DataType_OpositeAll:
  1156. case DataType_IpicOnly:
  1157. return HAL_NOT_IMPLEMENT;
  1158. break;
  1159. default:
  1160. return HAL_NOT_IMPLEMENT;
  1161. }
  1162. return HAL_SUCCESS;
  1163. };
  1164. //---------------------------------------
  1165. // CMixHALStream::GetDataDirection 1998.03.27 H.Yagi
  1166. //---------------------------------------
  1167. HALRESULT CMixHALStream::GetDataDirection( DirectionType *pDataType )
  1168. {
  1169. // check power state
  1170. POWERSTATE PowerState;
  1171. ASSERT( m_pZiVABoard != NULL );
  1172. m_pZiVABoard->GetPowerState( &PowerState );
  1173. if( PowerState == POWERSTATE_OFF )
  1174. {
  1175. DBG_BREAK();
  1176. return HAL_ERROR;
  1177. };
  1178. return HAL_NOT_IMPLEMENT;
  1179. };
  1180. //***************************************************************************
  1181. // End of
  1182. //***************************************************************************