Source code of Windows XP (NT5)
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  1. /*
  2. * Copyright (c) 2000, Intel Corporation
  3. * All rights reserved.
  4. *
  5. * WARRANTY DISCLAIMER
  6. *
  7. * THESE MATERIALS ARE PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  8. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  9. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  10. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
  11. * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  12. * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  13. * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  14. * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
  15. * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
  16. * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THESE
  17. * MATERIALS, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  18. *
  19. * Intel Corporation is the author of the Materials, and requests that all
  20. * problem reports or change requests be submitted to it directly at
  21. * http://developer.intel.com/opensource.
  22. */
  23. /*****************************************************************************/
  24. /* decoder_priv.h */
  25. /*****************************************************************************/
  26. #ifndef _DECODER_PRIV_H_
  27. #define _DECODER_PRIV_H_
  28. #define EM_DECODER_MAX_CLIENTS 20
  29. #define DEFAULT_MACHINE_TYPE EM_DECODER_CPU_P7
  30. #define DEFAULT_MACHINE_MODE EM_DECODER_MODE_EM
  31. typedef struct
  32. {
  33. int is_used;
  34. EM_Decoder_Machine_Type machine_type;
  35. EM_Decoder_Machine_Mode machine_mode;
  36. void ** info_ptr; /*** after dynamic allocation, ***/
  37. /*** info_ptr points to an array ***/
  38. /*** of pointers. The i'th pointer ***/
  39. /*** in the array is a ptr to the ***/
  40. /*** client info. ***/
  41. unsigned long flags;
  42. } Client_Entry;
  43. Client_Entry em_clients_table[EM_DECODER_MAX_CLIENTS];
  44. #define FILL_PREDICATE_INFO(Inst_code, Dinfo_p) \
  45. { \
  46. int pred_no = (IEL_GETDW0(Inst_code) >> EM_PREDICATE_POS) & \
  47. ((1 << EM_PREDICATE_BITS)-1); \
  48. Dinfo_p->pred.valid = TRUE; \
  49. Dinfo_p->pred.value = pred_no; \
  50. Dinfo_p->pred.type = EM_DECODER_PRED_REG; \
  51. Dinfo_p->pred.name = EM_DECODER_REG_P0 + pred_no; \
  52. }
  53. #define GET_BRANCH_BEHAVIOUR_BIT(Inst_code,Bit) \
  54. { \
  55. unsigned int tmp; \
  56. U64 tmp64; \
  57. IEL_SHR(tmp64,(Inst_code),BRANCH_BEHAVIOUR_BIT); \
  58. tmp = IEL_GETDW0(tmp64); \
  59. (Bit) = tmp & 1; \
  60. }
  61. #define EM_DECODER_SET_UNC_ILLEGAL_FAULT(di) ((di)->flags |= EM_DECODER_BIT_UNC_ILLEGAL_FAULT)
  62. /*** Static variables initialization ***/
  63. static const char em_ver_string[] = VER_STR; /*** initialized by Makefile ***/
  64. static const char *em_err_msg[EM_DECODER_LAST_ERROR] =
  65. {
  66. "",
  67. "EM_DECODER_INVALID_SLOT_BRANCH_INST: Instruction must be in the last slot of the current bundle",
  68. "EM_DECODER_MUST_BE_GROUP_LAST: Instruction must be the last in instruction group",
  69. "EM_DECODER_BASE_EQUAL_DEST: Source and destination operands have the same value",
  70. "EM_DECODER_EQUAL_DESTS: Two destination operands have the same value",
  71. "EM_DECODER_ODD_EVEN_DESTS: Both destination floating-point registers have odd or even values",
  72. "EM_DECODER_WRITE_TO_ZERO_REGISTER: Destination general register r0 is invalid",
  73. "EM_DECODER_WRITE_TO_SPECIAL_FP_REGISTER: Destination floating point register is f0 or f1",
  74. "EM_DECODER_REGISTER_VALUE_OUT_OF_RANGE: Register value is out of permitted range",
  75. "EM_DECODER_REGISTER_RESERVED_VALUE: Register operand value is reserved",
  76. "EM_DECODER_IMMEDIATE_VALUE_OUT_OF_RANGE: Immediate operand value is out of permitted range",
  77. "EM_DECODER_IMMEDIATE_INVALID_VALUE: Invalid immediate operand value",
  78. "EM_DECODER_STACK_FRAME_SIZE_OUT_OF_RANGE: Stack frame size is larger than maximum permitted value",
  79. "EM_DECODER_LOCALS_SIZE_LARGER_STACK_FRAME: Size of locals is larger than the stack frame",
  80. "EM_DECODER_ROTATING_SIZE_LARGER_STACK_FRAME: Size of rotating region is larger than the stack frame",
  81. "EM_DECODER_HARD_CODED_PREDICATE_INVALID_VALUE: Invalid hard-coded predicate value",
  82. "EM_DECODER_INVALID_PRM_OPCODE: Instruction contains an invalid opcode",
  83. "EM_DECODER_INVALID_INST_SLOT: Instruction slot is invalid in current bundle",
  84. "EM_DECODER_INVALID_TEMPLATE: Invalid template is specified",
  85. "EM_DECODER_INVALID_CLIENT_ID: Invalid client id",
  86. "EM_DECODER_NULL_PTR: A null pointer was specified in call",
  87. "EM_DECODER_TOO_SHORT_ERR: Instruction buffer is too short for instruction",
  88. "EM_DECODER_ASSOCIATE_MISS: There is an unassociated instruction",
  89. "EM_DECODER_INVALID_INST_ID: Invalid instruction id",
  90. "EM_DECODER_INVALID_MACHINE_MODE: Invalid machine mode",
  91. "EM_DECODER_INVALID_MACHINE_TYPE: Invalid machine type",
  92. "EM_DECODER_INTERNAL_ERROR: Internal data-base collisions"};
  93. typedef enum
  94. {
  95. BEHAVIOUR_UNDEF = 0,
  96. BEHAVIOUR_IGNORE_ON_FALSE_QP,
  97. BEHAVIOUR_FAULT
  98. }Behaviour_ill_opcode;
  99. static const Behaviour_ill_opcode branch_ill_opcode[]=
  100. {
  101. /* 0*/ BEHAVIOUR_UNDEF,
  102. /* 1*/ BEHAVIOUR_FAULT,
  103. /* 2*/ BEHAVIOUR_IGNORE_ON_FALSE_QP,
  104. /* 3*/ BEHAVIOUR_IGNORE_ON_FALSE_QP,
  105. /* 4*/ BEHAVIOUR_FAULT,
  106. /* 5*/ BEHAVIOUR_FAULT,
  107. /* 6*/ BEHAVIOUR_IGNORE_ON_FALSE_QP,
  108. /* 7*/ BEHAVIOUR_IGNORE_ON_FALSE_QP,
  109. /* 8*/ BEHAVIOUR_FAULT,
  110. /* 9*/ BEHAVIOUR_FAULT,
  111. /* a*/ BEHAVIOUR_FAULT,
  112. /* b*/ BEHAVIOUR_FAULT,
  113. /* c*/ BEHAVIOUR_FAULT,
  114. /* d*/ BEHAVIOUR_FAULT,
  115. /* e*/ BEHAVIOUR_FAULT,
  116. /* f*/ BEHAVIOUR_FAULT
  117. };
  118. #define PRED_BEHAVIOUR(trole, maj_op, behav) \
  119. { \
  120. switch(trole) \
  121. { \
  122. case(EM_TEMP_ROLE_MEM): \
  123. case(EM_TEMP_ROLE_INT): \
  124. case(EM_TEMP_ROLE_LONG): \
  125. case(EM_TEMP_ROLE_FP): \
  126. (behav) = BEHAVIOUR_IGNORE_ON_FALSE_QP; \
  127. break; \
  128. case(EM_TEMP_ROLE_BR): \
  129. (behav) = branch_ill_opcode[(maj_op)]; \
  130. break; \
  131. default: \
  132. (behav) = BEHAVIOUR_FAULT; \
  133. } \
  134. }
  135. /* this bit is crtical for machine behaviour within
  136. illegal branch instruction with major opcode 0 */
  137. #define BRANCH_BEHAVIOUR_BIT 32
  138. #endif /* _DECODER_PRIV_H_ */