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495 lines
13 KiB
495 lines
13 KiB
/*++
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Copyright (c) 1989 Microsoft Corporation
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Module Name:
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ixpciint.c
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Abstract:
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All PCI bus interrupt mapping is in this module, so that a real
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system which doesn't have all the limitations which PC PCI
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systems have can replaced this code easly.
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(bus memory & i/o address mappings can also be fix here)
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Author:
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Ken Reneris
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Environment:
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Kernel mode
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Revision History:
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--*/
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#include "halp.h"
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#include "pci.h"
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#include "pcip.h"
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#ifdef WANT_IRQ_ROUTING
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#include "ixpciir.h"
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#endif
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ULONG HalpEisaELCR;
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BOOLEAN HalpDoingCrashDump;
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BOOLEAN HalpPciLockSettings;
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#ifdef ALLOC_PRAGMA
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#pragma alloc_text(PAGE,HalpGetPCIIntOnISABus)
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#pragma alloc_text(PAGE,HalpAdjustPCIResourceList)
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#pragma alloc_text(PAGE,HalpGetISAFixedPCIIrq)
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#endif
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ULONG
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HalpGetPCIIntOnISABus (
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN ULONG BusInterruptLevel,
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IN ULONG BusInterruptVector,
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OUT PKIRQL Irql,
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OUT PKAFFINITY Affinity
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)
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{
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if (BusInterruptLevel < 1) {
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// bogus bus level
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return 0;
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}
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//
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// Current PCI buses just map their IRQs ontop of the ISA space,
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// so foreward this to the isa handler for the isa vector
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// (the isa vector was saved away at either HalSetBusData or
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// IoAssignReosurces time - if someone is trying to connect a
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// PCI interrupt without performing one of those operations first,
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// they are broken).
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//
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return HalGetInterruptVector (
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#ifndef MCA
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Isa, 0,
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#else
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MicroChannel, 0,
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#endif
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BusInterruptLevel ^ IRQXOR,
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0,
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Irql,
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Affinity
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);
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}
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VOID
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HalpPCIPin2ISALine (
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PCI_SLOT_NUMBER SlotNumber,
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IN PPCI_COMMON_CONFIG PciData
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)
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/*++
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This function maps the device's InterruptPin to an InterruptLine
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value.
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On the current PC implementations, the bios has already filled in
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InterruptLine as it's ISA value and there's no portable way to
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change it.
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On a DBG build we adjust InterruptLine just to ensure driver's
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don't connect to it without translating it on the PCI bus.
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--*/
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{
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if (!PciData->u.type0.InterruptPin) {
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return ;
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}
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//
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// On a PC there's no Slot/Pin/Line mapping which needs to
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// be done.
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//
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PciData->u.type0.InterruptLine ^= IRQXOR;
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}
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VOID
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HalpPCIISALine2Pin (
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PCI_SLOT_NUMBER SlotNumber,
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IN PPCI_COMMON_CONFIG PciNewData,
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IN PPCI_COMMON_CONFIG PciOldData
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)
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/*++
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This functions maps the device's InterruptLine to it's
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device specific InterruptPin value.
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On the current PC implementations, this information is
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fixed by the BIOS. Just make sure the value isn't being
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editted since PCI doesn't tell us how to dynically
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connect the interrupt.
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--*/
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{
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if (!PciNewData->u.type0.InterruptPin) {
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return ;
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}
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PciNewData->u.type0.InterruptLine ^= IRQXOR;
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#if DBG
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if (PciNewData->u.type0.InterruptLine != PciOldData->u.type0.InterruptLine ||
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PciNewData->u.type0.InterruptPin != PciOldData->u.type0.InterruptPin) {
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DbgPrint ("HalpPCILine2Pin: System does not support changing the PCI device interrupt routing\n");
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DbgBreakPoint ();
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}
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#endif
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}
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#if !defined(SUBCLASSPCI)
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VOID
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HalpPCIAcquireType2Lock (
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PKSPIN_LOCK SpinLock,
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PKIRQL Irql
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)
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{
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if (!HalpDoingCrashDump) {
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*Irql = KfRaiseIrql (HIGH_LEVEL);
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KiAcquireSpinLock (SpinLock);
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} else {
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*Irql = HIGH_LEVEL;
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}
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}
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VOID
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HalpPCIReleaseType2Lock (
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PKSPIN_LOCK SpinLock,
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KIRQL Irql
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)
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{
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if (!HalpDoingCrashDump) {
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KiReleaseSpinLock (SpinLock);
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KfLowerIrql (Irql);
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}
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}
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#endif
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NTSTATUS
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HalpAdjustPCIResourceList (
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN OUT PIO_RESOURCE_REQUIREMENTS_LIST *pResourceList
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)
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/*++
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Rewrite the callers requested resource list to fit within
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the supported ranges of this bus
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--*/
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{
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NTSTATUS Status;
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PPCIPBUSDATA BusData;
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PCI_SLOT_NUMBER PciSlot;
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PSUPPORTED_RANGE Interrupt;
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PSUPPORTED_RANGE Range, HoldRange;
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PSUPPORTED_RANGES SupportedRanges;
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PPCI_COMMON_CONFIG PciData, PciOrigData;
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UCHAR buffer[PCI_COMMON_HDR_LENGTH];
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UCHAR buffer2[PCI_COMMON_HDR_LENGTH];
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BOOLEAN UseBusRanges;
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ULONG i, j, RomIndex, length, ebit;
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ULONG Base[PCI_TYPE0_ADDRESSES + 1];
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PULONG BaseAddress[PCI_TYPE0_ADDRESSES + 1];
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BusData = (PPCIPBUSDATA) BusHandler->BusData;
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PciSlot = *((PPCI_SLOT_NUMBER) &(*pResourceList)->SlotNumber);
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//
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// Determine PCI device's interrupt restrictions
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//
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Status = BusData->GetIrqRange(BusHandler, RootHandler, PciSlot, &Interrupt);
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if (!NT_SUCCESS(Status)) {
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return Status;
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}
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SupportedRanges = NULL;
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UseBusRanges = TRUE;
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Status = STATUS_INSUFFICIENT_RESOURCES;
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if (HalpPciLockSettings) {
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PciData = (PPCI_COMMON_CONFIG) buffer;
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PciOrigData = (PPCI_COMMON_CONFIG) buffer2;
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HalpReadPCIConfig (BusHandler, PciSlot, PciData, 0, PCI_COMMON_HDR_LENGTH);
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//
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// If this is a device, and it current has its decodes enabled,
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// then use the currently programmed ranges only
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//
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if (PCI_CONFIG_TYPE(PciData) == 0 &&
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(PciData->Command & (PCI_ENABLE_IO_SPACE | PCI_ENABLE_MEMORY_SPACE))) {
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//
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// Save current settings
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//
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RtlMoveMemory (PciOrigData, PciData, PCI_COMMON_HDR_LENGTH);
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for (j=0; j < PCI_TYPE0_ADDRESSES; j++) {
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BaseAddress[j] = &PciData->u.type0.BaseAddresses[j];
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}
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BaseAddress[j] = &PciData->u.type0.ROMBaseAddress;
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RomIndex = j;
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//
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// Write all one-bits to determine lengths for each address
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//
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for (j=0; j < PCI_TYPE0_ADDRESSES + 1; j++) {
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Base[j] = *BaseAddress[j];
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*BaseAddress[j] = 0xFFFFFFFF;
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}
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PciData->Command &= ~(PCI_ENABLE_IO_SPACE | PCI_ENABLE_MEMORY_SPACE);
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*BaseAddress[RomIndex] &= ~PCI_ROMADDRESS_ENABLED;
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HalpWritePCIConfig (BusHandler, PciSlot, PciData, 0, PCI_COMMON_HDR_LENGTH);
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HalpReadPCIConfig (BusHandler, PciSlot, PciData, 0, PCI_COMMON_HDR_LENGTH);
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//
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// restore original settings
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//
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HalpWritePCIConfig (
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BusHandler,
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PciSlot,
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&PciOrigData->Status,
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FIELD_OFFSET (PCI_COMMON_CONFIG, Status),
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PCI_COMMON_HDR_LENGTH - FIELD_OFFSET (PCI_COMMON_CONFIG, Status)
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);
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HalpWritePCIConfig (
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BusHandler,
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PciSlot,
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PciOrigData,
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0,
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FIELD_OFFSET (PCI_COMMON_CONFIG, Status)
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);
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//
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// Build a memory & io range list of just the ranges already
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// programmed into the device
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//
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UseBusRanges = FALSE;
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SupportedRanges = HalpAllocateNewRangeList();
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if (!SupportedRanges) {
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goto CleanUp;
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}
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*BaseAddress[RomIndex] &= ~PCI_ADDRESS_IO_SPACE;
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for (j=0; j < PCI_TYPE0_ADDRESSES + 1; j++) {
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i = *BaseAddress[j];
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if (i & PCI_ADDRESS_IO_SPACE) {
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length = 1 << 2;
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Range = &SupportedRanges->IO;
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ebit = PCI_ENABLE_IO_SPACE;
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} else {
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length = 1 << 4;
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Range = &SupportedRanges->Memory;
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ebit = PCI_ENABLE_MEMORY_SPACE;
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if (i & PCI_ADDRESS_MEMORY_PREFETCHABLE) {
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Range = &SupportedRanges->PrefetchMemory;
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}
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}
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Base[j] &= ~(length-1);
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while (!(i & length) && length) {
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length <<= 1;
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}
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if (j == RomIndex &&
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!(PciOrigData->u.type0.ROMBaseAddress & PCI_ROMADDRESS_ENABLED)) {
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// range not enabled, don't use it
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length = 0;
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}
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if (length) {
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if (!(PciOrigData->Command & ebit)) {
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// range not enabled, don't use preprogrammed values
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UseBusRanges = TRUE;
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}
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if (Range->Limit >= Range->Base) {
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HoldRange = Range->Next;
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Range->Next = ExAllocatePoolWithTag(
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PagedPool,
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sizeof(SUPPORTED_RANGE),
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HAL_POOL_TAG
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);
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Range = Range->Next;
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if (!Range) {
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goto CleanUp;
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}
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Range->Next = HoldRange;
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}
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Range->Base = Base[j];
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Range->Limit = Base[j] + length - 1;
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}
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if (Is64BitBaseAddress(i)) {
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// skip upper half of 64 bit address since this processor
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// only supports 32 bits of address space
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j++;
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}
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}
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}
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}
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//
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// Adjust resources
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//
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Status = HaliAdjustResourceListRange (
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UseBusRanges ? BusHandler->BusAddresses : SupportedRanges,
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Interrupt,
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pResourceList
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);
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CleanUp:
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if (SupportedRanges) {
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HalpFreeRangeList (SupportedRanges);
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}
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ExFreePool (Interrupt);
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return Status;
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}
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NTSTATUS
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HalpGetISAFixedPCIIrq (
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PCI_SLOT_NUMBER PciSlot,
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OUT PSUPPORTED_RANGE *Interrupt
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)
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{
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UCHAR buffer[PCI_COMMON_HDR_LENGTH];
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PPCI_COMMON_CONFIG PciData;
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PciData = (PPCI_COMMON_CONFIG) buffer;
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HalGetBusData (
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PCIConfiguration,
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BusHandler->BusNumber,
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PciSlot.u.AsULONG,
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PciData,
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PCI_COMMON_HDR_LENGTH
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);
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if (PciData->VendorID == PCI_INVALID_VENDORID) {
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return STATUS_UNSUCCESSFUL;
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}
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*Interrupt = ExAllocatePoolWithTag(PagedPool,
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sizeof(SUPPORTED_RANGE),
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HAL_POOL_TAG);
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if (!*Interrupt) {
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return STATUS_INSUFFICIENT_RESOURCES;
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}
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RtlZeroMemory (*Interrupt, sizeof (SUPPORTED_RANGE));
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(*Interrupt)->Base = 1; // base = 1, limit = 0
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if (!PciData->u.type0.InterruptPin) {
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return STATUS_SUCCESS;
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}
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#ifdef WANT_IRQ_ROUTING
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//
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// Let the arbiter decide which Irq this device gets.
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//
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if (IsPciIrqRoutingEnabled()) {
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//
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// If a video card has been enabled by the BIOS
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// and the BIOS did not assign any interrupt to it
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// then assume this device does not need an interrupt.
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//
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if (PciData->Command & (PCI_ENABLE_IO_SPACE | PCI_ENABLE_MEMORY_SPACE)) {
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if ( (PciData->BaseClass == PCI_CLASS_PRE_20 && PciData->SubClass == PCI_SUBCLASS_VID_XGA_CTLR) ||
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(PciData->BaseClass == PCI_CLASS_DISPLAY_CTLR &&
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(PciData->SubClass == PCI_SUBCLASS_VID_VGA_CTLR || PciData->SubClass == PCI_SUBCLASS_VID_XGA_CTLR))) {
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if ( PciData->u.type0.InterruptLine == (0 ^ IRQXOR) ||
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PciData->u.type0.InterruptLine == (0xFF ^ IRQXOR)) {
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#if DBG
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DbgPrint ("HalpGetValidPCIFixedIrq: BIOS did not assign an interrupt to the video device %04X%04X\n", PciData->VendorID, PciData->DeviceID);
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#endif
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//
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// We need to let the caller continue, since the caller may
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// not care that the interrupt vector is connected or not
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//
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return STATUS_SUCCESS;
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}
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}
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}
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//
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// Return all possible interrupts since Pci Irq Routing is enabled.
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//
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(*Interrupt)->Base = 0;
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(*Interrupt)->Limit = 0xFF;
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return STATUS_SUCCESS;
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}
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#endif
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if (PciData->u.type0.InterruptLine == (0 ^ IRQXOR) ||
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PciData->u.type0.InterruptLine == (0xFF ^ IRQXOR)) {
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#if DBG
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DbgPrint ("HalpGetValidPCIFixedIrq: BIOS did not assign an interrupt vector for the device\n");
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#endif
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//
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// We need to let the caller continue, since the caller may
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// not care that the interrupt vector is connected or not
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//
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return STATUS_SUCCESS;
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}
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(*Interrupt)->Base = PciData->u.type0.InterruptLine;
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(*Interrupt)->Limit = PciData->u.type0.InterruptLine;
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return STATUS_SUCCESS;
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}
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