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199 lines
4.0 KiB
199 lines
4.0 KiB
//+-------------------------------------------------------------------------
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//
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// Microsoft Windows
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//
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// Copyright (C) SCM Microsystems, 1998 - 1999
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//
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// File: stc.h
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//
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//--------------------------------------------------------------------------
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#if !defined( __STC_H__ )
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#define __STC_H__
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#define NAD_IDX 0x00
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#define PCB_IDX 0x01
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#define LEN_IDX 0x02
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#define DATA_IDX 0x03
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#define PROLOGUE_LEN 0x03
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#define EPILOGUE_LEN 0x01
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#define PACKET_OVERHEAD 4
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#define OSC 16000
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#define FREQ 3580
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#define CYC_TO_MS( cyc ) ((ULONG)( cyc / FREQ ))
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#define SW_SUCCESS 0x0090
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#define SW_OE 0x0020
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#define SW_FE 0x0040
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#define SW_INSERTED 0xA064
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#define SW_REMOVED 0xA164
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// register addresses
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#define ADR_ETULENGTH15 0x00
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#define ADR_ETULENGTH7 0x01
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#define ADR_CGT8 0x02
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#define ADR_CGT7 0x03
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#define ADR_CWT31 0x04
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#define ADR_CWT23 0x05
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#define ADR_CWT15 0x06
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#define ADR_CWT7 0x07
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#define ADR_BGT8 0x08
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#define ADR_BGT7 0x09
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#define ADR_BWT31 0x0A
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#define ADR_BWT23 0x0B
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#define ADR_BWT15 0x0C
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#define ADR_BWT7 0x0D
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#define ADR_TCON 0x0E
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#define ADR_UART_CONTROL 0x0F
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#define ADR_FIFO_CONFIG 0x10
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#define ADR_INT_CONTROL 0x11
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#define ADR_INT_STATUS 0x12
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#define ADR_DATA 0x13
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#define ADR_IO_CONFIG 0x14
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#define ADR_SC_CONTROL 0x15
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#define ADR_CLOCK_CONTROL 0x16
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// clock control register
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#define M_CKE 0x01
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#define M_OEN 0x02
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// ETU length register
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#define M_ETU_RST 0x80
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#define M_DIV 0x30
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#define M_DIV1 0x20
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#define M_DIV0 0x10
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#define M_ETUH 0x0F
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#define M_ETUL 0xFF
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// CGT length register
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#define M_CGTH 0x01
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#define M_CGTL 0XFF
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// BGT length register
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#define M_BGTH 0x01
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#define M_BGTL 0xFF
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// CWT register
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#define M_CWT4 0xFF
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#define M_CWT3 0xFF
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#define M_CWT2 0xFF
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#define M_CWT1 0xFF
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// TCON register
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#define M_MGT 0x80
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#define M_MWT 0x40
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#define M_WTR 0x04
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#define M_GT 0x02
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#define M_WT 0x01
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// UART control register
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#define M_UEN 0x40
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#define M_UART_RST 0x20
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#define M_CONV 0x10
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#define M_TS 0x08
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#define M_PE 0x04
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#define M_R 0x03
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// FIFO config register
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#define M_RFP 0x80
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#define M_LD 0x0F
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// INT control register
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#define M_SSL 0x20
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#define M_DRM 0x10
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#define M_DSM 0x08
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#define M_WTE 0x04
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#define M_SIM 0x02
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#define M_MEM 0x01
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#define M_DRM_MEM 0x11
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// INT status register
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#define M_FNE 0x80
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#define M_FE 0x40
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#define M_OE 0x20
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#define M_DR 0x10
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#define M_TRE 0x08
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#define M_WTOVF 0x04
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#define M_SENSE 0x02
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#define M_MOV 0x01
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// SMART card interface
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#define M_ALT1 0x20
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#define M_ALT2 0x10
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#define M_ALT0 0x08
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#define M_SDE 0x04
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#define M_SL 0x02
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#define M_SD 0x01
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// SMART card control register
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#define M_IO 0x80
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#define M_VCE 0x40
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#define M_SC_RST 0x20
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#define M_SCE 0x10
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#define M_SCK 0x08
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#define M_C8 0x04
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#define M_C4 0x02
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#define M_VPE 0x01
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// Nad
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#define HOST_TO_STC1 0x12
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#define HOST_TO_STC2 0x52
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#define HOST_TO_ICC1 0x02
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#define HOST_TO_ICC2 0x42
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#define STC1_TO_HOST 0x21
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#define STC2_TO_HOST 0x25
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#define ICC1_TO_HOST 0x20
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#define ICC2_TO_HOST 0x24
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// PCB
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#define PCB 0x00
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#define CLA_READ_REGISTER 0x00
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#define INS_READ_REGISTER 0xB0
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#define CLA_WRITE_REGISTER 0x00
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#define INS_WRITE_REGISTER 0xD0
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#define CLA_READ_FIRMWARE_REVISION 0x00
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#define INS_READ_FIRMWARE_REVISION 0xB1
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#define PCB_DEFAULT 0x00
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#define TLV_BUFFER_SIZE 0x20
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#define ATR_SIZE 0x40 // TS + 32 + SW + PROLOGUE + EPILOGUE...
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#define MAX_T1_BLOCK_SIZE 270
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// ATR interface byte coding in TS
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#define TAx 0x01
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#define TBx 0x02
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#define TCx 0x04
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#define TDx 0x08
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#define FREQ_DIV 1 // 3,58 MHz XTAL -> SC Clock = 3.58MHz
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//#define FREQ_DIV 0x08 /* 30MHz XTAL -> SC Clock = 3.75MHz */
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#define PROTOCOL_TO 0
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#define PROTOCOL_T1 1
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#define PROTOCOL_T14 14
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#define PROTOCOL_T15 15
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//
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// DATA TYPES
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//
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typedef struct _STC_REGISTER
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{
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UCHAR Register;
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UCHAR Size;
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ULONG Value;
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} STC_REGISTER, *PSTC_REGISTER;
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#endif // ! __STC_H__
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