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380 lines
16 KiB
380 lines
16 KiB
/*
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* $Log: V:/Flite/archives/TrueFFS5/Src/MDOCPLUS.H_V $
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*
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* Rev 1.14 Apr 15 2002 07:37:48 oris
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* Added OUT_CNTRL_STICKY_BIT_ENABLE definition.
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* Added FOUNDRY_WRITE_ENABLE definition.
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* Changed OUT_CNTRL_BSY_EN_MASK to OUT_CNTRL_BSY_DISABLE_MASK and used the complimentary value.
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*
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* Rev 1.13 Jan 29 2002 20:09:50 oris
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* Added IPL_SA_MODE_MARK and IPL_XSCALE_MODE_MARK definitions.
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* Changed DPS1_COPY0_16 to unit 3 instead of unit 2.
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* Changed IPL_SA_MARK_OFFSET1 to IPL_MODE_MARK_OFFSET.
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*
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* Rev 1.12 Jan 17 2002 23:03:12 oris
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* Changed flash addresses to interleave-1 to fit both 32MB and 16MB Plus DiskOnChip devices
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* include docsys file instead of docsysp.
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* Add 16MB Plus DiskOnChip ID 0x41
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*
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* Rev 1.11 Nov 22 2001 19:48:56 oris
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* Changed FLS__SEL_WP_MASK and FLS__SEL_CE_MASK to MPLUS_SEL_CE and MPLUS_SEL_WP.
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*
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* Rev 1.10 Sep 15 2001 23:47:26 oris
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* Include docsysp.h instead of docsys.h
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*
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* Rev 1.9 Jul 13 2001 01:08:20 oris
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* Added BBT_MEDIA_OFFSET definition.
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* Moved VERIFY_WRITE and VERIFY_ERASE compilation flag to flcustom.h.
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*
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* Rev 1.8 May 16 2001 21:20:44 oris
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* Added busy delay for download operation DOWNLOAD_BUSY_DELAY.
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* Moved SYNDROM_BYTES definition to flflash.h.
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*
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* Rev 1.7 May 09 2001 00:33:24 oris
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* Removed the IPL_CODE and READ_BBT_CODE defintion.
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*
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* Rev 1.6 May 06 2001 22:42:12 oris
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* redundant was misspelled.
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*
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* Rev 1.5 Apr 30 2001 18:02:40 oris
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* Added READ_BBT_CODE defintion.
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*
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* Rev 1.4 Apr 24 2001 17:11:40 oris
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* Bug fix - otp start address definition did not take interleave into acount.
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*
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* Rev 1.3 Apr 18 2001 21:25:58 oris
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* Added OTPLockStruct record.
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*
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* Rev 1.2 Apr 16 2001 13:55:20 oris
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* Removed warrnings.
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*
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* Rev 1.1 Apr 09 2001 15:08:22 oris
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* End with an empty line.
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*
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* Rev 1.0 Apr 01 2001 07:42:32 oris
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* Initial revision.
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*
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*/
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/*******************************************************************
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*
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* DESCRIPTION: basic mtd functions for the MDOC32
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*
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* AUTHOR: arie tamam
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*
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* HISTORY: created november 14, 2000
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*
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*******************************************************************/
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/***********************************************************************************/
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/* M-Systems Confidential */
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/* Copyright (C) M-Systems Flash Disk Pioneers Ltd. 1995-2001 */
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/* All Rights Reserved */
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/***********************************************************************************/
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/* NOTICE OF M-SYSTEMS OEM */
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/* SOFTWARE LICENSE AGREEMENT */
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/* */
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/* THE USE OF THIS SOFTWARE IS GOVERNED BY A SEPARATE LICENSE */
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/* AGREEMENT BETWEEN THE OEM AND M-SYSTEMS. REFER TO THAT AGREEMENT */
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/* FOR THE SPECIFIC TERMS AND CONDITIONS OF USE, */
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/* OR CONTACT M-SYSTEMS FOR LICENSE ASSISTANCE: */
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/* E-MAIL = [email protected] */
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/***********************************************************************************/
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#ifndef MDOCPLUS_H
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#define MDOCPLUS_H
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/** include files **/
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#include "docsys.h"
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/** public functions **/
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extern FLStatus changeInterleave(FLFlash vol, byte interNum);
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extern FLStatus chkASICmode (FLFlash vol);
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#ifndef MTD_STANDALONE
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extern FLBoolean checkWinForDOCPLUS(unsigned driveNo, NDOC2window memWinPtr);
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#endif /* MTD_STANDALONE */
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/*ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ.*/
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/* Feature list */
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/*ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ.*/
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/* #define MULTI_ERASE */ /* use multiple block erase feature */
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/* #define WIN_FROM_SS */ /* call Socket Services to get window location */
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/* #define LOG_FILE */ /* log edc errors */
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/*----------------------------------------------------------------------*/
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/* s e t F l o o r */
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/* */
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/* Set the specified floor as the active floor. */
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/* */
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/* Parameters: */
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/* vol : Pointer identifying drive */
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/* floor : The new active floor */
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/* */
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/*----------------------------------------------------------------------*/
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#define setFloor(volume,floor) flWrite8bitRegPlus(volume,NASICselect,floor); /* select ASIC */
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/* The first page of the customer OTP area */
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typedef struct {
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byte lockByte[4];
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LEulong usedSize;
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} OTPLockStruct;
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#define DOWNLOAD_BUSY_DELAY 300000L
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#define BUSY_DELAY 30000
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#define START_ADR 0xC8000L
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#define STOP_ADR 0xF0000L
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#define MDOCP_PAGES_PER_BLOCK 0x20 /* 16 pages per block on a single chip */
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#define CHIP_PAGE_SIZE 0x100 /* Page Size of 2 Mbyte Flash */
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#define IPL_MAX_SIZE 1024l /* IPL maximum media size */
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#define CHIP_TOTAL_SIZE 0x1000000L
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#define SIZE_OF_DPS 0x12
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#define NO_OF_DPS 2
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#define SECTOR_SIZE_MASK 0xff
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#define BBT_MEDIA_OFFSET 2048L
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/* Flash page area sizes */
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#define SECTOR_FLAG_SIZE 2
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#define UNIT_DATA_SIZE 8
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#define EDC_SIZE 6
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#define EDC_PLUS_SECTOR_FLAGS 8
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#define END_OF_SECOND_SECTOR_DATA 10
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#define START_OF_SECOND_SECTOR_DATA 10
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#define UNIT_DATA_OFFSET 16
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#define UNIT_DATA_OFFSET_MINUS_8 8
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#define SECOND_SECTOR_FLAGS_OFFSET 8
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#define TOTAL_EXTRA_AREA 16
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/* OTP defintions */
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#define OTP_LOCK_MARK 0
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#define CUSTOMER_OTP_SIZE 6*1024
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#define CUSTOMER_OTP_START SECTOR_SIZE*6L
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#define UNIQUE_ID_OFFSET 0x10
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#define UNIQUE_ID_SIZE 16
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/* IPL flash media offsets */
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#define IPL_START_OFFSET (SECTOR_SIZE<<1)
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#define IPL_HIGH_SECTOR (SECTOR_SIZE<<1)
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#define IPL0_COPY0_32 (flash->erasableBlockSize << 1) + IPL_START_OFFSET/* Unit 2 + 1024 */
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#define IPL1_COPY0_32 IPL0_COPY0_32 + IPL_HIGH_SECTOR /* Unit 2 + 2048 */
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#define IPL0_COPY0_16 (flash->erasableBlockSize * 3) + IPL_START_OFFSET /* Unit 3 + 1024 */
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#define IPL1_COPY0_16 IPL0_COPY0_16 + IPL_HIGH_SECTOR /* Unit 3 + 2048 */
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/* DPS flash media offsets */
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#define REDUNDANT_DPS_OFFSET (SECTOR_SIZE+0x80)
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#define DPS0_COPY0 flash->erasableBlockSize /* Unit 1 */
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#define DPS1_COPY0_32 (flash->erasableBlockSize<<1L) /* Unit 2 */
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#define DPS1_COPY0_16 (flash->erasableBlockSize*3L) /* Unit 3 */
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#define DPS0_UNIT_NO 1
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#define DPS1_UNIT_NO_32 2
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#define DPS1_UNIT_NO_16 3
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/* Strong arm mark offset */
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#define IPL_MODE_MARK_OFFSET IPL1_COPY0_16+8
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#define IPL_SA_MODE_MARK 0xF8 /* Strong Arm */
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#define IPL_XSCALE_MODE_MARK 0X8F /* X-Scale */
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/* miscellaneous limits */
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#define MAX_FLASH_DEVICES_MDOCP 1 /* maximum flash inside one MDOC */
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#define MAX_FLOORS 4
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#define CHIP_ID_MDOCP 0x40 /* MDOCP 32MB chip identification value */
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#define CHIP_ID_MDOCP16 0x41 /* MDOCP 16MB chip identification value */
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#define MDOC_ALIAS_RANGE 0x100
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#define ALIAS_RESOLUTION (MAX_FLASH_DEVICES_MDOCP + 10)
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/*ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿
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³ Definition for writing boot image ³
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ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ*/
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#define SPL_SIZE 0x2000 /* 8 KBytes */
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#define MAX_CODE_MODULES 6 /* max number of code modules in boot area (incl. SPL) */
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/*-----------------------------------------
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| Definition of MDOC32 memory window |
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----------------------------------------*/
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/* MDOC32 memory window layout :
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0000 .... 07FF RAM ( 1KB aliased across 2KB)
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0800 .... 0FFF Flash Data Register (2KB alias of address 1028H-1029H)
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1000 Chip Identification register
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1002 NOP register
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1004 Alias Resolution register
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1006 DOC Control register
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1008 Device ID select register
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100a Configuration Input register
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100c Output Control register
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100e Interrupt Control register
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1012 Output Enable Delay register
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101E - 101F Flash Slow Read register[1:0]
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1020 Flash Control Register
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1022 Flash Select register
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1024 Flash Command register
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1026 Flash Address register
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1028-1029 Flash Data Register
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102A Read Pipeline Initialization register
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102C-102D Last Data Read register
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102E Write Pipeline Termination register
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1040-1045 ECC Syndrome register[5:0]
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1046 ECC Control register
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1048 Customer OTP Pointer register
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105A Flash Geometry register
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105C-105D Data Protect Structure Status register[1:0]
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105E-105f Data Protect Structure Pointer register[1:0]
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1060-1063 Data Protect Lower Address register 0 [3:0]
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1064-1067 Data Protect Upper Address register 0 [3:0]
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1068-106B Data Protect Lower Address register 1 [3:0]
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106C-106F Data Protect Upper Address register 1 [3:0]
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1070 Data Protect Key register[0]
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1072 Data Protect Key register[1]
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1074 Download status register
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1076 DOC Control Confirmation register
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1078 Protection Status register
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107E Foundry Test register
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1800-1FFE RAM (1KB aliased across 2KB)
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1FFF Release from power down mode
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*/
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#define Nio 0x800 /* Flash Data Register (2KB alias of address 1028H-1029H) read/write */
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#define NIPLpart2 0x800 /* Flash Data Register (2KB alias of address 1028H-1029H) read/write */
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#define NchipId 0x1000 /* Chip Identification register. read */
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#define ID_FAMILY_MASK 0xf0 /* family . */
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#define ID_VERSION_MASK 0x7 /* version. */
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#define NNOPreg 0x1002 /* NOP register. read/write */
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#define NaliasResolution 0x1004 /* Alias Resolution register. read write */
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/* Asic controll register */
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#define NDOCcontrol 0x1006 /* DOC Control register. read/write */
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#define NDOCcontrolConfirm 0x1076 /*DOC Control Confirmation register.read only*/
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#define DOC_CNTRL_RAM_WE_MASK 0x20 /* ram write enable. 1=allow write to RAM. */
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#define DOC_CNTRL_RST_LAT_MASK 0x10 /* reset mode latched. */
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#define DOC_CNTRL_BDETCT_MASK 0x8 /* boot detect. */
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#define DOC_CNTRL_MDWREN_MASK 0x4 /* mode write enable. */
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#define DOC_CNTRL_MODE_MASK 0x3 /* mode of operation. 00=reset, 01=normal, 1x=power down */
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#define DOC_CNTRL_MODE_RESET 0x0 /* Reset mode + MDWREN */
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#define DOC_CNTRL_MODE_NORMAL 0x1 /* Normal mode + MDWREN */
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#define DOC_CNTRL_MODE_PWR_DWN 0x2 /* Power down mode + MDWREN */
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/* The modes are ORed with the following state:
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a) Do not enable ram write. ~0x20
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b) Reset the reset mode latche. 0x10
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c) Reset the boot detect latche 0x08
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d) Enable writing new mode 0x04
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e) Clear mode bits 2 LSB */
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#define DOC_CNTRL_DEFAULT 0x1c
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#define NASICselect 0x1008 /* Device ID select register. read/ write */
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#define ASIC_SELECT_ID_MASK 0x3 /* identification */
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#define NconfigInput 0x100A /* Configuration Input register. read/write */
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#define CONFIG_IF_CFG_MASK 0x80 /* state of IF_CFG input pin. */
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#define CONFIG_MAX_ID_MASK 0x30 /* maximum device ID */
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#define CONFIG_BD_IHN_MASK 0x8 /* boot detector inhibit */
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#define CONFIG_INTLV_MASK 0x4 /* interleave. 0=interleave-1, 1=interleave-2 */
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#define NoutputControl 0x100C /* Output Control register. read/write */
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#define OUT_CNTRL_BSY_DISABLE_MASK 0xfe /* busy enable . 1=enable assertion of the BUSY# output */
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#define OUT_CNTRL_STICKY_BIT_ENABLE 0x8 /* sticky bit . 8=prevent key insertion */
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#define NinterruptControl 0x100E /* Interrupt Control register. read/write */
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#define INTR_IRQ_P_MASK 0x40 /* interrupt request on protection violation */
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#define INTR_IRQ_F_MASK 0x20 /* interrupt request on FREADY */
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#define INTR_EDGE_MASK 0x10 /* edge/level interrupt. 1=edge */
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#define INTR_PROT_T_MASK 0x8 /* protection trigger */
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#define INTR_FRDY_T_MASK 0x7 /* flash ready trigger */
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#define NoutputEnableDelay 0x1012 /* Output Enable Delay register. read/write */
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#define NslowIO 0x101E /* Flash Slow Read register[1:0]. read only */
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#define NflashControl 0x1020 /* Flash Control Register. read write */
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#define FLS_FR_B_MASK 0xc0 /* flash ready/busy for 2 byte lanes*/
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#define FLS_FR_B_EVEN_MASK 0x40 /* flash ready/busy for even lane*/
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#define FLS_FR_B_ODD_MASK 0x80 /* flash ready/busy for odd lane*/
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#define FLS_ALE_MASK 0x4 /* address latch enable */
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#define FLS_CLE_MASK 0x2 /* command latch enable */
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#define NflashSelect 0x1022 /* Flash Select register. read write */
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#define MPLUS_SEL_CE 0x80 /* chip enable */
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#define MPLUS_SEL_WP 0x60 /* write protect*/
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#define FLS_SEL_BANK_MASK 0x2 /* select flash bank to access */
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#define FLS_SEL_BYTE_L_MASK 0x1 /* select flash device of the bankbyte lane*/
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/* The default for MDOCP is the following combination:
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a) Send chip enable. - 0x80
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b) Lower write protect. - 0x40
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c) Select chip bank 0 chip 0 - 0 for bits 0-5 */
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#define FLS_SEL_DEFAULT 0x80
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#define NflashCommand 0x1024 /*Flash Command register. write only */
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#define NflashAddress 0x1026 /* Flash Address register. write only */
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#define NflashData 0x1028 /* Flash Data Register[1:0]. read/write */
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#define NreadPipeInit 0x102A /* Read Pipeline Initialization register. read only */
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#define NreadLastData_1 0x102C /* Last Data Read register. read only */
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#define NreadLastData_2 0x102D /* Last Data Read register. read only */
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#define NwritePipeTerm 0x102E /*Write Pipeline Termination register. write only */
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#define Nsyndrom 0x1040 /*ECC Syndrome register[5:0]. read only */
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#define NECCcontrol 0x1046 /*ECC Control register. read/write */
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#define ECC_CNTRL_ERROR_MASK 0x80 /*EDC error detection */
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#define ECC_CNTRL_ECC_RW_MASK 0x20 /* ECC read/write. 1=ECC in write mode*/
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#define ECC_CNTRL_ECC_EN_MASK 0x8 /* ECC enable */
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#define ECC_CNTRL_TOGGLE_MASK 0x4 /* identify presence of MDOC*/
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#define ECC_CNTRL_IGNORE_MASK 0x1 /* ignore the ECC unit*/
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#define ECC_RESET 0 /* reset the ECC */
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#define NcustomerOTPptr 0x1048 /* Customer OTP Pointer register. read only*/
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#define NflashGeometry 0x105A /* Flash Geometry register. read only */
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#define NdownloadStatus 0x1074 /*Download status register. read only*/
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#define DWN_STAT_IPL_ERR 0x30
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#define DWN_STAT_IPL_INVALID 0x20
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#define DWN_STAT_IPL_1_ERR 0x10
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#define DWN_STAT_OTP_ERR 0x40 /* */
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#define DWN_STAT_DPS1_ERR 0xc
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#define DWN_STAT_DPS0_ERR 0x3
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#define DWN_STAT_DPS10_ERR 0x4
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#define DWN_STAT_DPS11_ERR 0x8
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#define DWN_STAT_DPS00_ERR 0x1
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#define DWN_STAT_DPS01_ERR 0x2
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#define DWN_STAT_DWLD_ERR 0x4a /* otp + all 4 copies of dps */
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#define NprotectionStatus 0x1078 /*Protection Status register. read only*/
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#define PROTECT_STAT_ACCERR 0x80
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#define PROTECT_STAT_LOCK_INPUT_MASK 0x10
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#define PROTECT_STAT_4BA_MASK 0x8
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#define PROTECT_STAT_COTPL_MASK 0x4
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#define PROTECT_STAT_BUC_MASK 0x2
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#define PROTECT_STAT_FOTPL_MASK 0x1
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#define NfoudaryTest 0x107E /* Foundry Test register. write only */
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#define FOUNDRY_WRITE_ENABLE 0xc3
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#define FOUNDRY_DNLD_MASK 0x80
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#define NreleasePowerDown 0x1FFF /* Release from power down. */
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#endif /* MDOCPLUS */
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