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754 lines
26 KiB
754 lines
26 KiB
/*++
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Copyright (c) Microsoft Corporation. All rights reserved.
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Module Name:
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parallel.h
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Abstract:
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This file defines the services supplied by the ParPort driver.
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Author:
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norbertk
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Revision History:
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--*/
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#ifndef _PARALLEL_
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#define _PARALLEL_
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#include <ntddpar.h>
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//
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// Define the parallel port device name strings.
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//
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#define DD_PARALLEL_PORT_BASE_NAME_U L"ParallelPort"
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//
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// IEEE 1284.3 Daisy Chain (DC) Device ID's range from 0 to 3. Devices
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// are identified based on their connection order in the daisy chain
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// relative to the other 1284.3 DC devices. Device 0 is the 1284.3 DC
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// device that is closest to host port.
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//
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#define IEEE_1284_3_DAISY_CHAIN_MAX_ID 3
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//
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// NtDeviceIoControlFile internal IoControlCode values for parallel device.
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//
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// Legacy - acquires entire parallel "bus"
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#define IOCTL_INTERNAL_PARALLEL_PORT_ALLOCATE CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 11, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_INTERNAL_GET_PARALLEL_PORT_INFO CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 12, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_INTERNAL_PARALLEL_CONNECT_INTERRUPT CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 13, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_INTERNAL_PARALLEL_DISCONNECT_INTERRUPT CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 14, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_INTERNAL_RELEASE_PARALLEL_PORT_INFO CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 15, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_INTERNAL_GET_MORE_PARALLEL_PORT_INFO CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 17, METHOD_BUFFERED, FILE_ANY_ACCESS)
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// Saves current chipset mode - puts the chipset into Specified mode (implemented in filter)
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#define IOCTL_INTERNAL_PARCHIP_CONNECT CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 18, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_INTERNAL_PARALLEL_SET_CHIP_MODE CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 19, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_INTERNAL_PARALLEL_CLEAR_CHIP_MODE CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 20, METHOD_BUFFERED, FILE_ANY_ACCESS)
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// New parport IOCTLs
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#define IOCTL_INTERNAL_GET_PARALLEL_PNP_INFO CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 21, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_INTERNAL_INIT_1284_3_BUS CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 22, METHOD_BUFFERED, FILE_ANY_ACCESS)
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// Takes a flat namespace Id for the device, also acquires the port
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#define IOCTL_INTERNAL_SELECT_DEVICE CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 23, METHOD_BUFFERED, FILE_ANY_ACCESS)
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// Takes a flat namespace Id for the device, also releases the port
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#define IOCTL_INTERNAL_DESELECT_DEVICE CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 24, METHOD_BUFFERED, FILE_ANY_ACCESS)
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// New parclass IOCTLs
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#define IOCTL_INTERNAL_GET_PARPORT_FDO CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 29, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_INTERNAL_PARCLASS_CONNECT CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 30, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_INTERNAL_PARCLASS_DISCONNECT CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 31, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_INTERNAL_DISCONNECT_IDLE CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 32, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_INTERNAL_LOCK_PORT CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 37, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_INTERNAL_UNLOCK_PORT CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 38, METHOD_BUFFERED, FILE_ANY_ACCESS)
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// IOCTL version of call to ParPort's FreePort function
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#define IOCTL_INTERNAL_PARALLEL_PORT_FREE CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 40, METHOD_BUFFERED, FILE_ANY_ACCESS)
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// IOCTLs for IEEE1284.3
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#define IOCTL_INTERNAL_PARDOT3_CONNECT CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 41, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_INTERNAL_PARDOT3_DISCONNECT CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 42, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_INTERNAL_PARDOT3_RESET CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 43, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_INTERNAL_PARDOT3_SIGNAL CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 44, METHOD_BUFFERED, FILE_ANY_ACCESS)
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//
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// IOCTLs for registering/unregistering for ParPort's RemovalRelations
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//
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// - A device object should register for removal relations with a
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// parport device if the device is physically connected to the
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// parallel port.
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//
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// - Parport will report all devices that have registered with it for
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// removal relations in response to a PnP QUERY_DEVICE_RELATIONS of
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// type RemovalRelations. This allows PnP to remove all device stacks
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// that depend on the parport device prior to removing the parport
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// device itself.
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//
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// - The single Input parameter is a PARPORT_REMOVAL_RELATIONS
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// structure that is defined below
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//
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#define IOCTL_INTERNAL_REGISTER_FOR_REMOVAL_RELATIONS CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 50, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_INTERNAL_UNREGISTER_FOR_REMOVAL_RELATIONS CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 51, METHOD_BUFFERED, FILE_ANY_ACCESS)
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typedef struct _PARPORT_REMOVAL_RELATIONS {
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PDEVICE_OBJECT DeviceObject; // device object that is registering w/Parport
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ULONG Flags; // Flags - reserved - set to 0 for now
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PUNICODE_STRING DeviceName; // DeviceName identifier of device registering for removal relations - used for debugging
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// - printed in parport's debug spew - convention is to use same DeviceName that was passed to
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// IoCreateDevice
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} PARPORT_REMOVAL_RELATIONS, *PPARPORT_REMOVAL_RELATIONS;
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#define IOCTL_INTERNAL_LOCK_PORT_NO_SELECT CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 52, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_INTERNAL_UNLOCK_PORT_NO_DESELECT CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 53, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_INTERNAL_DISABLE_END_OF_CHAIN_BUS_RESCAN CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 54, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_INTERNAL_ENABLE_END_OF_CHAIN_BUS_RESCAN CTL_CODE(FILE_DEVICE_PARALLEL_PORT, 55, METHOD_BUFFERED, FILE_ANY_ACCESS)
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// Define 1284.3 command qualifiers
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#define MODE_LEN_1284_3 7 // # of magic sequence bytes
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static UCHAR ModeQualifier[MODE_LEN_1284_3] = { 0xAA, 0x55, 0x00, 0xFF, 0x87, 0x78, 0xFF };
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#define LEGACYZIP_MODE_LEN 3
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static UCHAR LegacyZipModeQualifier[LEGACYZIP_MODE_LEN] = { 0x00, 0x3c, 0x20 };
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typedef enum {
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P12843DL_OFF,
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P12843DL_DOT3_DL,
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P12843DL_MLC_DL,
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P12843DL_DOT4_DL
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} P12843_DL_MODES;
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// Define 1284.3 Commands
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#define CPP_ASSIGN_ADDR 0x00
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#define CPP_SELECT 0xE0
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#define CPP_DESELECT 0x30
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#define CPP_QUERY_INT 0x08
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#define CPP_DISABLE_INT 0x40
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#define CPP_ENABLE_INT 0x48
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#define CPP_CLEAR_INT_LAT 0x50
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#define CPP_SET_INT_LAT 0x58
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#define CPP_COMMAND_FILTER 0xF8
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typedef
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BOOLEAN
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(*PPARALLEL_TRY_ALLOCATE_ROUTINE) (
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IN PVOID TryAllocateContext
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);
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typedef
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VOID
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(*PPARALLEL_FREE_ROUTINE) (
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IN PVOID FreeContext
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);
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typedef
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ULONG
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(*PPARALLEL_QUERY_WAITERS_ROUTINE) (
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IN PVOID QueryAllocsContext
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);
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typedef
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NTSTATUS
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(*PPARALLEL_SET_CHIP_MODE) (
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IN PVOID SetChipContext,
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IN UCHAR ChipMode
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);
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typedef
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NTSTATUS
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(*PPARALLEL_CLEAR_CHIP_MODE) (
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IN PVOID ClearChipContext,
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IN UCHAR ChipMode
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);
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typedef
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NTSTATUS
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(*PPARALLEL_TRY_SELECT_ROUTINE) (
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IN PVOID TrySelectContext,
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IN PVOID TrySelectCommand
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);
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typedef
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NTSTATUS
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(*PPARALLEL_DESELECT_ROUTINE) (
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IN PVOID DeselectContext,
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IN PVOID DeselectCommand
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);
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typedef
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NTSTATUS
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(*PPARCHIP_SET_CHIP_MODE) (
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IN PVOID SetChipContext,
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IN UCHAR ChipMode
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);
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typedef
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NTSTATUS
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(*PPARCHIP_CLEAR_CHIP_MODE) (
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IN PVOID ClearChipContext,
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IN UCHAR ChipMode
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);
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//
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// Hardware Capabilities
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//
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#define PPT_NO_HARDWARE_PRESENT 0x00000000
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#define PPT_ECP_PRESENT 0x00000001
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#define PPT_EPP_PRESENT 0x00000002
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#define PPT_EPP_32_PRESENT 0x00000004
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#define PPT_BYTE_PRESENT 0x00000008
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#define PPT_BIDI_PRESENT 0x00000008 // deprecated - will be removed soon! dvdf
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#define PPT_1284_3_PRESENT 0x00000010
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// Added DVDR 10-6-98
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// Structure passed to the ParChip Filter when calling it
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// with the IOCTL_INTERNAL_CHIP_FILTER_CONNECT ioctl
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typedef struct _PARALLEL_PARCHIP_INFO {
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PUCHAR Controller;
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PUCHAR EcrController;
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ULONG HardwareModes;
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PPARCHIP_SET_CHIP_MODE ParChipSetMode;
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PPARCHIP_CLEAR_CHIP_MODE ParChipClearMode;
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PVOID Context;
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BOOLEAN success;
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} PARALLEL_PARCHIP_INFO, *PPARALLEL_PARCHIP_INFO;
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// End Added by DVDR 10-6-1998
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typedef struct _PARALLEL_PORT_INFORMATION {
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PHYSICAL_ADDRESS OriginalController;
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PUCHAR Controller;
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ULONG SpanOfController;
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PPARALLEL_TRY_ALLOCATE_ROUTINE TryAllocatePort; // nonblocking callback to allocate port
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PPARALLEL_FREE_ROUTINE FreePort; // callback to free port
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PPARALLEL_QUERY_WAITERS_ROUTINE QueryNumWaiters; // callback to query number of waiters for port allocation
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PVOID Context; // context for callbacks to ParPort device
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} PARALLEL_PORT_INFORMATION, *PPARALLEL_PORT_INFORMATION;
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typedef struct _PARALLEL_PNP_INFORMATION {
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PHYSICAL_ADDRESS OriginalEcpController;
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PUCHAR EcpController;
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ULONG SpanOfEcpController;
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ULONG PortNumber; // deprecated - do not use
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ULONG HardwareCapabilities;
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PPARALLEL_SET_CHIP_MODE TrySetChipMode;
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PPARALLEL_CLEAR_CHIP_MODE ClearChipMode;
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ULONG FifoDepth;
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ULONG FifoWidth;
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PHYSICAL_ADDRESS EppControllerPhysicalAddress;
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ULONG SpanOfEppController;
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ULONG Ieee1284_3DeviceCount; // number of .3 daisy chain devices connected to this ParPort
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PPARALLEL_TRY_SELECT_ROUTINE TrySelectDevice;
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PPARALLEL_DESELECT_ROUTINE DeselectDevice;
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PVOID Context;
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ULONG CurrentMode;
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PWSTR PortName; // symbolic link name for legacy device object
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} PARALLEL_PNP_INFORMATION, *PPARALLEL_PNP_INFORMATION;
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// Start Added by DVDR 2-19-1998
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//
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// PARALLEL_1284_COMMAND CommandFlags
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//
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// this flag is deprecated - use 1284.3 daisy chain ID == 4 to indicate End-Of-Chain device
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#define PAR_END_OF_CHAIN_DEVICE ((ULONG)0x00000001) // The target device for this command
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// is an End-Of-Chain device, the
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// contents of the ID field are
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// undefined and should be ignored
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#define PAR_HAVE_PORT_KEEP_PORT ((ULONG)0x00000002) // Indicates that the requesting driver
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// has previously acquired the parallel port
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// and does is not ready to release it yet.
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//
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// On a SELECT_DEVICE ParPort should NOT
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// try to acquire the port before selecting
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// the device.
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//
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// On a DESELECT_DEVICE ParPort should NOT
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// free the port after deselecting the device.
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#define PAR_LEGACY_ZIP_DRIVE ((ULONG)0x00000004) // The target device for this command
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// is a Legacy Iomega Zip drive, the
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// contents of the ID field are
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// undefined and should be ignored
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#define PAR_LEGACY_ZIP_DRIVE_STD_MODE ((ULONG)0x00000010) // The target device for these commands
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#define PAR_LEGACY_ZIP_DRIVE_EPP_MODE ((ULONG)0x00000020) // are a Legacy Iomega Zip drive, the
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// contents of the ID field are
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// undefined and should be ignored
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// This will select the Zip into DISK or EPP Mode
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#define DOT3_END_OF_CHAIN_ID 4 // this ID used in a 1284.3 SELECT or DESELECT means the End-Of-Chain device
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#define DOT3_LEGACY_ZIP_ID 5 // this ID used in a 1284.3 SELECT or DESELECT means Legacy Zip drive
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//
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// The following structure is passed in on an
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// IOCTL_INTERNAL_SELECT_DEVICE and on an
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// IOCTL_INTERNAL_DESELECT_DEVICE
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typedef struct _PARALLEL_1284_COMMAND {
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UCHAR ID; // 0..3 for 1284.3 daisy chain device, 4 for End-Of-Chain device, 5 for Legacy Zip
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UCHAR Port; // reserved ( set == 0 )
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ULONG CommandFlags; // see above
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} PARALLEL_1284_COMMAND, *PPARALLEL_1284_COMMAND;
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//
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// Hardware Modes
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//
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#define INITIAL_MODE 0x00000000
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// Disable Parchip and ECR arbitrator
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// 0 - Parchip and ecr arbritrator is off
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// 1 - Parchip and ecr arbitrator is on
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#define PARCHIP_ECR_ARBITRATOR 1
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//
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// The following structure is passed in on an
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// IOCTL_INTERNAL_PARALLEL_SET_CHIP_MODE and on an
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// IOCTL_INTERNAL_PARALLEL_CLEAR_CHIP_MODE
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//
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typedef struct _PARALLEL_CHIP_MODE {
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UCHAR ModeFlags;
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BOOLEAN success;
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} PARALLEL_CHIP_MODE, *PPARALLEL_CHIP_MODE;
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// End Added by DVDR 2-19-1998
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//
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// The following structure is passed in on an
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// IOCTL_INTERNAL_PARALLEL_CONNECT_INTERRUPT and on an
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// IOCTL_INTERNAL_PARALLEL_DISCONNECT_INTERRUPT request.
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//
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typedef
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VOID
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(*PPARALLEL_DEFERRED_ROUTINE) (
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IN PVOID DeferredContext
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);
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typedef struct _PARALLEL_INTERRUPT_SERVICE_ROUTINE {
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PKSERVICE_ROUTINE InterruptServiceRoutine;
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PVOID InterruptServiceContext;
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PPARALLEL_DEFERRED_ROUTINE DeferredPortCheckRoutine; /* OPTIONAL */
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PVOID DeferredPortCheckContext; /* OPTIONAL */
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} PARALLEL_INTERRUPT_SERVICE_ROUTINE, *PPARALLEL_INTERRUPT_SERVICE_ROUTINE;
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//
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// The following structure is returned on an
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// IOCTL_INTERNAL_PARALLEL_CONNECT_INTERRUPT request;
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//
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typedef struct _PARALLEL_INTERRUPT_INFORMATION {
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PKINTERRUPT InterruptObject;
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PPARALLEL_TRY_ALLOCATE_ROUTINE TryAllocatePortAtInterruptLevel;
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PPARALLEL_FREE_ROUTINE FreePortFromInterruptLevel;
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PVOID Context;
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} PARALLEL_INTERRUPT_INFORMATION, *PPARALLEL_INTERRUPT_INFORMATION;
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//
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// The following structure is returned on an
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// IOCTL_INTERNAL_GET_MORE_PARALLEL_PORT_INFO.
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//
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typedef struct _MORE_PARALLEL_PORT_INFORMATION {
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INTERFACE_TYPE InterfaceType;
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ULONG BusNumber;
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ULONG InterruptLevel;
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ULONG InterruptVector;
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KAFFINITY InterruptAffinity;
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KINTERRUPT_MODE InterruptMode;
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} MORE_PARALLEL_PORT_INFORMATION, *PMORE_PARALLEL_PORT_INFORMATION;
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typedef enum {
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SAFE_MODE,
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UNSAFE_MODE // Available only through kernel. Your driver
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// will be humiliated if you choose UNSAFE_MODE and
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// then "make a mistake". - dvrh (PCized by dvdf)
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} PARALLEL_SAFETY;
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//
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// The following structure is returned by
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// IOCTL_INTERNAL_PARCLASS_CONNECT.
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//
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typedef
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USHORT
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(*PDETERMINE_IEEE_MODES) (
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IN PVOID Context
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);
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#define OLD_PARCLASS 0
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#if OLD_PARCLASS
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typedef
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NTSTATUS
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(*PNEGOTIATE_IEEE_MODE) (
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IN PVOID Extension,
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IN UCHAR Extensibility
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);
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#else
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typedef
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NTSTATUS
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(*PNEGOTIATE_IEEE_MODE) (
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IN PVOID Context,
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IN USHORT ModeMaskFwd,
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IN USHORT ModeMaskRev,
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IN PARALLEL_SAFETY ModeSafety,
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IN BOOLEAN IsForward
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);
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#endif
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typedef
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NTSTATUS
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(*PTERMINATE_IEEE_MODE) (
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IN PVOID Context
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);
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typedef
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NTSTATUS
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(*PPARALLEL_IEEE_FWD_TO_REV)(
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IN PVOID Context
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);
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typedef
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NTSTATUS
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(*PPARALLEL_IEEE_REV_TO_FWD)(
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IN PVOID Context
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);
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typedef
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NTSTATUS
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(*PPARALLEL_READ) (
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IN PVOID Context,
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OUT PVOID Buffer,
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IN ULONG NumBytesToRead,
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OUT PULONG NumBytesRead,
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IN UCHAR Channel
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);
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typedef
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NTSTATUS
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(*PPARALLEL_WRITE) (
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IN PVOID Context,
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OUT PVOID Buffer,
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IN ULONG NumBytesToWrite,
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OUT PULONG NumBytesWritten,
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IN UCHAR Channel
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);
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typedef
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NTSTATUS
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(*PPARALLEL_TRYSELECT_DEVICE) (
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IN PVOID Context,
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IN PARALLEL_1284_COMMAND Command
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);
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typedef
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NTSTATUS
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(*PPARALLEL_DESELECT_DEVICE) (
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IN PVOID Context,
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IN PARALLEL_1284_COMMAND Command
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);
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typedef struct _PARCLASS_INFORMATION {
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PUCHAR Controller;
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PUCHAR EcrController;
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ULONG SpanOfController;
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PDETERMINE_IEEE_MODES DetermineIeeeModes;
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PNEGOTIATE_IEEE_MODE NegotiateIeeeMode;
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PTERMINATE_IEEE_MODE TerminateIeeeMode;
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PPARALLEL_IEEE_FWD_TO_REV IeeeFwdToRevMode;
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PPARALLEL_IEEE_REV_TO_FWD IeeeRevToFwdMode;
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PPARALLEL_READ ParallelRead;
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PPARALLEL_WRITE ParallelWrite;
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PVOID ParclassContext;
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ULONG HardwareCapabilities;
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ULONG FifoDepth;
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ULONG FifoWidth;
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PPARALLEL_TRYSELECT_DEVICE ParallelTryselect;
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PPARALLEL_DESELECT_DEVICE ParallelDeSelect;
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} PARCLASS_INFORMATION, *PPARCLASS_INFORMATION;
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//
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// Standard and ECP parallel port offsets.
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//
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#define DATA_OFFSET 0
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#define OFFSET_ECP_AFIFO 0x0000 // ECP Mode Address FIFO
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#define AFIFO_OFFSET OFFSET_ECP_AFIFO // ECP Mode Address FIFO
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#define DSR_OFFSET 1
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#define DCR_OFFSET 2
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#define EPP_OFFSET 4
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// default to the old defines - note that the old defines break on PCI cards
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#ifndef DVRH_USE_PARPORT_ECP_ADDR
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#define DVRH_USE_PARPORT_ECP_ADDR 0
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#endif
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// DVRH_USE_PARPORT_ECP_ADDR settings
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// 0 - ECP registers are hardcoded to
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// Controller + 0x400
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// 1 - ECP registers are pulled from
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// Parport which hopefully got
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// them from PnP.
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#if (0 == DVRH_USE_PARPORT_ECP_ADDR)
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// ***Note: These do not hold for PCI parallel ports
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#define ECP_OFFSET 0x400
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#define CNFGB_OFFSET 0x401
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#define ECR_OFFSET 0x402
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#else
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#define ECP_OFFSET 0x0
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#define CNFGB_OFFSET 0x1
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#define ECR_OFFSET 0x2
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#endif
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#define FIFO_OFFSET ECP_OFFSET
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#define CFIFO_OFFSET ECP_OFFSET
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#define CNFGA_OFFSET ECP_OFFSET
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#define ECP_DFIFO_OFFSET ECP_OFFSET // ECP Mode Data FIFO
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#define TFIFO_OFFSET ECP_OFFSET
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#define OFFSET_ECP_DFIFO ECP_OFFSET // ECP Mode Data FIFO
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#define OFFSET_TFIFO ECP_OFFSET // Test FIFO
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#define OFFSET_CFIFO ECP_OFFSET // Fast Centronics Data FIFO
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#define OFFSET_ECR ECR_OFFSET // Extended Control Register
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#define OFFSET_PARALLEL_REGISTER_SPAN 0x0003
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#define ECP_SPAN 3
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#define EPP_SPAN 4
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//
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// Bit definitions for the DSR.
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//
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#define DSR_NOT_BUSY 0x80
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#define DSR_NOT_ACK 0x40
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#define DSR_PERROR 0x20
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#define DSR_SELECT 0x10
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#define DSR_NOT_FAULT 0x08
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//
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// More bit definitions for the DSR.
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//
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#define DSR_NOT_PTR_BUSY 0x80
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#define DSR_NOT_PERIPH_ACK 0x80
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#define DSR_WAIT 0x80
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#define DSR_PTR_CLK 0x40
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#define DSR_PERIPH_CLK 0x40
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#define DSR_INTR 0x40
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#define DSR_ACK_DATA_REQ 0x20
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#define DSR_NOT_ACK_REVERSE 0x20
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#define DSR_XFLAG 0x10
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#define DSR_NOT_DATA_AVAIL 0x08
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#define DSR_NOT_PERIPH_REQUEST 0x08
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//
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// Bit definitions for the DCR.
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//
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#define DCR_RESERVED 0xC0
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#define DCR_DIRECTION 0x20
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#define DCR_ACKINT_ENABLED 0x10
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#define DCR_SELECT_IN 0x08
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#define DCR_NOT_INIT 0x04
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#define DCR_AUTOFEED 0x02
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#define DCR_STROBE 0x01
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//
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// More bit definitions for the DCR.
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//
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#define DCR_NOT_1284_ACTIVE 0x08
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#define DCR_ASTRB 0x08
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#define DCR_NOT_REVERSE_REQUEST 0x04
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#define DCR_NULL 0x04
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#define DCR_NOT_HOST_BUSY 0x02
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#define DCR_NOT_HOST_ACK 0x02
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#define DCR_DSTRB 0x02
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#define DCR_NOT_HOST_CLK 0x01
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#define DCR_WRITE 0x01
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//
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// Bit definitions for configuration register A.
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//
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#define CNFGA_IMPID_MASK 0x70
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#define CNFGA_IMPID_16BIT 0x00
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#define CNFGA_IMPID_8BIT 0x10
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#define CNFGA_IMPID_32BIT 0x20
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#define CNFGA_NO_TRANS_BYTE 0x04
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////////////////////////////////////////////////////////////////////////////////
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// ECR values that establish basic hardware modes. In each case, the default
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// is to disable error interrupts, DMA, and service interrupts.
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////////////////////////////////////////////////////////////////////////////////
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#if (0 == PARCHIP_ECR_ARBITRATOR)
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#define DEFAULT_ECR_PS2 0x34
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#define DEFAULT_ECR_ECP 0x74
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#endif
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//
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// Bit definitions for ECR register.
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//
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#define ECR_ERRINT_DISABLED 0x10
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#define ECR_DMA_ENABLED 0x08
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#define ECR_SVC_INT_DISABLED 0x04
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#define ECR_MODE_MASK 0x1F
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#define ECR_SPP_MODE 0x00
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#define ECR_BYTE_MODE 0x20 // PS/2
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#define ECR_BYTE_PIO_MODE (ECR_BYTE_MODE | ECR_ERRINT_DISABLED | ECR_SVC_INT_DISABLED)
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#define ECR_FASTCENT_MODE 0x40
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#define ECR_ECP_MODE 0x60
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#define ECR_ECP_PIO_MODE (ECR_ECP_MODE | ECR_ERRINT_DISABLED | ECR_SVC_INT_DISABLED)
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#define ECR_EPP_MODE 0x80
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#define ECR_EPP_PIO_MODE (ECR_EPP_MODE | ECR_ERRINT_DISABLED | ECR_SVC_INT_DISABLED)
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#define ECR_RESERVED_MODE 0x10
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#define ECR_TEST_MODE 0xC0
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#define ECR_CONFIG_MODE 0xE0
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#define DEFAULT_ECR_TEST 0xD4
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#define DEFAULT_ECR_COMPATIBILITY 0x14
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#define DEFAULT_ECR_CONFIGURATION 0xF4
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#define ECR_FIFO_MASK 0x03 // Mask to isolate FIFO bits
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#define ECR_FIFO_FULL 0x02 // FIFO completely full
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#define ECR_FIFO_EMPTY 0x01 // FIFO completely empty
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#define ECR_FIFO_SOME_DATA 0x00 // FIFO has some data in it
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#define ECP_MAX_FIFO_DEPTH 4098 // Likely max for ECP HW FIFO size
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//------------------------------------------------------------------------
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// Mask and test values for extracting the Implementation ID from the
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// ConfigA register
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//------------------------------------------------------------------------
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#define CNFGA_IMPID_MASK 0x70
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#define CNFGA_IMPID_SHIFT 4
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#define FIFO_PWORD_8BIT 1
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#define FIFO_PWORD_16BIT 0
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#define FIFO_PWORD_32BIT 2
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#define TEST_ECR_FIFO(registerValue,testValue) \
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( ( (registerValue) & ECR_FIFO_MASK ) == testValue )
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//////////////////////////////////////////////////////////////////////////////
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// The following BIT_x definitions provide a generic bit shift value
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// based upon the bit's position in a hardware register or byte of
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// memory. These constants are used by some of the macros that are
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// defined below.
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//////////////////////////////////////////////////////////////////////////////
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#define BIT_7 7
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#define BIT_6 6
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#define BIT_5 5
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#define BIT_4 4
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#define BIT_3 3
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#define BIT_2 2
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#define BIT_1 1
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#define BIT_0 0
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#define BIT_7_SET 0x80
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#define BIT_6_SET 0x40
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#define BIT_5_SET 0x20
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#define BIT_4_SET 0x10
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#define BIT_3_SET 0x8
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#define BIT_2_SET 0x4
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#define BIT_1_SET 0x2
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#define BIT_0_SET 0x1
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//////////////////////////////////////////////////////////////////////////////
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// The following defines and macros may be used to set, test, and
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// update the Device Control Register (DCR).
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//////////////////////////////////////////////////////////////////////////////
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#define DIR_READ 1
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#define DIR_WRITE 0
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#define IRQEN_ENABLE 1
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#define IRQEN_DISABLE 0
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#define ACTIVE 1
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#define INACTIVE 0
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#define DONT_CARE 2
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#define DVRH_USE_FAST_MACROS 1
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#define DVRH_USE_NIBBLE_MACROS 1
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//////////////////////////////////////////////////////////////////////////////
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// The following defines may be used generically in any of the SET_xxx,
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// TEST_xxx, or UPDATE_xxx macros that follow.
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//////////////////////////////////////////////////////////////////////////////
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#if (1 == DVRH_USE_FAST_MACROS)
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#define SET_DCR(b5,b4,b3,b2,b1,b0) \
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((UCHAR)((b5==ACTIVE? BIT_5_SET : 0) | \
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(b4==ACTIVE? BIT_4_SET : 0) | \
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(b3==ACTIVE? 0 : BIT_3_SET) | \
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(b2==ACTIVE? BIT_2_SET : 0) | \
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(b1==ACTIVE? 0 : BIT_1_SET) | \
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(b0==ACTIVE? 0 : BIT_0_SET) ) )
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#else
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#define SET_DCR(b5,b4,b3,b2,b1,b0) \
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((UCHAR)(((b5==ACTIVE?1:0)<<BIT_5) | \
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((b4==ACTIVE?1:0)<<BIT_4) | \
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((b3==ACTIVE?0:1)<<BIT_3) | \
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((b2==ACTIVE?1:0)<<BIT_2) | \
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((b1==ACTIVE?0:1)<<BIT_1) | \
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((b0==ACTIVE?0:1)<<BIT_0) ) )
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#endif
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typedef enum {
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PHASE_UNKNOWN,
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PHASE_NEGOTIATION,
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PHASE_SETUP, // Used in ECP mode only
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PHASE_FORWARD_IDLE,
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PHASE_FORWARD_XFER,
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PHASE_FWD_TO_REV,
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PHASE_REVERSE_IDLE,
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PHASE_REVERSE_XFER,
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PHASE_REV_TO_FWD,
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PHASE_TERMINATE,
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PHASE_DATA_AVAILABLE, // Used in nibble and byte modes only
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PHASE_DATA_NOT_AVAIL, // Used in nibble and byte modes only
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PHASE_INTERRUPT_HOST // Used in nibble and byte modes only
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} P1284_PHASE;
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typedef enum {
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HW_MODE_COMPATIBILITY,
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HW_MODE_PS2,
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HW_MODE_FAST_CENTRONICS,
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HW_MODE_ECP,
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HW_MODE_EPP,
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HW_MODE_RESERVED,
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HW_MODE_TEST,
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HW_MODE_CONFIGURATION
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} P1284_HW_MODE;
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#endif // _PARALLEL_
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